Clang: Define macro _MIPS_SPFPSET

[wzssyqa]

Summary

GCC defines this macro for how many single-precision floating point registers
can be used.

If the -mno-odd-spreg option is given, it will be 16; if either -mno-odd-spreg
nor -modd-spreg are given, we set it to 16 for FPXX.

[MaskRay]

In GCC, -mno-odd-spreg -modd-spreg affects code generation. If we don't implement the behavior, I am not sure we can define _MIPS_SPFPSET.

Actually, do we really want to define the macro? CodeSearch context:global _MIPS_SPFPSET -f:gcc|sysdeps/ (regex) gives no result.

[wzssyqa]

In D157896#4594431, @MaskRay wrote:

In GCC, -mno-odd-spreg -modd-spreg affects code generation. If we don't implement the behavior, I am not sure we can define _MIPS_SPFPSET.

Actually, do we really want to define the macro? CodeSearch context:global _MIPS_SPFPSET -f:gcc|sysdeps/ (regex) gives no result.

I am working on libunwind. I'd plan to use this macro to

In D157896#4594431, @MaskRay wrote:

In GCC, -mno-odd-spreg -modd-spreg affects code generation. If we don't implement the behavior, I am not sure we can define _MIPS_SPFPSET.

We do implement this behavior. I test with this code

float x(float a, float b) {
	return a*3+b*4;
}

The objdump result of clang -O2 -mfpxx -mno-odd-spreg -target mipsel-linux-gnu -c xx.c

00000000 <x>:
   0:	3c020000 	lui	v0,0x0
   4:	24420000 	addiu	v0,v0,0
   8:	00590821 	addu	at,v0,t9
   c:	8c220000 	lw	v0,0(at)
  10:	c4400000 	lwc1	$f0,0(v0)
  14:	46007002 	mul.s	$f0,$f14,$f0
  18:	8c210000 	lw	at,0(at)
  1c:	c4220000 	lwc1	$f2,0(at)
  20:	46026082 	mul.s	$f2,$f12,$f2
  24:	03e00008 	jr	ra
  28:	46001000 	add.s	$f0,$f2,$f0

The objdump result of clang -O2 -mfpxx -modd-spreg -target mipsel-linux-gnu -c xx.c

00000000 <x>:
   0:	3c020000 	lui	v0,0x0
   4:	24420000 	addiu	v0,v0,0
   8:	00590821 	addu	at,v0,t9
   c:	8c220000 	lw	v0,0(at)
  10:	c4400000 	lwc1	$f0,0(v0)
  14:	46007002 	mul.s	$f0,$f14,$f0
  18:	8c210000 	lw	at,0(at)
  1c:	c4210000 	lwc1	$f1,0(at)
  20:	46016042 	mul.s	$f1,$f12,$f1
  24:	03e00008 	jr	ra
  28:	46000800 	add.s	$f0,$f1,$f0

Actually, do we really want to define the macro? CodeSearch context:global _MIPS_SPFPSET -f:gcc|sysdeps/ (regex) gives no result.

I am working on libunwind to support both FP64 (-mfp64), and FPXX (-mfpxx -mno-odd-spreg).
It will need this macro.

1. if __mips_fpr == 64, all 32 64bit FPR can be read/write with getFloatRegister, setFloatRegister.
2. if __mips_fpr != 64, and _MIPS_SPFPSET==32, which means -modd-spreg is used, we should just reject to compile.
3. if __mips_fpr != 64 and _MIPS_SPFPSET==16, which means -mno-odd-spreg is used. we can support it. if the argument is even-FPR, we just do the request, and if it's odd-FPR, _LIBUNWIND_ABORT can be used to reject it.

[theraven]

Looks fine to me, though I’ve never seen code using this macro. For a single (not yet implemented) consumer I’m not certain it’s worth putting in the compiler since the same place in the build system that adds the flag directing code generation can also add a -D flag.

[wzssyqa]

In D157896#4630236, @theraven wrote:

Looks fine to me, though I’ve never seen code using this macro. For a single (not yet implemented) consumer I’m not certain it’s worth putting in the compiler since the same place in the build system that adds the flag directing code generation can also add a -D flag.

I add this macro, as I plan to use it for libunwind.
Since the float point will quite different then.

clang/lib/Basic/Targets/Mips.h

   bool HasMSA;
   bool DisableMadd4;
   bool UseIndirectJumpHazard;
+  bool NoOddSpreg;
 
 protected:
   enum FPModeEnum { FPXX, FP32, FP64 } FPMode;

     FloatABI = HardFloat;
     DspRev = NoDSP;
     FPMode = isFP64Default() ? FP64 : FPXX;
+    NoOddSpreg = false;
+    bool OddSpregGiven = false;
 
     for (const auto &Feature : Features) {
       if (Feature == "+single-float")

         IsNoABICalls = true;
       else if (Feature == "+use-indirect-jump-hazard")
         UseIndirectJumpHazard = true;
+      else if (Feature == "+nooddspreg") {
+        NoOddSpreg = true;
+        OddSpregGiven = false;
+      } else if (Feature == "-nooddspreg") {
+        NoOddSpreg = false;
+        OddSpregGiven = true;
+      }
     }
 
+    if (FPMode == FPXX && !OddSpregGiven)
+      NoOddSpreg = true;
+
     setDataLayout();
 
     return true;

clang/lib/Basic/Targets/Mips.cpp

     Builder.defineMacro("_MIPS_FPSET", Twine(32));
   else
     Builder.defineMacro("_MIPS_FPSET", Twine(16));
+  if (NoOddSpreg)
+    Builder.defineMacro("_MIPS_SPFPSET", Twine(16));
+  else
+    Builder.defineMacro("_MIPS_SPFPSET", Twine(32));
 
   if (IsMips16)
     Builder.defineMacro("__mips16", Twine(1));

clang/test/Preprocessor/init-mips.c

 // MIPS32BE:#define _MIPS_ARCH_MIPS32R2 1
 // MIPS32BE:#define _MIPS_FPSET 16
 // MIPS32BE:#define _MIPS_SIM _ABIO32
+// MIPS32BE:#define _MIPS_SPFPSET 16
 // MIPS32BE:#define _MIPS_SZINT 32
 // MIPS32BE:#define _MIPS_SZLONG 32
 // MIPS32BE:#define _MIPS_SZPTR 32

 // MIPS32EL:#define _MIPS_ARCH_MIPS32R2 1
 // MIPS32EL:#define _MIPS_FPSET 16
 // MIPS32EL:#define _MIPS_SIM _ABIO32
+// MIPS32EL:#define _MIPS_SPFPSET 16
 // MIPS32EL:#define _MIPS_SZINT 32
 // MIPS32EL:#define _MIPS_SZLONG 32
 // MIPS32EL:#define _MIPS_SZPTR 32

 // MIPSN32BE: #define _MIPS_FPSET 32
 // MIPSN32BE: #define _MIPS_ISA _MIPS_ISA_MIPS64
 // MIPSN32BE: #define _MIPS_SIM _ABIN32
+// MIPSN32BE: #define _MIPS_SPFPSET 32
 // MIPSN32BE: #define _MIPS_SZINT 32
 // MIPSN32BE: #define _MIPS_SZLONG 32
 // MIPSN32BE: #define _MIPS_SZPTR 32

 // MIPSN32EL: #define _MIPS_FPSET 32
 // MIPSN32EL: #define _MIPS_ISA _MIPS_ISA_MIPS64
 // MIPSN32EL: #define _MIPS_SIM _ABIN32
+// MIPSN32EL: #define _MIPS_SPFPSET 32
 // MIPSN32EL: #define _MIPS_SZINT 32
 // MIPSN32EL: #define _MIPS_SZLONG 32
 // MIPSN32EL: #define _MIPS_SZPTR 32

 // MIPS64BE:#define _MIPS_ARCH_MIPS64R2 1
 // MIPS64BE:#define _MIPS_FPSET 32
 // MIPS64BE:#define _MIPS_SIM _ABI64
+// MIPS64BE:#define _MIPS_SPFPSET 32
 // MIPS64BE:#define _MIPS_SZINT 32
 // MIPS64BE:#define _MIPS_SZLONG 64
 // MIPS64BE:#define _MIPS_SZPTR 64

 // MIPS64EL:#define _MIPS_ARCH_MIPS64R2 1
 // MIPS64EL:#define _MIPS_FPSET 32
 // MIPS64EL:#define _MIPS_SIM _ABI64
+// MIPS64EL:#define _MIPS_SPFPSET 32
 // MIPS64EL:#define _MIPS_SZINT 32
 // MIPS64EL:#define _MIPS_SZLONG 64
 // MIPS64EL:#define _MIPS_SZPTR 64

 // MIPS-ARCH-32R6:#define _MIPS_ARCH "mips32r6"
 // MIPS-ARCH-32R6:#define _MIPS_ARCH_MIPS32R6 1
 // MIPS-ARCH-32R6:#define _MIPS_ISA _MIPS_ISA_MIPS32
+// MIPS-ARCH-32R6:#define __mips_fpr 64
 // MIPS-ARCH-32R6:#define __mips_isa_rev 6
 
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=mips64-none-none \

 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS32-NOFP %s
 // MIPS32-NOFP:#define __mips_fpr 0
 
+// RUN: %clang_cc1  -target-feature -nooddspreg \
+// RUN:   -E -dM -triple=mips-none-none < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix MIPS32-NOFP-ODD %s
+// MIPS32-NOFP-ODD:#define _MIPS_SPFPSET 32
+// MIPS32-NOFP-ODD:#define __mips_fpr 0
+
+// RUN: %clang_cc1  -target-feature +nooddspreg -target-feature -fp64 \
+// RUN:   -E -dM -triple=mips-none-none < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix MIPS32-FP64-NOODD %s
+// MIPS32-FP64-NOODD:#define _MIPS_SPFPSET 16
+// MIPS32-FP64-NOODD:#define __mips_fpr 32
+
 // RUN: %clang_cc1 -target-feature +fpxx \
 // RUN:   -E -dM -triple=mips-none-none < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS32-MFPXX %s
+// MIPS32-MFPXX:#define _MIPS_SPFPSET 16
 // MIPS32-MFPXX:#define __mips_fpr 0
 
 // RUN: %clang_cc1 -target-cpu mips32r6 -target-feature +fpxx \
 // RUN:   -E -dM -triple=mips-none-none < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS32R6-MFPXX %s
+// MIPS32R6-MFPXX:#define _MIPS_SPFPSET 16
 // MIPS32R6-MFPXX:#define __mips_fpr 0
 
 // RUN: %clang_cc1  \

 // RUN:   -E -dM -triple=mips-none-none < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS32-MFP32 %s
 // MIPS32-MFP32:#define _MIPS_FPSET 16
+// MIPS32-MFP32:#define _MIPS_SPFPSET 32
 // MIPS32-MFP32:#define __mips_fpr 32
 
 // RUN: %clang_cc1 -target-feature +fp64 \
 // RUN:   -E -dM -triple=mips-none-none < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS32-MFP64 %s
 // MIPS32-MFP64:#define _MIPS_FPSET 32
+// MIPS32-MFP64:#define _MIPS_SPFPSET 32
 // MIPS32-MFP64:#define __mips_fpr 64
 //
 // RUN: %clang_cc1 -target-feature +single-float \
 // RUN:   -E -dM -triple=mips-none-none < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS32-MFP32SF %s
 // MIPS32-MFP32SF:#define _MIPS_FPSET 32
+// MIPS32-MFP32SF:#define _MIPS_SPFPSET 16
 // MIPS32-MFP32SF:#define __mips_fpr 0
 
 // RUN: %clang_cc1 -target-feature +fp64 \
 // RUN:   -E -dM -triple=mips64-none-none < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS64-MFP64 %s
 // MIPS64-MFP64:#define _MIPS_FPSET 32
+// MIPS64-MFP64:#define _MIPS_SPFPSET 32
 // MIPS64-MFP64:#define __mips_fpr 64
 
 // RUN: %clang_cc1 -target-feature -fp64 -target-feature +single-float \
 // RUN:   -E -dM -triple=mips64-none-none < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS64-NOMFP64 %s
 // MIPS64-NOMFP64:#define _MIPS_FPSET 32
+// MIPS64-NOMFP64:#define _MIPS_SPFPSET 32
 // MIPS64-NOMFP64:#define __mips_fpr 32
 
 // RUN: %clang_cc1 -target-cpu mips32r6 \

 // RUN:   -E -dM -triple=mips64-none-none < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefix MIPS-XXR6 %s
 // MIPS-XXR6:#define _MIPS_FPSET 32
+// MIPS-XXR6:#define _MIPS_SPFPSET 32
 // MIPS-XXR6:#define __mips_fpr 64
 // MIPS-XXR6:#define __mips_nan2008 1