[DAG] Add constant SPLAT handling in getNodes SIGN_EXTEND_INREG

[dmgreen]

Summary

This helps simplify constant splats a little. Without this the code in https://github.com/llvm/llvm-project/blob/b8e297d1af5ae42e81b4c79e14a6d2427db0311b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L14072 always returns the existing node.

[RKSimon]

LGTM

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

6617

N1.getConstantOperandAPInt(0)?

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
           continue;
         }
         ConstantSDNode *C = cast<ConstantSDNode>(Op);
         APInt Val = C->getAPIntValue();
         Ops.push_back(SignExtendInReg(Val, OpVT));
       }
       return getBuildVector(VT, DL, Ops);
     }
+
+    if (N1.getOpcode() == ISD::SPLAT_VECTOR &&
+        isa<ConstantSDNode>(N1.getOperand(0)))
+      return getNode(
+          ISD::SPLAT_VECTOR, DL, VT,
+          SignExtendInReg(cast<ConstantSDNode>(N1.getOperand(0))->getAPIntValue(),
+                          N1.getOperand(0).getValueType()));
     break;
   }
   case ISD::FP_TO_SINT_SAT:
   case ISD::FP_TO_UINT_SAT: {
     assert(VT.isInteger() && cast<VTSDNode>(N2)->getVT().isInteger() &&
            N1.getValueType().isFloatingPoint() && "Invalid FP_TO_*INT_SAT");
     assert(N1.getValueType().isVector() == VT.isVector() &&
            "FP_TO_*INT_SAT type should be vector iff the operand type is "

llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64 -mattr=+sve %s -o - | FileCheck %s
 
 define i64 @scalable_int_min_max(ptr %arg, ptr %arg1, <vscale x 2 x ptr> %i37, <vscale x 2 x i64> %i42, <vscale x 2 x i64> %i54) {
 ; CHECK-LABEL: scalable_int_min_max:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    mov w8, #3745 // =0xea1
-; CHECK-NEXT:    movk w8, #16618, lsl #16
 ; CHECK-NEXT:    ld1w { z3.d }, p0/z, [x0]
+; CHECK-NEXT:    movk w8, #16618, lsl #16
 ; CHECK-NEXT:    mov w9, #57344 // =0xe000
-; CHECK-NEXT:    mov z6.d, #1023 // =0x3ff
 ; CHECK-NEXT:    movk w9, #17535, lsl #16
 ; CHECK-NEXT:    mov z4.s, w8
 ; CHECK-NEXT:    fmul z4.s, p0/m, z4.s, z3.s
 ; CHECK-NEXT:    mov z5.s, w9
 ; CHECK-NEXT:    fadd z4.s, p0/m, z4.s, z5.s
-; CHECK-NEXT:    mov z5.d, #0 // =0x0
+; CHECK-NEXT:    mov z5.d, #1023 // =0x3ff
 ; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.s
-; CHECK-NEXT:    sxtw z5.d, p0/m, z5.d
-; CHECK-NEXT:    smax z4.d, p0/m, z4.d, z5.d
-; CHECK-NEXT:    movprfx z5, z6
-; CHECK-NEXT:    sxtw z5.d, p0/m, z6.d
+; CHECK-NEXT:    smax z4.d, z4.d, #0
 ; CHECK-NEXT:    smin z4.d, p0/m, z4.d, z5.d
 ; CHECK-NEXT:    cmpne p1.d, p0/z, z4.d, #0
 ; CHECK-NEXT:    ld1w { z4.d }, p1/z, [x1]
 ; CHECK-NEXT:    ld1w { z0.d }, p1/z, [z0.d]
 ; CHECK-NEXT:    fadd z0.s, p0/m, z0.s, z4.s
 ; CHECK-NEXT:    fcmge p2.s, p0/z, z0.s, z3.s
 ; CHECK-NEXT:    add z0.d, z2.d, z1.d
 ; CHECK-NEXT:    bic p2.b, p1/z, p1.b, p2.b

llvm/test/CodeGen/AArch64/sve-splat-sext.ll

; CHECK-NEXT:    ret
   %b = ashr <vscale x 8 x i16> %a, shufflevector (<vscale x 8 x i16> insertelement(<vscale x 8 x i16> undef, i16 8, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer)
   ret <vscale x 8 x i16> %b
 }
 
 define <vscale x 8 x i1> @sext_icmp_splat_v8i16_128(<vscale x 8 x i8> %d) {
 ; CHECK-LABEL: sext_icmp_splat_v8i16_128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z1.h, #255 // =0xff
 ; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
-; CHECK-NEXT:    sxtb z1.h, p0/m, z1.h
-; CHECK-NEXT:    cmpgt p0.h, p0/z, z0.h, z1.h
+; CHECK-NEXT:    cmpgt p0.h, p0/z, z0.h, #-1
 ; CHECK-NEXT:    ret
   %i = insertelement <vscale x 8 x i8> poison, i8 128, i32 0
   %s = shufflevector <vscale x 8 x i8> %i, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %c = icmp ugt <vscale x 8 x i8> %s, %d
   ret <vscale x 8 x i1> %c
 }
 
 define <vscale x 4 x i1> @sext_icmp_splat_v4i16_128(<vscale x 4 x i8> %d) {
 ; CHECK-LABEL: sext_icmp_splat_v4i16_128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z1.s, #255 // =0xff
 ; CHECK-NEXT:    sxtb z0.s, p0/m, z0.s
-; CHECK-NEXT:    sxtb z1.s, p0/m, z1.s
-; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, #-1
 ; CHECK-NEXT:    ret
   %i = insertelement <vscale x 4 x i8> poison, i8 128, i32 0
   %s = shufflevector <vscale x 4 x i8> %i, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
   %c = icmp ugt <vscale x 4 x i8> %s, %d
   ret <vscale x 4 x i1> %c
 }