[AArch64][GISel] Fix selection of G_CONSTANT_FOLD_BARRIER

[dmgreen]

Summary

As far as I understand - When lowering a G_CONSTANT_FOLD_BARRIER we replace the DstReg with SrcReg, and need to check that the register class is equivalent when doing so for the replacement to be legal. During lowering we could end up visiting nodes in an odd order, leaving a G_CONSTANT_FOLD_BARRIER with a known regclass for the src, but only a regbank for the dst. Providing the Regbank contains the regclass, the replacement should still be safe.

This fixes an assert seen in the llvm-test-suite when lowering hoisted constants, relaxing the assert to account for the difference in visiting order.

[tschuett]

llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir

160

The verifier allows unconditional branches after conditional branches?

[tschuett]

llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir

160

Deleted!!!

[arsenm]

llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir

4

Should drop IR section

189–197

This can be reduced, can try llvm-reduce mir handling

[dmgreen]

Reduce test size.

[arsenm]

llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp

182–185

I would assume canReplaceReg covers all this

[dmgreen]

Move the logic into canReplaceReg.

llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp

#endif
       if (isPreISelGenericOptimizationHint(MI.getOpcode()) ||
           MI.getOpcode() == TargetOpcode::G_CONSTANT_FOLD_BARRIER) {
         auto [DstReg, SrcReg] = MI.getFirst2Regs();
 
         // At this point, the destination register class of the op may have
         // been decided.
         //
         // Propagate that through to the source register.
-        const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
-        if (DstRC)
-          MRI.setRegClass(SrcReg, DstRC);
-        assert(canReplaceReg(DstReg, SrcReg, MRI) &&
+        const auto &DstRBC = MRI.getRegClassOrRegBank(DstReg);
+        if (DstRBC && DstRBC.is<const TargetRegisterClass *>())
+          MRI.setRegClass(SrcReg, DstRBC.get<const TargetRegisterClass *>());
+        assert((canReplaceReg(DstReg, SrcReg, MRI) ||
+                (DstRBC && DstRBC.is<const RegisterBank *>() &&
+                 MRI.getRegClassOrNull(SrcReg) &&
+                 DstRBC.get<const RegisterBank *>()->covers(
+                     *MRI.getRegClassOrNull(SrcReg)))) &&
                "Must be able to replace dst with src!");
         MI.eraseFromParent();
         MRI.replaceRegWith(DstReg, SrcReg);
         continue;
       }
 
       if (MI.getOpcode() == TargetOpcode::G_INVOKE_REGION_START) {
         MI.eraseFromParent();

llvm/test/CodeGen/AArch64/GlobalISel/select-constbarrier.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64"
+
+  define fastcc i1 @test(i1 %cond, i1 %cond1) {
+  entry:
+    br i1 %cond, label %sw.bb9, label %sw.bb34
+
+  sw.bb9:                                           ; preds = %entry
+    br i1 %cond1, label %sw.bb72.i, label %sw.bb5.i
+
+  sw.bb5.i:                                         ; preds = %sw.bb9
+    br i1 %cond, label %common.ret, label %land.rhs.i
+
+  land.rhs.i:                                       ; preds = %sw.bb5.i
+    %const1 = bitcast i32 145185 to i32
+    %call45.i = tail call i32 (ptr, ptr, ...) @fprintf(ptr null, ptr null, ptr null, i32 1, ptr null, i32 %const1)
+    br label %common.ret
+
+  common.ret:                                       ; preds = %sw.bb34, %sw.bb72.i, %land.rhs.i, %sw.bb5.i
+    ret i1 false
+
+  sw.bb72.i:                                        ; preds = %sw.bb9
+    %const2 = bitcast i32 145185 to i32
+    %const_mat3 = add i32 %const2, 28
+    %call105.i = tail call i32 (ptr, ptr, ...) @fprintf(ptr null, ptr null, ptr null, i32 0, ptr null, i32 %const_mat3)
+    br label %common.ret
+
+  sw.bb34:                                          ; preds = %entry
+    %const = bitcast i32 145185 to i32
+    %const_mat = add i32 %const, 1169
+    %call133.i = tail call i32 (ptr, ptr, ...) @fprintf(ptr null, ptr null, ptr null, i32 0, ptr null, i32 %const_mat)
+    br label %common.ret
+  }
+
+  declare i32 @fprintf(ptr, ptr, ...)
+
+...
+---
+name:            test
+legalized:       true
+regBankSelected: true
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: test
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.6(0x40000000)
+  ; CHECK-NEXT:   liveins: $w0, $w1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32common = MOVi32imm 145185
+  ; CHECK-NEXT:   TBZW [[COPY]], 0, %bb.6
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.sw.bb9:
+  ; CHECK-NEXT:   successors: %bb.5(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   TBNZW [[COPY1]], 0, %bb.5
+  ; CHECK-NEXT:   B %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.sw.bb5.i:
+  ; CHECK-NEXT:   successors: %bb.4(0x40000000), %bb.3(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   TBNZW [[COPY]], 0, %bb.4
+  ; CHECK-NEXT:   B %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.land.rhs.i:
+  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
+  ; CHECK-NEXT:   $x0 = COPY [[COPY2]]
+  ; CHECK-NEXT:   $x1 = COPY [[COPY2]]
+  ; CHECK-NEXT:   $x2 = COPY [[COPY2]]
+  ; CHECK-NEXT:   [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1
+  ; CHECK-NEXT:   $w3 = COPY [[MOVi32imm1]]
+  ; CHECK-NEXT:   $x4 = COPY [[COPY2]]
+  ; CHECK-NEXT:   $w5 = COPY [[MOVi32imm]]
+  ; CHECK-NEXT:   BL @fprintf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $x4, implicit $w5, implicit-def $w0
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4.common.ret:
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
+  ; CHECK-NEXT:   $w0 = COPY [[COPY3]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.5.sw.bb72.i:
+  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[MOVi32imm]], 28, 0
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gpr64 = COPY $xzr
+  ; CHECK-NEXT:   $x0 = COPY [[COPY4]]
+  ; CHECK-NEXT:   $x1 = COPY [[COPY4]]
+  ; CHECK-NEXT:   $x2 = COPY [[COPY4]]
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:gpr32 = COPY $wzr
+  ; CHECK-NEXT:   $w3 = COPY [[COPY5]]
+  ; CHECK-NEXT:   $x4 = COPY [[COPY4]]
+  ; CHECK-NEXT:   $w5 = COPY [[ADDWri]]
+  ; CHECK-NEXT:   BL @fprintf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $x4, implicit $w5, implicit-def $w0
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   B %bb.4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.6.sw.bb34:
+  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[MOVi32imm]], 1169, 0
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:gpr64 = COPY $xzr
+  ; CHECK-NEXT:   $x0 = COPY [[COPY6]]
+  ; CHECK-NEXT:   $x1 = COPY [[COPY6]]
+  ; CHECK-NEXT:   $x2 = COPY [[COPY6]]
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:gpr32 = COPY $wzr
+  ; CHECK-NEXT:   $w3 = COPY [[COPY7]]
+  ; CHECK-NEXT:   $x4 = COPY [[COPY6]]
+  ; CHECK-NEXT:   $w5 = COPY [[ADDWri1]]
+  ; CHECK-NEXT:   BL @fprintf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $x4, implicit $w5, implicit-def $w0
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   B %bb.4
+  bb.1.entry:
+    successors: %bb.2(0x40000000), %bb.7(0x40000000)
+    liveins: $w0, $w1
+
+    %4:gpr(s32) = COPY $w0
+    %2:gpr(s8) = G_TRUNC %4(s32)
+    %5:gpr(s32) = COPY $w1
+    %3:gpr(s8) = G_TRUNC %5(s32)
+    %6:gpr(s8) = G_ASSERT_ZEXT %2, 1
+    %7:gpr(s8) = G_ASSERT_ZEXT %3, 1
+    %8:gpr(s32) = G_CONSTANT i32 145185
+    %40:gpr(s32) = G_ANYEXT %6(s8)
+    %41:gpr(s32) = G_CONSTANT i32 1
+    %42:gpr(s32) = G_XOR %40, %41
+    %39:gpr(s32) = G_AND %42, %41
+    G_BRCOND %39(s32), %bb.7
+    G_BR %bb.2
+
+  bb.2.sw.bb9:
+    successors: %bb.6(0x40000000), %bb.3(0x40000000)
+
+    %44:gpr(s32) = G_CONSTANT i32 1
+    %45:gpr(s32) = G_ANYEXT %7(s8)
+    %38:gpr(s32) = G_AND %45, %44
+    G_BRCOND %38(s32), %bb.6
+    G_BR %bb.3
+
+  bb.3.sw.bb5.i:
+    successors: %bb.5(0x40000000), %bb.4(0x40000000)
+
+    %46:gpr(s32) = G_CONSTANT i32 1
+    %47:gpr(s32) = G_ANYEXT %6(s8)
+    %37:gpr(s32) = G_AND %47, %46
+    G_BRCOND %37(s32), %bb.5
+    G_BR %bb.4
+
+  bb.4.land.rhs.i:
+    successors: %bb.5(0x80000000)
+
+    %15:gpr(s32) = G_CONSTANT_FOLD_BARRIER %8
+    ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+    %33:gpr(p0) = G_CONSTANT i64 0
+    $x0 = COPY %33(p0)
+    $x1 = COPY %33(p0)
+    $x2 = COPY %33(p0)
+    %29:gpr(s32) = G_CONSTANT i32 1
+    $w3 = COPY %29(s32)
+    $x4 = COPY %33(p0)
+    $w5 = COPY %15(s32)
+    BL @fprintf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $x4, implicit $w5, implicit-def $w0
+    ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+
+  bb.5.common.ret:
+    %49:gpr(s32) = G_CONSTANT i32 0
+    $w0 = COPY %49(s32)
+    RET_ReallyLR implicit $w0
+
+  bb.6.sw.bb72.i:
+    successors: %bb.5(0x80000000)
+
+    %18:gpr(s32) = G_CONSTANT_FOLD_BARRIER %8
+    %28:gpr(s32) = G_CONSTANT i32 28
+    %20:gpr(s32) = G_ADD %18, %28
+    ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+    %34:gpr(p0) = G_CONSTANT i64 0
+    $x0 = COPY %34(p0)
+    $x1 = COPY %34(p0)
+    $x2 = COPY %34(p0)
+    %31:gpr(s32) = G_CONSTANT i32 0
+    $w3 = COPY %31(s32)
+    $x4 = COPY %34(p0)
+    $w5 = COPY %20(s32)
+    BL @fprintf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $x4, implicit $w5, implicit-def $w0
+    ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    G_BR %bb.5
+
+  bb.7.sw.bb34:
+    successors: %bb.5(0x80000000)
+
+    %9:gpr(s32) = G_CONSTANT_FOLD_BARRIER %8
+    %35:gpr(s32) = G_CONSTANT i32 1169
+    %11:gpr(s32) = G_ADD %9, %35
+    ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+    %32:gpr(p0) = G_CONSTANT i64 0
+    $x0 = COPY %32(p0)
+    $x1 = COPY %32(p0)
+    $x2 = COPY %32(p0)
+    %30:gpr(s32) = G_CONSTANT i32 0
+    $w3 = COPY %30(s32)
+    $x4 = COPY %32(p0)
+    $w5 = COPY %11(s32)
+    BL @fprintf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $x4, implicit $w5, implicit-def $w0
+    ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    G_BR %bb.5
+
+...