[RISCV][NFC] Change type of isOrdered to boolean

[wangpc]

Summary

The name is isOrdered but it's a string actually, which is a bit
confusing. We change its type to bit and get the order string via
its value.

[craig.topper]

LGTM

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

274–277

Do we need to use an argument to accomplish selection of O and U in addition to passing isOrdered? It's a little confusing to the user of this class that they should never pass the order argument. I think it would be a better interface to use !if() twice to avoid adding complexity for users of this class. WDYT?

[wangpc]

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

274–277

As what I said in description, I just use it to eliminate redundancies. But you are right, this can be confusing.
I will change it tomorrow. :-)

[wangpc]

Remove argument.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 class VSSSched<int eew, string emul, bit forceMasked = 0> : SchedCommon<
   [!cast<SchedWrite>("WriteVSTS" # eew # "_" # emul)],
   [!cast<SchedRead>("ReadVSTS" # eew # "V_" # emul), ReadVSTX, ReadVSTSX],
   emul, eew, forceMasked
 >;
 class VSSSchedMC<int eew> : VSSSched<eew, "WorstCase", forceMasked=1>;
 
 // Vector Indexed Loads and Stores
-class VLXSched<int dataEEW, string isOrdered, string dataEMUL, string idxEMUL,
+class VLXSched<int dataEEW, bit isOrdered, string dataEMUL, string idxEMUL,
                bit forceMasked = 0> : SchedCommon<
-  [!cast<SchedWrite>("WriteVLD" # isOrdered # "X" # dataEEW # "_" # dataEMUL)],
-  [ReadVLDX, !cast<SchedRead>("ReadVLD" # isOrdered # "XV_" # idxEMUL)],
+  [!cast<SchedWrite>("WriteVLD" # !if(isOrdered, "O", "U") # "X" # dataEEW # "_" # dataEMUL)],
+  [ReadVLDX, !cast<SchedRead>("ReadVLD" # !if(isOrdered, "O", "U") # "XV_" # idxEMUL)],
   dataEMUL, dataEEW, forceMasked
 >;
-class VLXSchedMC<int dataEEW, string isOrdered>:
+class VLXSchedMC<int dataEEW, bit isOrdered>:
   VLXSched<dataEEW, isOrdered, "WorstCase", "WorstCase", forceMasked=1>;
 
-class VSXSched<int dataEEW, string isOrdered, string dataEMUL, string idxEMUL,
+class VSXSched<int dataEEW, bit isOrdered, string dataEMUL, string idxEMUL,
                bit forceMasked = 0> : SchedCommon<
-  [!cast<SchedWrite>("WriteVST" # isOrdered # "X" # dataEEW # "_" # dataEMUL)],
-  [!cast<SchedRead>("ReadVST" # isOrdered #"X" # dataEEW # "_" # dataEMUL),
-   ReadVSTX, !cast<SchedRead>("ReadVST" # isOrdered # "XV_" # idxEMUL)],
+  [!cast<SchedWrite>("WriteVST" # !if(isOrdered, "O", "U") # "X" # dataEEW # "_" # dataEMUL)],
+  [!cast<SchedRead>("ReadVST" # !if(isOrdered, "O", "U") #"X" # dataEEW # "_" # dataEMUL),
+   ReadVSTX, !cast<SchedRead>("ReadVST" # !if(isOrdered, "O", "U") # "XV_" # idxEMUL)],
   dataEMUL, dataEEW, forceMasked
 >;
-class VSXSchedMC<int dataEEW, string isOrdered>:
+class VSXSchedMC<int dataEEW, bit isOrdered>:
   VSXSched<dataEEW, isOrdered, "WorstCase", "WorstCase", forceMasked=1>;
 
 // Unit-stride Fault-Only-First Loads
 class VLFSched<string lmul, bit forceMasked = 0> : SchedCommon<
   [!cast<SchedWrite>("WriteVLDFF_" # lmul)],
   [ReadVLDX], mx=lmul, forceMasked=forceMasked
 >;
 class VLFSchedMC: VLFSched<"WorstCase", forceMasked=1>;

 class VSSSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
   [!cast<SchedWrite>("WriteVSSSEG" #nf #"e" #eew #"_" #emul)],
   [!cast<SchedRead>("ReadVSTS" #eew #"V_" #emul),
    ReadVSTX, ReadVSTSX], emul, eew, forceMasked
 >;
 class VSSSEGSchedMC<int nf, int eew> : VSSSEGSched<nf, eew, "WorstCase",
                                                    forceMasked=1>;
 
 // Indexed Segment Loads and Stores
-class VLXSEGSched<int nf, int eew, string isOrdered, string emul,
+class VLXSEGSched<int nf, int eew, bit isOrdered, string emul,
                   bit forceMasked = 0> : SchedCommon<
-  [!cast<SchedWrite>("WriteVL" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul)],
-  [ReadVLDX, !cast<SchedRead>("ReadVLD" #isOrdered #"XV_" #emul)],
+  [!cast<SchedWrite>("WriteVL" #!if(isOrdered, "O", "U") #"XSEG" #nf #"e" #eew #"_" #emul)],
+  [ReadVLDX, !cast<SchedRead>("ReadVLD" #!if(isOrdered, "O", "U") #"XV_" #emul)],
   emul, eew, forceMasked
 >;
-class VLXSEGSchedMC<int nf, int eew, string isOrdered>:
+class VLXSEGSchedMC<int nf, int eew, bit isOrdered>:
   VLXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>;
 
 // Passes sew=0 instead of eew=0 since this pseudo does not follow MX_E form.
-class VSXSEGSched<int nf, int eew, string isOrdered, string emul,
+class VSXSEGSched<int nf, int eew, bit isOrdered, string emul,
                   bit forceMasked = 0> : SchedCommon<
-  [!cast<SchedWrite>("WriteVS" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul)],
-  [!cast<SchedRead>("ReadVST" #isOrdered #"X" #eew #"_" #emul),
-   ReadVSTX, !cast<SchedRead>("ReadVST" #isOrdered #"XV_" #emul)],
+  [!cast<SchedWrite>("WriteVS" #!if(isOrdered, "O", "U") #"XSEG" #nf #"e" #eew #"_" #emul)],
+  [!cast<SchedRead>("ReadVST" #!if(isOrdered, "O", "U") #"X" #eew #"_" #emul),
+   ReadVSTX, !cast<SchedRead>("ReadVST" #!if(isOrdered, "O", "U") #"XV_" #emul)],
   emul, sew=0, forceMasked=forceMasked
 >;
-class VSXSEGSchedMC<int nf, int eew, string isOrdered>:
+class VSXSEGSchedMC<int nf, int eew, bit isOrdered>:
   VSXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>;
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 // unit-stride load vd, (rs1), vm

 //===----------------------------------------------------------------------===//
 
 multiclass VIndexLoadStore<list<int> EEWList> {
   foreach n = EEWList in {
     defvar w = !cast<RISCVWidth>("LSWidth" # n);
 
     def VLUXEI # n # _V :
       VIndexedLoad<MOPLDIndexedUnord, w, "vluxei" # n # ".v">,
-      VLXSchedMC<n, "U">;
+      VLXSchedMC<n, isOrdered=0>;
     def VLOXEI # n # _V :
       VIndexedLoad<MOPLDIndexedOrder, w, "vloxei" # n # ".v">,
-      VLXSchedMC<n, "O">;
+      VLXSchedMC<n, isOrdered=1>;
 
     def VSUXEI # n # _V :
       VIndexedStore<MOPSTIndexedUnord, w, "vsuxei" # n # ".v">,
-      VSXSchedMC<n, "U">;
+      VSXSchedMC<n, isOrdered=0>;
     def VSOXEI # n # _V :
       VIndexedStore<MOPSTIndexedOrder, w, "vsoxei" # n # ".v">,
-      VSXSchedMC<n, "O">;
+      VSXSchedMC<n, isOrdered=1>;
   }
 }
 
 multiclass VALU_IV_V<string opcodestr, bits<6> funct6> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
            SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
 }
 
foreach eew = [8, 16, 32] in {
       def VSSSEG#nf#E#eew#_V :
         VStridedSegmentStore<!add(nf, -1), w, "vssseg"#nf#"e"#eew#".v">,
         VSSSEGSchedMC<nf, eew>;
 
       // Vector Indexed Instructions
       def VLUXSEG#nf#EI#eew#_V :
         VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, w,
                             "vluxseg"#nf#"ei"#eew#".v">,
-        VLXSEGSchedMC<nf, eew, "U">;
+        VLXSEGSchedMC<nf, eew, isOrdered=0>;
       def VLOXSEG#nf#EI#eew#_V :
         VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, w,
                             "vloxseg"#nf#"ei"#eew#".v">,
-        VLXSEGSchedMC<nf, eew, "O">;
+        VLXSEGSchedMC<nf, eew, isOrdered=1>;
       def VSUXSEG#nf#EI#eew#_V :
         VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, w,
                              "vsuxseg"#nf#"ei"#eew#".v">,
-        VSXSEGSchedMC<nf, eew, "U">;
+        VSXSEGSchedMC<nf, eew, isOrdered=0>;
       def VSOXSEG#nf#EI#eew#_V :
         VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, w,
                              "vsoxseg"#nf#"ei"#eew#".v">,
-        VSXSEGSchedMC<nf, eew, "O">;
+        VSXSEGSchedMC<nf, eew, isOrdered=1>;
     }
   }
 } // Predicates = [HasVInstructions]
 
 let Predicates = [HasVInstructionsI64] in {
   foreach nf=2-8 in {
     // Vector Unit-strided Segment Instructions
     def VLSEG#nf#E64_V :
let Predicates = [HasVInstructionsI64] in {
   }
 } // Predicates = [HasVInstructionsI64]
 let Predicates = [HasVInstructionsI64, IsRV64] in {
   foreach nf = 2 - 8 in {
     // Vector Indexed Segment Instructions
     def VLUXSEG #nf #EI64_V
         : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, LSWidth64,
                               "vluxseg" #nf #"ei64.v">,
-          VLXSEGSchedMC<nf, 64, "U">;
+          VLXSEGSchedMC<nf, 64, isOrdered=0>;
     def VLOXSEG #nf #EI64_V
         : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, LSWidth64,
                               "vloxseg" #nf #"ei64.v">,
-          VLXSEGSchedMC<nf, 64, "O">;
+          VLXSEGSchedMC<nf, 64, isOrdered=1>;
     def VSUXSEG #nf #EI64_V
         : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, LSWidth64,
                                "vsuxseg" #nf #"ei64.v">,
-          VSXSEGSchedMC<nf, 64, "U">;
+          VSXSEGSchedMC<nf, 64, isOrdered=0>;
     def VSOXSEG #nf #EI64_V
         : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64,
                                "vsoxseg" #nf #"ei64.v">,
-          VSXSEGSchedMC<nf, 64, "O">;
+          VSXSEGSchedMC<nf, 64, isOrdered=1>;
   }
 } // Predicates = [HasVInstructionsI64, IsRV64]
 
 include "RISCVInstrInfoVPseudos.td"

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

foreach dataEEW = EEWList in {
           !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW));
         if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
           defvar DataLInfo = dataEMUL.MX;
           defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;
           defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = dataEMUL.vrclass;
           defvar IdxVreg = idxEMUL.vrclass;
           defvar HasConstraint = !ne(dataEEW, idxEEW);
-          defvar Order = !if(Ordered, "O", "U");
           let VLMul = dataEMUL.value in {
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
               VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
-              VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
+              VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
               VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
               RISCVMaskedPseudo<MaskIdx=3>,
-              VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
+              VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
           }
         }
       }
     }
   }
 }
 
 multiclass VPseudoUSStore {
foreach dataEEW = EEWList in {
         defvar idxEMULOctuple =
           !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW));
         if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
           defvar DataLInfo = dataEMUL.MX;
           defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;
           defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = dataEMUL.vrclass;
           defvar IdxVreg = idxEMUL.vrclass;
-          defvar Order = !if(Ordered, "O", "U");
           let VLMul = dataEMUL.value in {
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
               VPseudoIStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
-              VSXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
+              VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
             def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
               VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
-              VSXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
+              VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
           }
         }
       }
     }
   }
 }
 
 multiclass VPseudoVPOP_M {
foreach dataEEW = EEWList in {
         // Calculate emul = eew * lmul / sew
         defvar idxEMULOctuple = !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW));
         if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
           defvar DataLInfo = dataEMUL.MX;
           defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;
           defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar DataVreg = dataEMUL.vrclass;
           defvar IdxVreg = idxEMUL.vrclass;
-          defvar Order = !if(Ordered, "O", "U");
           let VLMul = dataEMUL.value in {
             foreach nf = NFSet<dataEMUL>.L in {
               defvar Vreg = SegRegClass<dataEMUL, nf>.RC;
               def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
                 VPseudoISegLoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
                                       nf, Ordered>,
-                VLXSEGSched<nf, dataEEW, Order, DataLInfo>;
+                VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>;
               def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
                 VPseudoISegLoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
                                     nf, Ordered>,
-                VLXSEGSched<nf, dataEEW, Order, DataLInfo>;
+                VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>;
             }
           }
         }
       }
     }
   }
 }
 
foreach dataEEW = EEWList in {
         // Calculate emul = eew * lmul / sew
         defvar idxEMULOctuple = !srl(!mul(idxEEW, dataEMULOctuple), !logtwo(dataEEW));
         if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
           defvar DataLInfo = dataEMUL.MX;
           defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;
           defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar DataVreg = dataEMUL.vrclass;
           defvar IdxVreg = idxEMUL.vrclass;
-          defvar Order = !if(Ordered, "O", "U");
           let VLMul = dataEMUL.value in {
             foreach nf = NFSet<dataEMUL>.L in {
               defvar Vreg = SegRegClass<dataEMUL, nf>.RC;
               def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
                 VPseudoISegStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
                                        nf, Ordered>,
-                VSXSEGSched<nf, idxEEW, Order, DataLInfo>;
+                VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>;
               def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
                 VPseudoISegStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
                                      nf, Ordered>,
-                VSXSEGSched<nf, idxEEW, Order, DataLInfo>;
+                VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>;
             }
           }
         }
       }
     }
   }
 }