[AArch64] Correct the regtype of indexed fmlal

[dmgreen]

Summary

The indexed fmlal should use a low numbered register for the index operand, which this fixes by making it V128_lo.

Fixes 64104

llvm/lib/Target/AArch64/AArch64InstrFormats.td

 
 // ARMv8.2-A Fused Multiply Add-Long Instructions (Indexed)
 let mayRaiseFPException = 1, Uses = [FPCR] in
 class BaseSIMDThreeSameVectorFMLIndex<bit Q, bit U, bits<4> opc, string asm,
                                       string dst_kind, string lhs_kind,
                                       string rhs_kind, RegisterOperand RegType,
                                       ValueType AccumType, ValueType InputType,
                                       SDPatternOperator OpNode> :
-        BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, RegType, RegType, V128,
+        BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, RegType, RegType, V128_lo,
                             VectorIndexH, asm, "", dst_kind, lhs_kind, rhs_kind,
           [(set (AccumType RegType:$dst),
                 (AccumType (OpNode (AccumType RegType:$Rd),
                                    (InputType RegType:$Rn),
-                                   (InputType (AArch64duplane16 (v8f16 V128:$Rm),
+                                   (InputType (AArch64duplane16 (v8f16 V128_lo:$Rm),
                                                 VectorIndexH:$idx)))))]> {
   // idx = H:L:M
   bits<3> idx;
   let Inst{11} = idx{2}; // H
   let Inst{21} = idx{1}; // L
   let Inst{20} = idx{0}; // M
 }
 

llvm/test/CodeGen/AArch64/fmlal-loreg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=aarch64 -mattr=+fp16fml -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
 
 ; This tests that the fmlal/fmlal2 instructions only accept lo registers for
 ; the index operand, using inline asm to force the available registers.
 
 define <4 x float> @test(ptr %lhs_panel, ptr %rhs_panel, <4 x float> %a) {
 ; CHECK-LABEL: test:
 ; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset b8, -16
 ; CHECK-NEXT:    fmov x8, d0
-; CHECK-NEXT:    ldr q16, [x0]
-; CHECK-NEXT:    ldr q17, [x1]
+; CHECK-NEXT:    ldr q8, [x0]
+; CHECK-NEXT:    ldr q16, [x1]
 ; CHECK-NEXT:    lsr x9, x8, #32
 ; CHECK-NEXT:    //APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    //NO_APP
 ; CHECK-NEXT:    mov w8, w8
 ; CHECK-NEXT:    orr x8, x8, x9, lsl #32
 ; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    fmlal v0.4s, v17.4h, v16.h[0]
+; CHECK-NEXT:    fmlal v0.4s, v16.4h, v8.h[0]
 ; CHECK-NEXT:    mov v1.16b, v0.16b
-; CHECK-NEXT:    fmlal2 v1.4s, v17.4h, v16.h[0]
+; CHECK-NEXT:    fmlal2 v1.4s, v16.4h, v8.h[0]
 ; CHECK-NEXT:    fadd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   %0 = load <8 x half>, ptr %lhs_panel, align 2
   %1 = load <8 x half>, ptr %rhs_panel, align 2
   %vecinit91 = shufflevector <8 x half> %0, <8 x half> undef, <8 x i32> zeroinitializer
   %b = call <4 x float> asm sideeffect "nop", "=r,r,~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7}"(<4 x float> %a) nounwind
   %vfmlal_low3.i = tail call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %b, <8 x half> %1, <8 x half> %vecinit91)
   %vfmlal_high3.i = tail call <4 x float> @llvm.aarch64.neon.fmlal2.v4f32.v8f16(<4 x float> %vfmlal_low3.i, <8 x half> %1, <8 x half> %vecinit91)