[X86] AMD Genoa (znver4) LoopMicroOpBufferSize update

[GGanesh]

Summary

Change LoopMicroOpBufferSize to 512 similar to znver3 value. This is done so as to support unrolling threshold.

[RKSimon]

llvm/lib/Target/X86/X86ScheduleZnver4.td

1541

Please pre-commit whitespace cleanups as NFC and remove them from this patch

[GGanesh]

Updated for @RKSimon's comments

[RKSimon]

LGTM - cheers

[GGanesh]

Committed with commit 536e805e4dbcd8efb19dc279f00496766cad1fad

llvm/lib/Target/X86/X86ScheduleZnver4.td

def Znver4Model : SchedMachineModel {
   // Agner, 22.5 µop cache
   // The size of the µop cache is big enough for holding most critical loops.
   // FIXME: PR50584: MachineScheduler/PostRAScheduler have quadradic complexity,
   //        with large values here the compilation of certain loops
   //        ends up taking way too long.
   // Ideally for znver4, we should have 6.75K. However we don't add that
   // considerting the impact compile time and prefer using default values 
   // instead.
-  // let LoopMicroOpBufferSize = 6750;
+  // Retaining minimal value to influence unrolling as we did for znver3.
+  let LoopMicroOpBufferSize = 512;
   // AMD SOG 19h, 2.6.2 L1 Data Cache
   // The L1 data cache has a 4- or 5- cycle integer load-to-use latency.
   // AMD SOG 19h, 2.12 L1 Data Cache
   // The AGU and LS pipelines are optimized for simple address generation modes.
   // <...> and can achieve 4-cycle load-to-use integer load latency.
   let LoadLatency = 4;
   // AMD SOG 19h, 2.12 L1 Data Cache
   // The AGU and LS pipelines are optimized for simple address generation modes.

 
 // FIXUP and RANGE Instructions
 def Zn4WriteVFIXUPIMMPDZrr_VRANGESDrr : SchedWriteRes<[Zn4FPFMisc01]> {
   let Latency = 2;
   let ResourceCycles = [2];
   let NumMicroOps = 1;
 }
 def : InstRW<[Zn4WriteVFIXUPIMMPDZrr_VRANGESDrr], (instregex
   "VFIXUPIMM(S|P)(S|D)(Z|Z128|Z256?)rrik", "VFIXUPIMM(S|P)(S|D)(Z?|Z128?|Z256?)rrikz", 
         "VFIXUPIMM(S|P)(S|D)(Z128|Z256?)rri",  "VRANGE(S|P)(S|D)(Z?|Z128?|Z256?)rri(b?)",
   "VRANGE(S|P)(S|D)(Z|Z128|Z256?)rri(b?)k","VRANGE(S|P)(S|D)(Z?|Z128?|Z256?)rri(b?)kz"
   )>;
 
 // SCALE & REDUCE instructions
 def Zn4WriteSCALErr: SchedWriteRes<[Zn4FPFMisc23]> {
   let Latency = 6;
   let ResourceCycles = [6];

llvm/test/Transforms/LoopUnroll/X86/call-remark.ll

 ; RUN: opt -passes=debugify,loop-unroll -mcpu=znver3 -pass-remarks=loop-unroll -pass-remarks-analysis=loop-unroll < %s -S 2>&1 | FileCheck --check-prefixes=ALL,UNROLL %s
 ; RUN: opt -passes=debugify,loop-unroll -mcpu=znver3 -pass-remarks=TTI -pass-remarks-analysis=TTI  < %s -S 2>&1 | FileCheck --check-prefixes=ALL,TTI %s
+; RUN: opt -passes=debugify,loop-unroll -mcpu=znver4 -pass-remarks=loop-unroll -pass-remarks-analysis=loop-unroll < %s -S 2>&1 | FileCheck --check-prefixes=ALL,UNROLL %s
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; TTI: remark: <stdin>:7:1: advising against unrolling the loop because it contains a call
 ; UNROLL: remark: <stdin>:14:1: unrolled loop by a factor of 8 with run-time trip count
 
 define void @contains_external_call(i32 %count) {