[GIsel][AArch64] extend legalization of G_INSERT_VECTOR_ELT

[tschuett]

Summary

Fixes https://github.com/llvm/llvm-project/issues/63826

[Allen]

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

705–707

Thanks for helping to fix, would it make sense to add some other types, such as v2s8 ?
https://gcc.godbolt.org/z/azrjv64E8

[tschuett]

I would like to only do the minimal fix for your PR. Yes, there are more legal vectors.

[Allen]

ok, thanks.
I'm not familiar with this module, It is better to confirm it with the other expert.

[dmgreen]

As we will not have any tablegen patterns for v2s16 types, it may be better to legalize it to a v4s16 instead by clamping the number of elements.

[tschuett]

G_INSERT_VECTOR_ELT is manually handled by the instruction selector:
https://github.com/llvm/llvm-project/blob/feaf70b3cd64d09566ec667ce95340056c358ca2/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp#L5447

[tschuett]

The PR rooted in this diff:
https://reviews.llvm.org/D153394#4482620

[tschuett]

widen v2s16 -> v4s16

[tschuett]

reformat

[aemerson]

You can just add the test case to the existing one in AArch64/GlobalISel/legalize-insert-vector-elt.mir

llvm/test/CodeGen/AArch64/GlobalISel/pr-63826.mir

18–19 ↗

(On Diff #540934)

I prefer to use real values instead of undef for these in case some legalizer combine tries to be smart and elides them in future. For aarch64 you can just use copies from the fpr registers:

%1:_(s16) = COPY $h0
%2:_(s16) = COPY $h1

[tschuett]

move pr to legalize-insert-vector-elt.mir

[tschuett]

fix syntax error

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

getActionDefinitionsBuilder(G_EXTRACT_VECTOR_ELT)
           0, s8)
       .minScalarOrElt(0, s8) // Worst case, we need at least s8.
       .clampMaxNumElements(1, s64, 2)
       .clampMaxNumElements(1, s32, 4)
       .clampMaxNumElements(1, s16, 8)
       .clampMaxNumElements(1, p0, 2);
 
   getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
-      .legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}));
+      .legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}))
+      .clampMinNumElements(0, s16, 4)
+      .clampMaxNumElements(0, s16, 8);
 
   getActionDefinitionsBuilder(G_BUILD_VECTOR)
       .legalFor({{v8s8, s8},
                  {v16s8, s8},
                  {v4s16, s16},
                  {v8s16, s16},
                  {v2s32, s32},
                  {v4s32, s32},

llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s
-
+---
+name:            pr63826
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: pr63826
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $w0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[DEF]](s16), [[DEF]](s16)
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s16), [[C1]](s32)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[IVEC]](<4 x s16>)
+    ; CHECK-NEXT: $w0 = COPY [[UV2]](<2 x s16>)
+    %0:_(<2 x s16>) = COPY $w0
+    %1:_(s16) = G_CONSTANT i16 1
+    %2:_(s32) = G_CONSTANT i32 42
+    %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0(<2 x s16>), %1(s16), %2(s32)
+    $w0 = COPY %4(<2 x s16>)
+...
 ---
 name:            v8s8
 body: |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: v8s8
-    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: %val:_(s8) = G_CONSTANT i8 42
-    ; CHECK: [[IVEC:%[0-9]+]]:_(<8 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32)
-    ; CHECK: $d0 = COPY [[IVEC]](<8 x s8>)
-    ; CHECK: RET_ReallyLR
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: %val:_(s8) = G_CONSTANT i8 42
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32)
+    ; CHECK-NEXT: $d0 = COPY [[IVEC]](<8 x s8>)
+    ; CHECK-NEXT: RET_ReallyLR
     %0:_(<8 x s8>) = COPY $d0
     %1:_(s32) = G_CONSTANT i32 1
     %val:_(s8) = G_CONSTANT i8 42
     %2:_(<8 x s8>) = G_INSERT_VECTOR_ELT %0(<8 x s8>), %val(s8), %1(s32)
     $d0 = COPY %2(<8 x s8>)
     RET_ReallyLR
 ...
 ---
 name:            v16s8
 body: |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: v16s8
-    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: %val:_(s8) = G_CONSTANT i8 42
-    ; CHECK: [[IVEC:%[0-9]+]]:_(<16 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32)
-    ; CHECK: $q0 = COPY [[IVEC]](<16 x s8>)
-    ; CHECK: RET_ReallyLR
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: %val:_(s8) = G_CONSTANT i8 42
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<16 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32)
+    ; CHECK-NEXT: $q0 = COPY [[IVEC]](<16 x s8>)
+    ; CHECK-NEXT: RET_ReallyLR
     %0:_(<16 x s8>) = COPY $q0
     %1:_(s32) = G_CONSTANT i32 1
     %val:_(s8) = G_CONSTANT i8 42
     %2:_(<16 x s8>) = G_INSERT_VECTOR_ELT %0(<16 x s8>), %val(s8), %1(s32)
     $q0 = COPY %2(<16 x s8>)
     RET_ReallyLR
 ...
 ---
 name:            v4s16
 body: |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: v4s16
-    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: %val:_(s16) = G_CONSTANT i16 42
-    ; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
-    ; CHECK: $d0 = COPY [[IVEC]](<4 x s16>)
-    ; CHECK: RET_ReallyLR
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: %val:_(s16) = G_CONSTANT i16 42
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
+    ; CHECK-NEXT: $d0 = COPY [[IVEC]](<4 x s16>)
+    ; CHECK-NEXT: RET_ReallyLR
     %0:_(<4 x s16>) = COPY $d0
     %1:_(s32) = G_CONSTANT i32 1
     %val:_(s16) = G_CONSTANT i16 42
     %2:_(<4 x s16>) = G_INSERT_VECTOR_ELT %0(<4 x s16>), %val(s16), %1(s32)
     $d0 = COPY %2(<4 x s16>)
     RET_ReallyLR
 ...
 ---
 name:            v8s16
 body: |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: v8s16
-    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: %val:_(s16) = G_CONSTANT i16 42
-    ; CHECK: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
-    ; CHECK: $q0 = COPY [[IVEC]](<8 x s16>)
-    ; CHECK: RET_ReallyLR
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: %val:_(s16) = G_CONSTANT i16 42
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
+    ; CHECK-NEXT: $q0 = COPY [[IVEC]](<8 x s16>)
+    ; CHECK-NEXT: RET_ReallyLR
     %0:_(<8 x s16>) = COPY $q0
     %1:_(s32) = G_CONSTANT i32 1
     %val:_(s16) = G_CONSTANT i16 42
     %2:_(<8 x s16>) = G_INSERT_VECTOR_ELT %0(<8 x s16>), %val(s16), %1(s32)
     $q0 = COPY %2(<8 x s16>)
     RET_ReallyLR
 ...
 ---
 name:            v2s32
 body: |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: v2s32
-    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: %val:_(s32) = G_CONSTANT i32 42
-    ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
-    ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
-    ; CHECK: RET_ReallyLR
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: %val:_(s32) = G_CONSTANT i32 42
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
+    ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>)
+    ; CHECK-NEXT: RET_ReallyLR
     %0:_(<2 x s32>) = COPY $d0
     %1:_(s32) = G_CONSTANT i32 1
     %val:_(s32) = G_CONSTANT i32 42
     %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %val(s32), %1(s32)
     $d0 = COPY %2(<2 x s32>)
     RET_ReallyLR
 ...
 ---
 name:            v4s32
 body: |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: v4s32
-    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: %val:_(s32) = G_CONSTANT i32 42
-    ; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
-    ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
-    ; CHECK: RET_ReallyLR
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: %val:_(s32) = G_CONSTANT i32 42
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
+    ; CHECK-NEXT: $q0 = COPY [[IVEC]](<4 x s32>)
+    ; CHECK-NEXT: RET_ReallyLR
     %0:_(<4 x s32>) = COPY $q0
     %1:_(s32) = G_CONSTANT i32 1
     %val:_(s32) = G_CONSTANT i32 42
     %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0(<4 x s32>), %val(s32), %1(s32)
     $q0 = COPY %2(<4 x s32>)
     RET_ReallyLR
 ...
 ---
 name:            v2s64
 body: |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: v2s64
-    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: %val:_(s64) = G_CONSTANT i64 42
-    ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s32)
-    ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
-    ; CHECK: RET_ReallyLR
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: %val:_(s64) = G_CONSTANT i64 42
+    ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s32)
+    ; CHECK-NEXT: $q0 = COPY [[IVEC]](<2 x s64>)
+    ; CHECK-NEXT: RET_ReallyLR
     %0:_(<2 x s64>) = COPY $q0
     %1:_(s32) = G_CONSTANT i32 1
     %val:_(s64) = G_CONSTANT i64 42
     %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %0(<2 x s64>), %val(s64), %1(s32)
     $q0 = COPY %2(<2 x s64>)
     RET_ReallyLR
 ...