This is an archive of the discontinued LLVM Phabricator instance.

Differential D154978

[RISCV][GlobalISel] Legalize add, sub and binary logical instructions for narrow types
ClosedPublic

Authored by nitinjohnraj on Jul 11 2023, 8:53 AM.

Details

Reviewers
craig.topper
arsenm
lewis-revill
Commits
rG6a35ceaacf06: [RISCV][GlobalISel] Legalize add, sub and binary logical instructions for…
Summary

For rv32, we test the legalization of i8, i16 and i32. For rv64, we additionally test the legalization of i64.

This is the first of a series of commits aiming to legalize arithmetic instructions for RISCV.

Diff Detail

Event Timeline

nitinjohnraj created this revision.Jul 11 2023, 8:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 11 2023, 8:53 AM
Herald added subscribers: jobnoorman, luke, VincentWu and 28 others. · View Herald Transcript
nitinjohnraj requested review of this revision.Jul 11 2023, 8:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 11 2023, 8:53 AM
Herald added subscribers: llvm-commits, wangpc, eopXD and 2 others. · View Herald Transcript
craig.topper added a comment.Jul 11 2023, 9:33 AM

Can you work more information into the title to distinguish it from the other other 15 patches?

nitinjohnraj retitled this revision from [RISCV][GlobalISel][1/16] Legalize integer operations to [RISCV][GlobalISel] Legalize add, sub and binary logical instructions for narrow types.Jul 11 2023, 10:40 AM
nitinjohnraj edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B244502: Diff 539138.Jul 11 2023, 1:10 PM
nitinjohnraj updated this revision to Diff 539289.Jul 11 2023, 2:05 PM

Rebased

arsenm added inline comments.Jul 11 2023, 2:08 PM
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-and.mir
3

Don't need -global-isel in any mir tests

nitinjohnraj updated this revision to Diff 539350.Jul 11 2023, 5:46 PM

Tests don't need the --global-isel flag

arsenm accepted this revision.Jul 11 2023, 5:51 PM
This revision is now accepted and ready to land.Jul 11 2023, 5:51 PM
craig.topper accepted this revision.Jul 11 2023, 9:46 PM

LGTM

Harbormaster completed remote builds in B244650: Diff 539350.Jul 11 2023, 10:25 PM
nitinjohnraj marked an inline comment as done.Jul 12 2023, 9:41 AM
Closed by commit rG6a35ceaacf06: [RISCV][GlobalISel] Legalize add, sub and binary logical instructions for… (authored by nitinjohnraj). · Explain WhyJul 14 2023, 6:28 PM
This revision was automatically updated to reflect the committed changes.
nitinjohnraj added a commit: rG6a35ceaacf06: [RISCV][GlobalISel] Legalize add, sub and binary logical instructions for….

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
GISel/
10 lines
test/
CodeGen/
RISCV/
GlobalISel/
legalizer/
rv32/
58 lines
58 lines
58 lines
58 lines
58 lines
rv64/
77 lines
77 lines
77 lines
77 lines
77 lines

Diff 540610

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

//===-- RISCVLegalizerInfo.cpp ----------------------------------*- C++ -*-===// //===-- RISCVLegalizerInfo.cpp ----------------------------------*- C++ -*-===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// \file /// \file
/// This file implements the targeting of the Machinelegalizer class for RISC-V. /// This file implements the targeting of the Machinelegalizer class for RISC-V.
/// \todo This should be generated by TableGen. /// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "RISCVLegalizerInfo.h" #include "RISCVLegalizerInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h" #include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
using namespace llvm; using namespace llvm;
RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) { RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
const unsigned XLen = ST.getXLen();
const LLT XLenLLT = LLT::scalar(XLen);
using namespace TargetOpcode;
getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
.legalFor({XLenLLT})
.clampScalar(0, XLenLLT, XLenLLT);
getLegacyLegalizerInfo().computeTables(); getLegacyLegalizerInfo().computeTables();
} }

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: add_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: add_i8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
%3:_(s8) = G_TRUNC %1(s32)
%4:_(s8) = G_ADD %3, %4
%5:_(s32) = G_ANYEXT %4(s8)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: add_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: add_i16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
%3:_(s16) = G_TRUNC %1(s32)
%4:_(s16) = G_ADD %3, %4
%5:_(s32) = G_ANYEXT %4(s16)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: add_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: add_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_ADD %0, %1
$x10 = COPY %2(s32)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-and.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
arsenmUnsubmitted
Done
ReplyInline Actions

Don't need -global-isel in any mir tests

arsenm: Don't need -global-isel in any mir tests
---
name: and_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: and_i8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[AND]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
%3:_(s8) = G_TRUNC %1(s32)
%4:_(s8) = G_AND %3, %4
%5:_(s32) = G_ANYEXT %4(s8)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: and_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: and_i16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[AND]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
%3:_(s16) = G_TRUNC %1(s32)
%4:_(s16) = G_AND %3, %4
%5:_(s32) = G_ANYEXT %4(s16)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: and_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: and_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[AND]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_AND %0, %1
$x10 = COPY %2(s32)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-or.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: or_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: or_i8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[OR]]
; CHECK-NEXT: $x10 = COPY [[OR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
%3:_(s8) = G_TRUNC %1(s32)
%4:_(s8) = G_OR %3, %4
%5:_(s32) = G_ANYEXT %4(s8)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: or_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: or_i16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[OR]]
; CHECK-NEXT: $x10 = COPY [[OR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
%3:_(s16) = G_TRUNC %1(s32)
%4:_(s16) = G_OR %3, %4
%5:_(s32) = G_ANYEXT %4(s16)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: or_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: or_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[OR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_OR %0, %1
$x10 = COPY %2(s32)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: sub_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: sub_i8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[SUB]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
%3:_(s8) = G_TRUNC %1(s32)
%4:_(s8) = G_SUB %3, %4
%5:_(s32) = G_ANYEXT %4(s8)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: sub_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: sub_i16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[SUB]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
%3:_(s16) = G_TRUNC %1(s32)
%4:_(s16) = G_SUB %3, %4
%5:_(s32) = G_ANYEXT %4(s16)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: sub_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: sub_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_SUB %0, %1
$x10 = COPY %2(s32)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-xor.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: xor_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: xor_i8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[XOR]]
; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s8) = G_TRUNC %0(s32)
%3:_(s8) = G_TRUNC %1(s32)
%4:_(s8) = G_XOR %3, %4
%5:_(s32) = G_ANYEXT %4(s8)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: xor_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: xor_i16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[XOR]]
; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s16) = G_TRUNC %0(s32)
%3:_(s16) = G_TRUNC %1(s32)
%4:_(s16) = G_XOR %3, %4
%5:_(s32) = G_ANYEXT %4(s16)
$x10 = COPY %5(s32)
PseudoRET implicit $x10
...
---
name: xor_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: xor_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s32) = G_XOR %0, %1
$x10 = COPY %2(s32)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: add_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: add_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ADD]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_ADD %3, %4
%5:_(s64) = G_ANYEXT %4(s8)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: add_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: add_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ADD]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
%3:_(s16) = G_TRUNC %1(s64)
%4:_(s16) = G_ADD %3, %4
%5:_(s64) = G_ANYEXT %4(s16)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: add_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: add_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ADD]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_ADD %3, %4
%5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: add_i64
body: |
bb.0.entry:
; CHECK-LABEL: name: add_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_ADD %0, %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-and.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: and_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: and_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_AND %3, %4
%5:_(s64) = G_ANYEXT %4(s8)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: and_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: and_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
%3:_(s16) = G_TRUNC %1(s64)
%4:_(s16) = G_AND %3, %4
%5:_(s64) = G_ANYEXT %4(s16)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: and_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: and_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[AND]]
; CHECK-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_AND %3, %4
%5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: and_i64
body: |
bb.0.entry:
; CHECK-LABEL: name: and_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_AND %0, %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-or.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: or_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: or_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[OR]]
; CHECK-NEXT: $x10 = COPY [[OR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_OR %3, %4
%5:_(s64) = G_ANYEXT %4(s8)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: or_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: or_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[OR]]
; CHECK-NEXT: $x10 = COPY [[OR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
%3:_(s16) = G_TRUNC %1(s64)
%4:_(s16) = G_OR %3, %4
%5:_(s64) = G_ANYEXT %4(s16)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: or_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: or_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[OR]]
; CHECK-NEXT: $x10 = COPY [[OR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_OR %3, %4
%5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: or_i64
body: |
bb.0.entry:
; CHECK-LABEL: name: or_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[OR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_OR %0, %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: sub_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: sub_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[SUB]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_SUB %3, %4
%5:_(s64) = G_ANYEXT %4(s8)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: sub_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: sub_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[SUB]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
%3:_(s16) = G_TRUNC %1(s64)
%4:_(s16) = G_SUB %3, %4
%5:_(s64) = G_ANYEXT %4(s16)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: sub_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: sub_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[SUB]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_SUB %3, %4
%5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: sub_i64
body: |
bb.0.entry:
; CHECK-LABEL: name: sub_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_SUB %0, %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-xor.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name: xor_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: xor_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[XOR]]
; CHECK-NEXT: $x10 = COPY [[XOR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_XOR %3, %4
%5:_(s64) = G_ANYEXT %4(s8)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: xor_i16
body: |
bb.0.entry:
; CHECK-LABEL: name: xor_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[XOR]]
; CHECK-NEXT: $x10 = COPY [[XOR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64)
%3:_(s16) = G_TRUNC %1(s64)
%4:_(s16) = G_XOR %3, %4
%5:_(s64) = G_ANYEXT %4(s16)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: xor_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: xor_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[XOR]]
; CHECK-NEXT: $x10 = COPY [[XOR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_XOR %3, %4
%5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64)
PseudoRET implicit $x10
...
---
name: xor_i64
body: |
bb.0.entry:
; CHECK-LABEL: name: xor_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[XOR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(s64) = G_XOR %0, %1
$x10 = COPY %2(s64)
PseudoRET implicit $x10
...