[ARM] mark tMOVi32imm as killing flags

[simonwallis2]

Summary

Mark the tMOVi32imm pseudo instr as killing the flags register.

The pseudo instruction expands to a sequence of 7 movs/lsls/adds
instructions, which are all Thumb-1 flag setting instructions.

For a test case, take an existing arm test which checks for
"Don't CSE a cmp across a call that clobbers CPSR."
and retarget it at thumbv6m execute-only.

[stuij]

llvm/test/CodeGen/ARM/udivmodei5.ll

2 ↗

(On Diff #538623)

I would add a comment explaining why we're testing with XO here, as otherwise there's no way to guess the intent.

[simonwallis2]

Addressed review feedback by adding comment to test case.

[stuij]

llvm/test/CodeGen/ARM/udivmodei5.ll

2 ↗

(On Diff #538623)

perhaps be a bit more specific? to me stating the error message can still mean just about anything.

[simonwallis2]

removed incidental test case udivmodei5.ll, which was less important than the targeted test case cse-call.ll

[stuij]

LGTM. Thanks!

llvm/lib/Target/ARM/ARMInstrThumb.td

def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),
                                 [(set tGPR:$dst,
                                       (ARMWrapper tglobaladdr:$src))]>,
                      Requires<[IsThumb, DontUseMovt, DontGenExecuteOnly]>;
 
 // 32-bit immediate using mov/add with the 4 :lower0_7: to :upper8_15:
 // relocations.
 // This is a single pseudo instruction to make it re-materializable.
 // FIXME: Remove this when we can do generalized remat.
-let isReMaterializable = 1, isMoveImm = 1, Size = 16, hasNoSchedulingInfo = 1 in
+let Defs = [CPSR], isReMaterializable = 1, isMoveImm = 1, Size = 16, hasNoSchedulingInfo = 1 in
 def tMOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), NoItinerary,
                             [(set rGPR:$dst, (i32 imm:$src))]>,
                             Requires<[IsThumb1Only, GenExecuteOnly, DontUseMovt]>;
 
 def : ARMPat<(ARMWrapper  tglobaladdr :$dst), (tMOVi32imm tglobaladdr :$dst)>,
             Requires<[GenT1ExecuteOnly]>;
 def : ARMPat<(ARMWrapper texternalsym :$dst), (tMOVi32imm texternalsym :$dst)>,
             Requires<[GenT1ExecuteOnly]>;

llvm/test/CodeGen/ARM/cse-call.ll

-; RUN: llc < %s -mcpu=arm1136jf-s -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=armv6-apple-ios0.0.0 -mcpu=arm1136jf-s -verify-machineinstrs | FileCheck %s
+; RUN: llc -mtriple=thumbv6m-eabi -mattr=+execute-only -verify-machineinstrs %s -o - | FileCheck --check-prefix=CHECK-T1 %s
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
-target triple = "armv6-apple-ios0.0.0"
 
 ; Don't CSE a cmp across a call that clobbers CPSR.
 ;
 ; CHECK: cmp
+
+; CHECK-T1: movs [[REG:r[0-7]+]], :upper8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :upper0_7:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower0_7:
+
+; CHECK-T1: movs [[REG:r[0-7]+]], :upper8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :upper0_7:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower8_15:
+; CHECK-T1-NEXT: lsls    [[REG]], [[REG]], #8
+; CHECK-T1-NEXT: adds    [[REG]], :lower0_7:
+
+; CHECK-T1: cmp
+
 ; CHECK: S_trimzeros
 ; CHECK: cmp
 ; CHECK: strlen
 
 @F_floatmul.man1 = external global [200 x i8], align 1
 @F_floatmul.man2 = external global [200 x i8], align 1
 
 declare i32 @strlen(ptr nocapture) nounwind readonly