[AMDGPU] Fix ISD perm compute known bits wrong.

[bcl5980]

Summary

SelBits can be 7.

[foad]

LGTM but can this be tested?

[jrbyrnes]

It also LGTM, but I wonder why we aren't handling masks 0x08 - 0x0b here?

[arsenm]

Should get a test

[bcl5980]

I'm sorry I have no time to continue this work. So I will abandon this. Anyone who want to continue work on this is fine.

[foad]

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

5004

I can't find any test cases where handling PERM here has any effect. I've tested it on a large corpus of graphics shaders.

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

if (Opc == AMDGPUISD::MUL_I24) {
       unsigned RHSValBits = RHSKnown.countMaxActiveBits();
       unsigned MaxValBits = LHSValBits + RHSValBits;
       if (MaxValBits >= 32)
         break;
       Known.Zero.setBitsFrom(MaxValBits);
     }
     break;
   }
   case AMDGPUISD::PERM: {
     ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Op.getOperand(2));
     if (!CMask)
       return;
 
     KnownBits LHSKnown = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
     KnownBits RHSKnown = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
     unsigned Sel = CMask->getZExtValue();
 
     for (unsigned I = 0; I < 32; I += 8) {
       unsigned SelBits = Sel & 0xff;
       if (SelBits < 4) {
         SelBits *= 8;
         Known.One |= ((RHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
         Known.Zero |= ((RHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
-      } else if (SelBits < 7) {
+      } else if (SelBits < 8) {
         SelBits = (SelBits & 3) * 8;
         Known.One |= ((LHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
         Known.Zero |= ((LHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
       } else if (SelBits == 0x0c) {
         Known.Zero |= 0xFFull << I;
       } else if (SelBits > 0x0c) {
         Known.One |= 0xFFull << I;
       }