[PowerPC] Add DFP format instructions definitions and MC tests

[lei]

Summary

Add td definitions and asm/disasm tests for the dfp format
instructions in ISA 3.1 section 5.6.6

[lei]

remove unrelated new line

[kamaub]

This looks good to me, just some request that can be done pre-commit

llvm/lib/Target/PowerPC/PPCInstrDFP.td

105–108

I think we don't use these itineraries for these instructions at all right? Its still a bit odd to only apply the FPGeneral for the extract bias instructions only since all the others are also marked as "are treated as Floating-Point instructions in terms of resource availability.". Unless I misunderstood something about this instr specifically could you remove it here or apply it to each one, which ever you prefer.

105–126

According to isa3.1 section. 5.6.7, only the first four instruction, encoding and decoding, may raise a floating point exception, these remaining ones need to moved outside of the } // mayRaiseFPException brace I think.

[lei]

address review comments

[lei]

llvm/lib/Target/PowerPC/PPCInstrDFP.td

105–108

removing since we have no scheduling info currently for dfp instr.

105–126

keeping the 2 instr that raises exceptions here and moving the rest below.

[stefanp]

I only have one minor nit.
Otherwise, LGTM!

Feel free to address the nit when you commit the patch.

llvm/lib/Target/PowerPC/PPCInstrDFP.td

145

nit:
Should be f8rc:$RA.

[lei]

fix encoding for diexq

llvm/lib/Target/PowerPC/PPCInstrDFP.td

 //===-- PPCInstrDFP.td - PowerPC Decimal Floating Point ----*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the PowerPC Decimal Floating Point (DFP) instructions.
 //
 //===----------------------------------------------------------------------===//
 
 // We provide no scheduling info for the DFP instructions.
 // While they are not pseudo instructions we don't intend on scheduling them.
+
 let hasNoSchedulingInfo = 1 in {
 let mayRaiseFPException = 1, hasSideEffects = 0 in {
 
 let isCommutable = 1 in {
 defm DADD : XForm_28r<59, 2, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
                       "dadd",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
 
 defm DADDQ : XForm_28r<63, 2, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
defm DRINTXQ: Z23Form_FRTB5_R1_RMC2r<63, 99, (outs fpairrc:$FRT),
                                      (ins u1imm:$R, fpairrc:$FRB, u2imm:$RMC),
                                      "drintxq", "$R, $FRT, $FRB, $RMC", []>;
 defm DRINTN: Z23Form_FRTB5_R1_RMC2r<59, 227, (outs f8rc:$FRT),
                                     (ins u1imm:$R, f8rc:$FRB, u2imm:$RMC),
                                     "drintn", "$R, $FRT, $FRB, $RMC", []>;
 defm DRINTNQ: Z23Form_FRTB5_R1_RMC2r<63, 227, (outs fpairrc:$FRT),
                                      (ins u1imm:$R, fpairrc:$FRB, u2imm:$RMC),
                                      "drintnq", "$R, $FRT, $FRB, $RMC", []>;
+// 5.6.6 DFP Format Instructions
+defm DDEDPD: XForm_SP2_FRTB5r<59, 322, (outs f8rc:$FRT),
+                              (ins u2imm:$SP, f8rc:$FRB),
+                              "ddedpd", "$SP, $FRT, $FRB", []>;
+defm DDEDPDQ: XForm_SP2_FRTB5r<63, 322, (outs fpairrc:$FRT),
+                               (ins u2imm:$SP, fpairrc:$FRB),
+                               "ddedpdq", "$SP, $FRT, $FRB", []>;
+defm DENBCD: XForm_S1_FRTB5r<59, 834, (outs f8rc:$FRT),
+                              (ins u1imm:$S, f8rc:$FRB),
+                              "denbcd", "$S, $FRT, $FRB", []>;
+defm DENBCDQ: XForm_S1_FRTB5r<63, 834, (outs fpairrc:$FRT),
+                               (ins u1imm:$S, fpairrc:$FRB),
+                               "denbcdq", "$S, $FRT, $FRB", []>;
+defm DXEX: XForm_26r<59, 354, (outs f8rc:$RST), (ins f8rc:$RB),
+                     "dxex", "$RST, $RB", IIC_FPGeneral, []>;
+defm DXEXQ: XForm_26r<63, 354, (outs f8rc:$RST), (ins fpairrc:$RB),
+                      "dxexq", "$RST, $RB", IIC_FPGeneral, []>;
+defm DIEX: XForm_base_r3xo_r<59, 866, (outs f8rc:$RST),
+                             (ins f8rc:$RA, f8rc:$RB),
+                             "diex", "$RST, $RA, $RB", []>;
+defm DIEXQ: XForm_base_r3xo_r<63, 866, (outs fpairrc:$RST),
+                              (ins fpairrc:$RA, fpairrc:$RB),
+                              "diexq", "$RST, $RA, $RB", []>;
+defm DSCLI: Z22Form_FRTA5_SH6r<59, 66, (outs f8rc:$FRT),
+                               (ins f8rc:$FRA, u6imm:$SH),
+                               "dscli", "$FRT, $FRA, $SH", []>;
+defm DSCLIQ: Z22Form_FRTA5_SH6r<63, 66, (outs fpairrc:$FRT),
+                                (ins fpairrc:$FRA, u6imm:$SH),
+                                "dscliq", "$FRT, $FRA, $SH", []>;
+defm DSCRI: Z22Form_FRTA5_SH6r<59, 98, (outs f8rc:$FRT),
+                               (ins f8rc:$FRA, u6imm:$SH),
+                               "dscri", "$FRT, $FRA, $SH", []>;
+defm DSCRIQ: Z22Form_FRTA5_SH6r<63, 98, (outs fpairrc:$FRT),
+                                (ins fpairrc:$FRA, u6imm:$SH),
+                                "dscriq", "$FRT, $FRA, $SH", []>;
 
 } // mayRaiseFPException
 } // hasNoSchedulingInfo
 

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
 
   let Inst{6-10}  = D{4-0};  // D
   let Inst{11-15} = RA;
   let Inst{16-20} = RB;
   let Inst{21-30} = xo;
   let Inst{31}    = D{5};    // DX
 }
 
+class XForm_SP2_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+                  list<dag> pattern, InstrItinClass itin>
+    : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<2> SP;
+  bits<5> FRT;
+  bits<5> FRB;
+
+  let Pattern = pattern;
+
+  bit RC = 0; // set by isRecordForm
+
+  let Inst{6 - 10} = FRT;
+  let Inst{11 - 12} = SP;
+  let Inst{13 - 15} = 0;
+  let Inst{16 - 20} = FRB;
+  let Inst{21 - 30} = xo;
+  let Inst{31} = RC;
+}
+
+class XForm_S1_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                 string asmstr, list<dag> pattern, InstrItinClass itin>
+    : I<opcode, OOL, IOL, asmstr, itin> {
+  bit S;
+  bits<5> FRT;
+  bits<5> FRB;
+
+  let Pattern = pattern;
+
+  bit RC = 0; // set by isRecordForm
+
+  let Inst{6 - 10} = FRT;
+  let Inst{11} = S;
+  let Inst{12 - 15} = 0;
+  let Inst{16 - 20} = FRB;
+  let Inst{21 - 30} = xo;
+  let Inst{31} = RC;
+}
+
 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<6> XT;
   bits<6> XA;
   bits<6> XB;
 
   let Pattern = pattern;
class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
   let Inst{6-10}  = VD;
   let Inst{11-15} = VA;
   let Inst{16-20} = VB;
   let Inst{21}    = 1;
   let Inst{22}    = PS;
   let Inst{23-31} = xo;
 }
 
+class Z22Form_FRTA5_SH6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+              string asmstr, list<dag> pattern, InstrItinClass itin>
+    : I<opcode, OOL, IOL, asmstr, itin> {
+
+  bits<5> FRT;
+  bits<5> FRA;
+  bits<6> SH;
+
+  let Pattern = pattern;
+
+  bit RC = 0; // set by isRecordForm
+
+  let Inst{6 - 10} = FRT;
+  let Inst{11 - 15} = FRA;
+  let Inst{16 - 21} = SH;
+  let Inst{22 - 30} = xo;
+  let Inst{31} = RC;
+}
+
 class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> VRT;
   bit R;
   bits<5> VRB;
   bits<2> idx;
 

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">,
                  AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>;
 def IsAIX : Predicate<"Subtarget->isAIXABI()">;
 def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
 def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
 def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Multiclass Definitions.
+multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                      string asmbase, string asmstr, list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : XForm_base_r3xo<opcode, xo, OOL, IOL,
+                                !strconcat(asmbase, !strconcat(" ", asmstr)),
+                                NoItinerary, pattern>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : XForm_base_r3xo<opcode, xo, OOL, IOL,
+                               !strconcat(asmbase, !strconcat(". ", asmstr)),
+                               NoItinerary, []>, isRecordForm, RecFormRel;
+  }
+}
 
 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : XForm_6<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
def NAME : XForm_28<opcode, xo, OOL, IOL,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
     def _rec    : XForm_28<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isRecordForm, RecFormRel;
   }
 }
 
+multiclass XForm_SP2_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                        string asmbase, string asmstr, list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : XForm_SP2_FRTB5<opcode, xo, OOL, IOL,
+                               !strconcat(asmbase, !strconcat(" ", asmstr)),
+                               pattern, NoItinerary>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : XForm_SP2_FRTB5<opcode, xo, OOL, IOL,
+                               !strconcat(asmbase, !strconcat(". ", asmstr)),
+                               [], NoItinerary>, isRecordForm, RecFormRel;
+  }
+}
+
+multiclass XForm_S1_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                      string asmbase, string asmstr, list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : XForm_S1_FRTB5<opcode, xo, OOL, IOL,
+                              !strconcat(asmbase, !strconcat(" ", asmstr)),
+                              pattern, NoItinerary>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : XForm_S1_FRTB5<opcode, xo, OOL, IOL,
+                              !strconcat(asmbase, !strconcat(". ", asmstr)), [],
+                              NoItinerary>, isRecordForm, RecFormRel;
+  }
+}
+
 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
     def NAME : AForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
def NAME : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL,
                                pattern>, RecFormRel;
     let Defs = [CR1] in
     def _rec : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL,
                                !strconcat(asmbase, !strconcat(". ", asmstr)),
                                []>, isRecordForm, RecFormRel;
   }
 }
 
+multiclass Z22Form_FRTA5_SH6r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+                      string asmbase, string asmstr, list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL,
+                                 !strconcat(asmbase, !strconcat(" ", asmstr)),
+                                 pattern, NoItinerary>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL,
+                                 !strconcat(asmbase, !strconcat(". ", asmstr)),
+                                 [], NoItinerary>, isRecordForm, RecFormRel;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // END OF MULTICLASS DEFINITIONS
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Definitions.
 
 // Pseudo instructions:

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt

 # CHECK: drintn. 1, 10, 6, 2
 0xed 0x41 0x35 0xc7
 
 # CHECK: drintnq 1, 10, 6, 2
 0xfd 0x41 0x35 0xc6
 
 # CHECK: drintnq. 0, 10, 6, 2
 0xfd 0x40 0x35 0xc7
+
+# CHECK: ddedpd 0, 8, 10
+0xed 0x00 0x52 0x84
+
+# CHECK: ddedpd. 0, 8, 10
+0xed 0x00 0x52 0x85
+
+# CHECK: ddedpdq 1, 8, 10
+0xfd 0x08 0x52 0x84
+
+# CHECK: ddedpdq. 1, 8, 10
+0xfd 0x08 0x52 0x85
+
+# CHECK: denbcd 1, 12, 16
+0xed 0x90 0x86 0x84
+
+# CHECK: denbcd. 0, 12, 16
+0xed 0x80 0x86 0x85
+
+# CHECK: denbcdq 1, 12, 16
+0xfd 0x90 0x86 0x84
+
+# CHECK: denbcdq. 0, 12, 16
+0xfd 0x80 0x86 0x85
+
+# CHECK: dxex 8, 20
+0xed 0x00 0xa2 0xc4
+
+# CHECK: dxex. 8, 20
+0xed 0x00 0xa2 0xc5
+
+# CHECK: dxexq 8, 20
+0xfd 0x00 0xa2 0xc4
+
+# CHECK: dxexq. 8, 20
+0xfd 0x00 0xa2 0xc5
+
+# CHECK: diex 8, 12, 18
+0xed 0x0c 0x96 0xc4
+
+# CHECK: diex. 8, 12, 18
+0xed 0x0c 0x96 0xc5
+
+# CHECK: diexq. 8, 12, 18
+0xfd 0x0c 0x96 0xc5
+
+# CHECK: diexq 8, 12, 18
+0xfd 0x0c 0x96 0xc4
+
+# CHECK: dscli 22, 4, 63
+0xee 0xc4 0xfc 0x84
+
+# CHECK: dscli. 22, 4, 63
+0xee 0xc4 0xfc 0x85
+
+# CHECK: dscliq 22, 4, 63
+0xfe 0xc4 0xfc 0x84
+
+# CHECK: dscliq. 22, 4, 63
+0xfe 0xc4 0xfc 0x85
+
+# CHECK: dscri 16, 10, 50
+0xee 0x0a 0xc8 0xc4
+
+# CHECK: dscri. 16, 10, 50
+0xee 0x0a 0xc8 0xc5
+
+# CHECK: dscriq 16, 10, 50
+0xfe 0x0a 0xc8 0xc4
+
+# CHECK: dscriq. 16, 10, 50
+0xfe 0x0a 0xc8 0xc5

llvm/test/MC/PowerPC/ppc64-encoding-dfp.s

 # CHECK-BE: drintn. 0, 10, 6, 2            # encoding: [0xed,0x40,0x35,0xc7]
             drintn. 0, 10, 6, 2
 # CHECK-LE: drintnq 0, 10, 6, 2            # encoding: [0xc6,0x35,0x40,0xfd]
 # CHECK-BE: drintnq 0, 10, 6, 2            # encoding: [0xfd,0x40,0x35,0xc6]
             drintnq 0, 10, 6, 2
 # CHECK-LE: drintnq. 1, 10, 6, 2           # encoding: [0xc7,0x35,0x41,0xfd]
 # CHECK-BE: drintnq. 1, 10, 6, 2           # encoding: [0xfd,0x41,0x35,0xc7]
             drintnq. 1, 10, 6, 2
+# CHECK-BE: ddedpd 0, 8, 10                # encoding: [0xed,0x00,0x52,0x84]
+# CHECK-LE: ddedpd 0, 8, 10                # encoding: [0x84,0x52,0x00,0xed]
+            ddedpd 0, 8, 10
+# CHECK-BE: ddedpd. 0, 8, 10               # encoding: [0xed,0x00,0x52,0x85]
+# CHECK-LE: ddedpd. 0, 8, 10               # encoding: [0x85,0x52,0x00,0xed]
+            ddedpd. 0, 8, 10
+# CHECK-BE: ddedpdq 1, 8, 10               # encoding: [0xfd,0x08,0x52,0x84]
+# CHECK-LE: ddedpdq 1, 8, 10               # encoding: [0x84,0x52,0x08,0xfd]
+            ddedpdq 1, 8, 10
+# CHECK-BE: ddedpdq. 1, 8, 10              # encoding: [0xfd,0x08,0x52,0x85]
+# CHECK-LE: ddedpdq. 1, 8, 10              # encoding: [0x85,0x52,0x08,0xfd]
+            ddedpdq. 1, 8, 10
+# CHECK-BE: denbcd 1, 12, 16               # encoding: [0xed,0x90,0x86,0x84]
+# CHECK-LE: denbcd 1, 12, 16               # encoding: [0x84,0x86,0x90,0xed]
+            denbcd 1, 12, 16
+# CHECK-BE: denbcd. 0, 12, 16              # encoding: [0xed,0x80,0x86,0x85]
+# CHECK-LE: denbcd. 0, 12, 16              # encoding: [0x85,0x86,0x80,0xed]
+            denbcd. 0, 12, 16
+# CHECK-BE: denbcdq 1, 12, 16              # encoding: [0xfd,0x90,0x86,0x84]
+# CHECK-LE: denbcdq 1, 12, 16              # encoding: [0x84,0x86,0x90,0xfd]
+            denbcdq 1, 12, 16
+# CHECK-BE: denbcdq. 0, 12, 16             # encoding: [0xfd,0x80,0x86,0x85]
+# CHECK-LE: denbcdq. 0, 12, 16             # encoding: [0x85,0x86,0x80,0xfd]
+            denbcdq. 0, 12, 16
+# CHECK-BE: dxex 8, 20                     # encoding: [0xed,0x00,0xa2,0xc4]
+# CHECK-LE: dxex 8, 20                     # encoding: [0xc4,0xa2,0x00,0xed]
+            dxex 8, 20
+# CHECK-BE: dxex. 8, 20                    # encoding: [0xed,0x00,0xa2,0xc5]
+# CHECK-LE: dxex. 8, 20                    # encoding: [0xc5,0xa2,0x00,0xed]
+            dxex. 8, 20
+# CHECK-BE: dxexq 8, 20                    # encoding: [0xfd,0x00,0xa2,0xc4]
+# CHECK-LE: dxexq 8, 20                    # encoding: [0xc4,0xa2,0x00,0xfd]
+            dxexq 8, 20
+# CHECK-BE: dxexq. 8, 20                   # encoding: [0xfd,0x00,0xa2,0xc5]
+# CHECK-LE: dxexq. 8, 20                   # encoding: [0xc5,0xa2,0x00,0xfd]
+            dxexq. 8, 20
+# CHECK-BE: diex 8, 12, 18                 # encoding: [0xed,0x0c,0x96,0xc4]
+# CHECK-LE: diex 8, 12, 18                 # encoding: [0xc4,0x96,0x0c,0xed]
+            diex 8, 12, 18
+# CHECK-BE: diex. 8, 12, 18                # encoding: [0xed,0x0c,0x96,0xc5]
+# CHECK-LE: diex. 8, 12, 18                # encoding: [0xc5,0x96,0x0c,0xed]
+            diex. 8, 12, 18
+# CHECK-BE: diexq 8, 12, 18                # encoding: [0xfd,0x0c,0x96,0xc4]
+# CHECK-LE: diexq 8, 12, 18                # encoding: [0xc4,0x96,0x0c,0xfd]
+            diexq 8, 12, 18
+# CHECK-BE: diexq. 8, 12, 18               # encoding: [0xfd,0x0c,0x96,0xc5]
+# CHECK-LE: diexq. 8, 12, 18               # encoding: [0xc5,0x96,0x0c,0xfd]
+            diexq. 8, 12, 18
+# CHECK-BE: dscli 22, 4, 63                # encoding: [0xee,0xc4,0xfc,0x84]
+# CHECK-LE: dscli 22, 4, 63                # encoding: [0x84,0xfc,0xc4,0xee]
+            dscli 22, 4, 63
+# CHECK-BE: dscli. 22, 4, 63               # encoding: [0xee,0xc4,0xfc,0x85]
+# CHECK-LE: dscli. 22, 4, 63               # encoding: [0x85,0xfc,0xc4,0xee]
+            dscli. 22, 4, 63
+# CHECK-BE: dscliq 22, 4, 63               # encoding: [0xfe,0xc4,0xfc,0x84]
+# CHECK-LE: dscliq 22, 4, 63               # encoding: [0x84,0xfc,0xc4,0xfe]
+            dscliq 22, 4, 63
+# CHECK-BE: dscliq. 22, 4, 63              # encoding: [0xfe,0xc4,0xfc,0x85]
+# CHECK-LE: dscliq. 22, 4, 63              # encoding: [0x85,0xfc,0xc4,0xfe]
+            dscliq. 22, 4, 63
+# CHECK-BE: dscri 16, 10, 50               # encoding: [0xee,0x0a,0xc8,0xc4]
+# CHECK-LE: dscri 16, 10, 50               # encoding: [0xc4,0xc8,0x0a,0xee]
+            dscri 16, 10, 50
+# CHECK-BE: dscri. 16, 10, 50              # encoding: [0xee,0x0a,0xc8,0xc5]
+# CHECK-LE: dscri. 16, 10, 50              # encoding: [0xc5,0xc8,0x0a,0xee]
+            dscri. 16, 10, 50
+# CHECK-BE: dscriq 16, 10, 50              # encoding: [0xfe,0x0a,0xc8,0xc4]
+# CHECK-LE: dscriq 16, 10, 50              # encoding: [0xc4,0xc8,0x0a,0xfe]
+            dscriq 16, 10, 50
+# CHECK-BE: dscriq. 16, 10, 50             # encoding: [0xfe,0x0a,0xc8,0xc5]
+# CHECK-LE: dscriq. 16, 10, 50             # encoding: [0xc5,0xc8,0x0a,0xfe]
+            dscriq. 16, 10, 50