[AMDGPU] Fix incorrect hazard mitigation

[stepthomas]

Summary

GCNHazardRecognizer::fixVcmpxExecWARHazard() mitigates a specific hazard
by inserting a wait on sa_sdst==0 if such a wait isn't already present.
Unfortunately, the check for an existing wait incorrectly checks for one
that doesn't actually care about sa_sdst itself, but requires that no
other counters are waited for.

Once the check is performed correctly, a lit test needs to be updated,
since it is currently testing for the incorrect behaviour.

[foad]

LGTM with or without nit.

llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir

149

If you're renaming tests, maybe change this one to no_hazard_?

[stepthomas]

llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir

149

I did consider this, but decided that the test was illustrating a case where the was a hazard, it's just that the hazard recognizer had now correctly identified that it was already mitigated.

llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

auto IsExpiredFn = [TII, TRI](const MachineInstr &MI, int) {
     if (SIInstrInfo::isVALU(MI)) {
       if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst))
         return true;
       for (auto MO : MI.implicit_operands())
         if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg())))
           return true;
     }
     if (MI.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR &&
-        AMDGPU::DepCtr::encodeFieldSaSdst(MI.getOperand(0).getImm(), 0) ==
-            0xfffe)
+        AMDGPU::DepCtr::decodeFieldSaSdst(MI.getOperand(0).getImm()) == 0)
       return true;
     return false;
   };
 
   if (::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn) ==
       std::numeric_limits<int>::max())
     return false;
 

llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir

bb.0:
     S_WAITCNT_DEPCTR 65534
     V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     S_ENDPGM 0
 ...
 
-# GCN-LABEL: name: no_hazard_vcmpx_smov_exec_lo_depctr_ffff
-# GCN:      $sgpr0 = S_MOV_B32 $exec_lo
-# GCN-NEXT: S_WAITCNT_DEPCTR 65535
-# GCN-NEXT: V_CMPX_LE_F32_nosdst_e32
+# GCN-LABEL: name: hazard_vcmpx_smov_exec_lo_depctr_ffff
+# GCN:        $sgpr0 = S_MOV_B32 $exec_lo
+# GCN-NEXT:   S_WAITCNT_DEPCTR 65535
+# GFX10-NEXT: S_WAITCNT_DEPCTR 65534
+# GCN-NEXT:   V_CMPX_LE_F32_nosdst_e32
 ---
-name:            no_hazard_vcmpx_smov_exec_lo_depctr_ffff
+name:            hazard_vcmpx_smov_exec_lo_depctr_ffff
 body:            |
   bb.0:
     successors: %bb.1
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $sgpr0 = S_MOV_B32 $exec_lo
     S_WAITCNT_DEPCTR 65535
     V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: hazard_vcmpx_smov_exec_lo_depctr_effe
 # GCN:        $sgpr0 = S_MOV_B32 $exec_lo
 # GCN-NEXT:   S_WAITCNT_DEPCTR 61438
-# GFX10-NEXT: S_WAITCNT_DEPCTR 65534
 # GCN-NEXT:   V_CMPX_LE_F32_nosdst_e32
 ---
 name:            hazard_vcmpx_smov_exec_lo_depctr_effe
 body:            |
   bb.0:
     successors: %bb.1
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $sgpr0 = S_MOV_B32 $exec_lo
     S_WAITCNT_DEPCTR 61438
     V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     S_ENDPGM 0
 ...