[PowerPC] Add DFP quantum adjustment instruction definitions and MC tests

[lei]

Summary

Add td definitions and asm/disasm tests for the quantum adjustment
instructions in ISA 3.1 section 5.6.4

[lei]

fix indentation

[lei]

clang-format

[stefanp]

I think this mostly looks good all I found was a couple of typos in two instructions.

llvm/lib/Target/PowerPC/PPCInstrDFP.td

178

Typo:
I think that this instruction is drrnd.

181

Typo:
This one too. I think it is drrndq.

[lei]

llvm/lib/Target/PowerPC/PPCInstrDFP.td

181

Ops ... thanks for catching that!

[lei]

fix error in instruction name from drmd[q] to drrnd[q].

[stefanp]

I have one more nit that I missed the first time around.

I will approve the patch and the nit can be addressed on commit.

llvm/lib/Target/PowerPC/PPCInstrDFP.td

180

nit:
Missed this the first time.
$FRA is actually f8rc.

[lei]

fix f8rc reg

[lei]

Move class and multi class def.

[stefanp]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrDFP.td

 //===-- PPCInstrDFP.td - PowerPC Decimal Floating Point ----*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the PowerPC Decimal Floating Point (DFP) instructions.
 //
 //===----------------------------------------------------------------------===//
 
+class Z23Form_TE5_FRTB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+                             string asmstr, list<dag> pattern>
+         : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+  bits<5> TE;
+  bits<5> FRT;
+  bits<5> FRB;
+  bits<2> RMC;
+
+  let Pattern = pattern;
+
+  bit RC = 0;    // set by isRecordForm
+
+  let Inst{6-10}  = FRT;
+  let Inst{11-15} = TE;
+  let Inst{16-20} = FRB;
+  let Inst{21-22} = RMC;
+  let Inst{23-30} = xo;
+  let Inst{31}    = RC;
+}
+
+multiclass Z23Form_TE5_FRTB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+                                   string asmbase, string asmstr,
+                                   list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL,
+                               !strconcat(asmbase, !strconcat(" ", asmstr)),
+                               pattern>, RecFormRel;
+    let Defs = [CR0] in
+    def _rec : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL,
+                               !strconcat(asmbase, !strconcat(". ", asmstr)),
+                               []>, isRecordForm, RecFormRel;
+  }
+}
+
+class Z23Form_FRTAB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+                          string asmstr, list<dag> pattern>
+         : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+  bits<5> FRT;
+  bits<5> FRA;
+  bits<5> FRB;
+  bits<2> RMC;
+
+  let Pattern = pattern;
+
+  bit RC = 0;    // set by isRecordForm
+
+  let Inst{6-10}  = FRT;
+  let Inst{11-15} = FRA;
+  let Inst{16-20} = FRB;
+  let Inst{21-22} = RMC;
+  let Inst{23-30} = xo;
+  let Inst{31}    = RC;
+}
+
+multiclass Z23Form_FRTAB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+                                string asmbase, string asmstr,
+                                list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL,
+                                   !strconcat(asmbase, !strconcat(" ", asmstr)),
+                                   pattern>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL,
+                                   !strconcat(asmbase, !strconcat(". ", asmstr)),
+                                   []>, isRecordForm, RecFormRel;
+  }
+}
+
+class Z23Form_FRTB5_R1_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+                            string asmstr, list<dag> pattern>
+         : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+  bits<5> FRT;
+  bits<1> R;
+  bits<5> FRB;
+  bits<2> RMC;
+
+  let Pattern = pattern;
+
+  bit RC = 0;    // set by isRecordForm
+
+  let Inst{6-10}  = FRT;
+  let Inst{11-14} = 0;
+  let Inst{15}    = R;
+  let Inst{16-20} = FRB;
+  let Inst{21-22} = RMC;
+  let Inst{23-30} = xo;
+  let Inst{31}    = RC;
+}
+
+multiclass Z23Form_FRTB5_R1_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+                                  string asmbase, string asmstr,
+                                  list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL,
+                               !strconcat(asmbase, !strconcat(" ", asmstr)),
+                               pattern>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL,
+                               !strconcat(asmbase, !strconcat(". ", asmstr)),
+                               []>, isRecordForm, RecFormRel;
+  }
+}
+
 // We provide no scheduling info for the DFP instructions.
 // While they are not pseudo instructions we don't intend on scheduling them.
 let hasNoSchedulingInfo = 1 in {
 let mayRaiseFPException = 1, hasSideEffects = 0 in {
 
 let isCommutable = 1 in {
 defm DADD : XForm_28r<59, 2, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
                       "dadd",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
def DCMPUQ : XForm_17<63, 642, (outs crrc:$BF), (ins fpairrc:$RA, fpairrc:$RB),
                         "dcmpuq $BF, $RA, $RB", IIC_FPCompare>;
 
   def DCMPO : XForm_17<59, 130, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
                        "dcmpo $BF, $RA, $RB", IIC_FPCompare>;
 
   def DCMPOQ : XForm_17<63, 130, (outs crrc:$BF), (ins fpairrc:$RA, fpairrc:$RB),
                         "dcmpoq $BF, $RA, $RB", IIC_FPCompare>;
 }
-}
-}
+
+// 5.6.4 DFP Quantum Adjustment Instructions
+defm DQUAI: Z23Form_TE5_FRTB5_RMC2r<59, 67, (outs f8rc:$FRT),
+                                    (ins s5imm:$TE, f8rc:$FRB, u2imm:$RMC),
+                                    "dquai", "$TE, $FRT, $FRB, $RMC", []>;
+defm DQUAIQ: Z23Form_TE5_FRTB5_RMC2r<63, 67, (outs fpairrc:$FRT),
+                                     (ins s5imm:$TE, fpairrc:$FRB, u2imm:$RMC),
+                                     "dquaiq", "$TE, $FRT, $FRB, $RMC", []>;
+defm DQUA: Z23Form_FRTAB5_RMC2r<59, 3, (outs f8rc:$FRT),
+                                (ins f8rc:$FRA, f8rc:$FRB, u2imm:$RMC),
+                                "dqua", "$FRT, $FRA, $FRB, $RMC", []>;
+defm DQUAQ: Z23Form_FRTAB5_RMC2r<63, 3, (outs fpairrc:$FRT),
+                                 (ins fpairrc:$FRA, fpairrc:$FRB, u2imm:$RMC),
+                                 "dquaq", "$FRT, $FRA, $FRB, $RMC", []>;
+defm DRMD: Z23Form_FRTAB5_RMC2r<59, 35, (outs f8rc:$FRT),
+                                (ins f8rc:$FRA, f8rc:$FRB, u2imm:$RMC),
+                                "drmd", "$FRT, $FRA, $FRB, $RMC", []>;
+defm DRMDQ: Z23Form_FRTAB5_RMC2r<63, 35, (outs fpairrc:$FRT),
+                                 (ins fpairrc:$FRA, fpairrc:$FRB, u2imm:$RMC),
+                                 "drmdq", "$FRT, $FRA, $FRB, $RMC", []>;
+defm DRINTX: Z23Form_FRTB5_R1_RMC2r<59, 99, (outs f8rc:$FRT),
+                                    (ins u1imm:$R, f8rc:$FRB, u2imm:$RMC),
+                                    "drintx", "$R, $FRT, $FRB, $RMC", []>;
+defm DRINTXQ: Z23Form_FRTB5_R1_RMC2r<63, 99, (outs fpairrc:$FRT),
+                                     (ins u1imm:$R, fpairrc:$FRB, u2imm:$RMC),
+                                     "drintxq", "$R, $FRT, $FRB, $RMC", []>;
+defm DRINTN: Z23Form_FRTB5_R1_RMC2r<59, 227, (outs f8rc:$FRT),
+                                    (ins u1imm:$R, f8rc:$FRB, u2imm:$RMC),
+                                    "drintn", "$R, $FRT, $FRB, $RMC", []>;
+defm DRINTNQ: Z23Form_FRTB5_R1_RMC2r<63, 227, (outs fpairrc:$FRT),
+                                     (ins u1imm:$R, fpairrc:$FRB, u2imm:$RMC),
+                                     "drintnq", "$R, $FRT, $FRB, $RMC", []>;
+
+} // mayRaiseFPException
+} // hasNoSchedulingInfo
 

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt

 # CHECK: dcmpuq 2, 6, 4
 0xfd 0x06 0x25 0x04
 
 # CHECK: dcmpo 2, 6, 4
 0xed 0x06 0x21 0x04
 
 # CHECK: dcmpoq 2, 6, 4
 0xfd 0x06 0x21 0x04
+
+# CHECK: dquai 15, 8, 4, 3
+0xed 0x0f 0x26 0x86
+
+# CHECK: dquai. 15, 8, 4, 3
+0xed 0x0f 0x26 0x87
+
+# CHECK: dquaiq 15, 8, 4, 3
+0xfd 0x0f 0x26 0x86
+
+# CHECK: dquaiq. 15, 8, 4, 3
+0xfd 0x0f 0x26 0x87
+
+# CHECK: dqua 7, 15, 4, 2
+0xec 0xef 0x24 0x06
+
+# CHECK: dqua. 7, 15, 4, 2
+0xec 0xef 0x24 0x07
+
+# CHECK: dquaq 6, 14, 4, 2
+0xfc 0xce 0x24 0x06
+
+# CHECK: dquaq. 6, 14, 4, 2
+0xfc 0xce 0x24 0x07
+
+# CHECK: drmd 8, 12, 6, 2
+0xed 0x0c 0x34 0x46
+
+# CHECK: drmd. 8, 12, 6, 2
+0xed 0x0c 0x34 0x47
+
+# CHECK: drmdq 8, 12, 6, 2
+0xfd 0x0c 0x34 0x46
+
+# CHECK: drmdq. 8, 12, 6, 2
+0xfd 0x0c 0x34 0x47
+
+# CHECK: drintx 1, 8, 10, 3
+0xed 0x01 0x56 0xc6
+
+# CHECK: drintx. 0, 8, 10, 3
+0xed 0x00 0x56 0xc7
+
+# CHECK: drintxq 0, 8, 10, 3
+0xfd 0x00 0x56 0xc6
+
+# CHECK: drintxq. 1, 8, 10, 3
+0xfd 0x01 0x56 0xc7
+
+# CHECK: drintn 0, 10, 6, 2
+0xed 0x40 0x35 0xc6
+
+# CHECK: drintn. 1, 10, 6, 2
+0xed 0x41 0x35 0xc7
+
+# CHECK: drintnq 1, 10, 6, 2
+0xfd 0x41 0x35 0xc6
+
+# CHECK: drintnq. 0, 10, 6, 2
+0xfd 0x40 0x35 0xc7

llvm/test/MC/PowerPC/ppc64-encoding-dfp.s

 # CHECK-LE: dcmpuq 2, 6, 4                 # encoding: [0x04,0x25,0x06,0xfd]
             dcmpuq 2, 6, 4
 # CHECK-BE: dcmpo 2, 6, 4                  # encoding: [0xed,0x06,0x21,0x04]
 # CHECK-LE: dcmpo 2, 6, 4                  # encoding: [0x04,0x21,0x06,0xed]
             dcmpo 2, 6, 4
 # CHECK-BE: dcmpoq 2, 6, 4                 # encoding: [0xfd,0x06,0x21,0x04]
 # CHECK-LE: dcmpoq 2, 6, 4                 # encoding: [0x04,0x21,0x06,0xfd]
             dcmpoq 2, 6, 4
+# CHECK-BE: dquai 15, 8, 4, 3              # encoding: [0xed,0x0f,0x26,0x86]
+# CHECK-LE: dquai 15, 8, 4, 3              # encoding: [0x86,0x26,0x0f,0xed]
+            dquai 15, 8, 4, 3
+# CHECK-BE: dquai. 15, 8, 4, 3             # encoding: [0xed,0x0f,0x26,0x87]
+# CHECK-LE: dquai. 15, 8, 4, 3             # encoding: [0x87,0x26,0x0f,0xed]
+            dquai. 15, 8, 4, 3
+# CHECK-BE: dquaiq 15, 8, 4, 3             # encoding: [0xfd,0x0f,0x26,0x86]
+# CHECK-LE: dquaiq 15, 8, 4, 3             # encoding: [0x86,0x26,0x0f,0xfd]
+            dquaiq 15, 8, 4, 3
+# CHECK-BE: dquaiq. 15, 8, 4, 3            # encoding: [0xfd,0x0f,0x26,0x87]
+# CHECK-LE: dquaiq. 15, 8, 4, 3            # encoding: [0x87,0x26,0x0f,0xfd]
+            dquaiq. 15, 8, 4, 3
+# CHECK-BE: dqua 7, 15, 4, 2               # encoding: [0xec,0xef,0x24,0x06]
+# CHECK-LE: dqua 7, 15, 4, 2               # encoding: [0x06,0x24,0xef,0xec]
+            dqua 7, 15, 4, 2
+# CHECK-BE: dqua. 7, 15, 4, 2              # encoding: [0xec,0xef,0x24,0x07]
+# CHECK-LE: dqua. 7, 15, 4, 2              # encoding: [0x07,0x24,0xef,0xec]
+            dqua. 7, 15, 4, 2
+# CHECK-BE: dquaq 6, 14, 4, 2              # encoding: [0xfc,0xce,0x24,0x06]
+# CHECK-LE: dquaq 6, 14, 4, 2              # encoding: [0x06,0x24,0xce,0xfc]
+            dquaq 6, 14, 4, 2
+# CHECK-BE: dquaq. 6, 14, 4, 2             # encoding: [0xfc,0xce,0x24,0x07]
+# CHECK-LE: dquaq. 6, 14, 4, 2             # encoding: [0x07,0x24,0xce,0xfc]
+            dquaq. 6, 14, 4, 2
+# CHECK-BE: drmd 8, 12, 6, 2               # encoding: [0xed,0x0c,0x34,0x46]
+# CHECK-LE: drmd 8, 12, 6, 2               # encoding: [0x46,0x34,0x0c,0xed]
+            drmd 8, 12, 6, 2
+# CHECK-BE: drmd. 8, 12, 6, 2              # encoding: [0xed,0x0c,0x34,0x47]
+# CHECK-LE: drmd. 8, 12, 6, 2              # encoding: [0x47,0x34,0x0c,0xed]
+            drmd. 8, 12, 6, 2
+# CHECK-BE: drmdq 8, 12, 6, 2              # encoding: [0xfd,0x0c,0x34,0x46]
+# CHECK-LE: drmdq 8, 12, 6, 2              # encoding: [0x46,0x34,0x0c,0xfd]
+            drmdq 8, 12, 6, 2
+# CHECK-BE: drmdq. 8, 12, 6, 2             # encoding: [0xfd,0x0c,0x34,0x47]
+# CHECK-LE: drmdq. 8, 12, 6, 2             # encoding: [0x47,0x34,0x0c,0xfd]
+            drmdq. 8, 12, 6, 2
+# CHECK-LE: drintx 0, 8, 10, 3             # encoding: [0xc6,0x56,0x00,0xed]
+# CHECK-BE: drintx 0, 8, 10, 3             # encoding: [0xed,0x00,0x56,0xc6]
+            drintx 0, 8, 10, 3
+# CHECK-LE: drintx. 1, 8, 10, 3            # encoding: [0xc7,0x56,0x01,0xed]
+# CHECK-BE: drintx. 1, 8, 10, 3            # encoding: [0xed,0x01,0x56,0xc7]
+            drintx. 1, 8, 10, 3
+# CHECK-LE: drintxq 1, 8, 10, 3            # encoding: [0xc6,0x56,0x01,0xfd]
+# CHECK-BE: drintxq 1, 8, 10, 3            # encoding: [0xfd,0x01,0x56,0xc6]
+            drintxq 1, 8, 10, 3
+# CHECK-LE: drintxq. 0, 8, 10, 3           # encoding: [0xc7,0x56,0x00,0xfd]
+# CHECK-BE: drintxq. 0, 8, 10, 3           # encoding: [0xfd,0x00,0x56,0xc7]
+            drintxq. 0, 8, 10, 3
+# CHECK-LE: drintn 1, 10, 6, 2             # encoding: [0xc6,0x35,0x41,0xed]
+# CHECK-BE: drintn 1, 10, 6, 2             # encoding: [0xed,0x41,0x35,0xc6]
+            drintn 1, 10, 6, 2
+# CHECK-LE: drintn. 0, 10, 6, 2            # encoding: [0xc7,0x35,0x40,0xed]
+# CHECK-BE: drintn. 0, 10, 6, 2            # encoding: [0xed,0x40,0x35,0xc7]
+            drintn. 0, 10, 6, 2
+# CHECK-LE: drintnq 0, 10, 6, 2            # encoding: [0xc6,0x35,0x40,0xfd]
+# CHECK-BE: drintnq 0, 10, 6, 2            # encoding: [0xfd,0x40,0x35,0xc6]
+            drintnq 0, 10, 6, 2
+# CHECK-LE: drintnq. 1, 10, 6, 2           # encoding: [0xc7,0x35,0x41,0xfd]
+# CHECK-BE: drintnq. 1, 10, 6, 2           # encoding: [0xfd,0x41,0x35,0xc7]
+            drintnq. 1, 10, 6, 2