[MC] Use regunits instead of MCRegUnitIterator. NFC.

[foad]

llvm/lib/MC/MCRegisterInfo.cpp

138

This still mentions MCRegUnitIterator but it gets away from the non-standard isValid style of iteration, towards the standard iterator_range style.

[barannikov88]

llvm/lib/MC/MCRegisterInfo.cpp

138

This still mentions MCRegUnitIterator

I think this is fine.

(suggestion) The default constructor of MCRegUnitIterator creates an end iterator, it can be used to simplify code a bit:

...
MCRegUnitIterator IA = regunits(RegA).begin();
MCRegUnitIterator IB = regunits(RegB).begin();
MCRegUnitIterator E;
...
} while (*IA < *IB ? ++IA != E : ++IB != E);

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

1023

There is range_size just for this.

[foad]

llvm/lib/MC/MCRegisterInfo.cpp

138

That is certainly simpler, but less standard. I'm not sure which I prefer.

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

1023

Thanks! But why don't we have iterator_range::size like Boost does?

[foad]

Use range_size.

[barannikov88]

llvm/lib/MC/MCRegisterInfo.cpp

138

std::istreambuf_iterator behaves similarly.

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

1023

Probably no one took care of implementing it. There is only a handful uses of this function.

llvm/lib/CodeGen/MachineCopyPropagation.cpp

public:
 
   MachineInstr *findCopyDefViaUnit(MCRegister RegUnit,
                                    const TargetRegisterInfo &TRI) {
     auto CI = Copies.find(RegUnit);
     if (CI == Copies.end())
       return nullptr;
     if (CI->second.DefRegs.size() != 1)
       return nullptr;
-    MCRegUnitIterator RUI(CI->second.DefRegs[0], &TRI);
-    return findCopyForUnit(*RUI, TRI, true);
+    MCRegUnit RU = *TRI.regunits(CI->second.DefRegs[0]).begin();
+    return findCopyForUnit(RU, TRI, true);
   }
 
   MachineInstr *findAvailBackwardCopy(MachineInstr &I, MCRegister Reg,
                                       const TargetRegisterInfo &TRI,
                                       const TargetInstrInfo &TII,
                                       bool UseCopyInstr) {
-    MCRegUnitIterator RUI(Reg, &TRI);
-    MachineInstr *AvailCopy = findCopyDefViaUnit(*RUI, TRI);
+    MCRegUnit RU = *TRI.regunits(Reg).begin();
+    MachineInstr *AvailCopy = findCopyDefViaUnit(RU, TRI);
 
     if (!AvailCopy)
       return nullptr;
 
     std::optional<DestSourcePair> CopyOperands =
         isCopyInstr(*AvailCopy, TII, UseCopyInstr);
     Register AvailSrc = CopyOperands->Source->getReg();
     Register AvailDef = CopyOperands->Destination->getReg();
MachineInstr *findAvailBackwardCopy(MachineInstr &I, MCRegister Reg,
     return AvailCopy;
   }
 
   MachineInstr *findAvailCopy(MachineInstr &DestCopy, MCRegister Reg,
                               const TargetRegisterInfo &TRI,
                               const TargetInstrInfo &TII, bool UseCopyInstr) {
     // We check the first RegUnit here, since we'll only be interested in the
     // copy if it copies the entire register anyway.
-    MCRegUnitIterator RUI(Reg, &TRI);
+    MCRegUnit RU = *TRI.regunits(Reg).begin();
     MachineInstr *AvailCopy =
-        findCopyForUnit(*RUI, TRI, /*MustBeAvailable=*/true);
+        findCopyForUnit(RU, TRI, /*MustBeAvailable=*/true);
 
     if (!AvailCopy)
       return nullptr;
 
     std::optional<DestSourcePair> CopyOperands =
         isCopyInstr(*AvailCopy, TII, UseCopyInstr);
     Register AvailSrc = CopyOperands->Source->getReg();
     Register AvailDef = CopyOperands->Destination->getReg();
public:
   }
 
   // Find last COPY that defines Reg before Current MachineInstr.
   MachineInstr *findLastSeenDefInCopy(const MachineInstr &Current,
                                       MCRegister Reg,
                                       const TargetRegisterInfo &TRI,
                                       const TargetInstrInfo &TII,
                                       bool UseCopyInstr) {
-    MCRegUnitIterator RUI(Reg, &TRI);
-    auto CI = Copies.find(*RUI);
+    MCRegUnit RU = *TRI.regunits(Reg).begin();
+    auto CI = Copies.find(RU);
     if (CI == Copies.end() || !CI->second.Avail)
       return nullptr;
 
     MachineInstr *DefCopy = CI->second.MI;
     std::optional<DestSourcePair> CopyOperands =
         isCopyInstr(*DefCopy, TII, UseCopyInstr);
     Register Def = CopyOperands->Destination->getReg();
     if (!TRI.isSubRegisterEq(Def, Reg))
for (const MachineInstr &MI :
           }
 
     return DefCopy;
   }
 
   // Find last COPY that uses Reg.
   MachineInstr *findLastSeenUseInCopy(MCRegister Reg,
                                       const TargetRegisterInfo &TRI) {
-    MCRegUnitIterator RUI(Reg, &TRI);
-    auto CI = Copies.find(*RUI);
+    MCRegUnit RU = *TRI.regunits(Reg).begin();
+    auto CI = Copies.find(RU);
     if (CI == Copies.end())
       return nullptr;
     return CI->second.LastSeenUseInCopy;
   }
 
   void clear() {
     Copies.clear();
   }

llvm/lib/CodeGen/RDFRegisters.cpp

if (I == 0)          // Reg 0 should be ignored
       C &= maskLeadingOnes<unsigned>(31);
     if (I + 1 == E && NumRegs % 32 != 0) // Last word may be partial
       C &= maskTrailingOnes<unsigned>(NumRegs % 32);
     if (C == 0)
       continue;
     while (C != 0) {
       unsigned T = llvm::countr_zero(C);
       unsigned CR = 32 * I + T; // Clobbered reg
-      for (MCRegUnitIterator U(CR, &TRI); U.isValid(); ++U)
-        Units.insert(*U);
+      for (MCRegUnit U : TRI.regunits(CR))
+        Units.insert(U);
       C &= ~(1u << T);
     }
   }
   return Units;
 }
 
 RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const {
   if (RR.Reg == R)

llvm/lib/CodeGen/RegAllocFast.cpp

void RegAllocFast::reloadAtBegin(MachineBasicBlock &MBB) {
   // of spilling here is deterministic, if arbitrary.
   MachineBasicBlock::iterator InsertBefore
     = getMBBBeginInsertionPoint(MBB, PrologLiveIns);
   for (const LiveReg &LR : LiveVirtRegs) {
     MCPhysReg PhysReg = LR.PhysReg;
     if (PhysReg == 0)
       continue;
 
-    MCRegister FirstUnit = *MCRegUnitIterator(PhysReg, TRI);
+    MCRegister FirstUnit = *TRI->regunits(PhysReg).begin();
     if (RegUnitStates[FirstUnit] == regLiveIn)
       continue;
 
     assert((&MBB != &MBB.getParent()->front() || IgnoreMissingDefs) &&
            "no reload in start block. Missing vreg def?");
 
     if (PrologLiveIns.count(PhysReg)) {
       // FIXME: Theoretically this should use an insert point skipping labels
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
     }
   }
   return displacedAny;
 }
 
 void RegAllocFast::freePhysReg(MCPhysReg PhysReg) {
   LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':');
 
-  MCRegister FirstUnit = *MCRegUnitIterator(PhysReg, TRI);
+  MCRegister FirstUnit = *TRI->regunits(PhysReg).begin();
   switch (unsigned VirtReg = RegUnitStates[FirstUnit]) {
   case regFree:
     LLVM_DEBUG(dbgs() << '\n');
     return;
   case regPreAssigned:
     LLVM_DEBUG(dbgs() << '\n');
     setPhysRegState(PhysReg, regFree);
     return;

llvm/lib/MC/MCRegisterInfo.cpp

if (I == L2CVRegs.end())
     report_fatal_error("unknown codeview register " + (RegNum < getNumRegs()
                                                            ? getName(RegNum)
                                                            : Twine(RegNum)));
   return I->second;
 }
 
 bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const {
   // Regunits are numerically ordered. Find a common unit.
-  MCRegUnitIterator RUA(RegA, this);
-  MCRegUnitIterator RUB(RegB, this);
+  auto RangeA = regunits(RegA);
+  MCRegUnitIterator IA = RangeA.begin(), EA = RangeA.end();
+  auto RangeB = regunits(RegB);
+  MCRegUnitIterator IB = RangeB.begin(), EB = RangeB.end();
   do {
-    if (*RUA == *RUB)
+    if (*IA == *IB)
       return true;
-  } while (*RUA < *RUB ? (++RUA).isValid() : (++RUB).isValid());
+  } while (*IA < *IB ? ++IA != EA : ++IB != EB);
   return false;
 }

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
   assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&
          getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) &&
          (getSubRegIndexLaneMask(AMDGPU::lo16) |
           getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() ==
            getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() &&
          "getNumCoveredRegs() will not work with generated subreg masks!");
 
   RegPressureIgnoredUnits.resize(getNumRegUnits());
-  RegPressureIgnoredUnits.set(
-      *MCRegUnitIterator(MCRegister::from(AMDGPU::M0), this));
+  RegPressureIgnoredUnits.set(*regunits(MCRegister::from(AMDGPU::M0)).begin());
   for (auto Reg : AMDGPU::VGPR_HI16RegClass)
-    RegPressureIgnoredUnits.set(*MCRegUnitIterator(Reg, this));
+    RegPressureIgnoredUnits.set(*regunits(Reg).begin());
 
   // HACK: Until this is fully tablegen'd.
   static llvm::once_flag InitializeRegSplitPartsFlag;
 
   static auto InitializeRegSplitPartsOnce = [this]() {
     for (unsigned Idx = 1, E = getNumSubRegIndices() - 1; Idx < E; ++Idx) {
       unsigned Size = getSubRegIdxSize(Idx);
       if (Size & 31)

llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp

 // instructions we want to add necessarily clobber SCC.
 MachineBasicBlock::iterator SIWholeQuadMode::prepareInsertion(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator First,
     MachineBasicBlock::iterator Last, bool PreferLast, bool SaveSCC) {
   if (!SaveSCC)
     return PreferLast ? Last : First;
 
   LiveRange &LR =
-      LIS->getRegUnit(*MCRegUnitIterator(MCRegister::from(AMDGPU::SCC), TRI));
+      LIS->getRegUnit(*TRI->regunits(MCRegister::from(AMDGPU::SCC)).begin());
   auto MBBE = MBB.end();
   SlotIndex FirstIdx = First != MBBE ? LIS->getInstructionIndex(*First)
                                      : LIS->getMBBEndIdx(&MBB);
   SlotIndex LastIdx =
       Last != MBBE ? LIS->getInstructionIndex(*Last) : LIS->getMBBEndIdx(&MBB);
   SlotIndex Idx = PreferLast ? LastIdx : FirstIdx;
   const LiveRange::Segment *S;
 

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
     LiveIntervals *LIS, VirtRegMap *VRM) const {
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   unsigned Size = MFI.getObjectSize(FrameIndex);
   unsigned Opcode = MI.getOpcode();
 
   // Check CC liveness if new instruction introduces a dead def of CC.
-  MCRegUnitIterator CCUnit(MCRegister::from(SystemZ::CC), TRI);
   SlotIndex MISlot = SlotIndex();
   LiveRange *CCLiveRange = nullptr;
   bool CCLiveAtMI = true;
   if (LIS) {
     MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
-    CCLiveRange = &LIS->getRegUnit(*CCUnit);
+    auto CCUnits = TRI->regunits(MCRegister::from(SystemZ::CC));
+    assert(range_size(CCUnits) == 1 && "CC only has one reg unit.");
+    CCLiveRange = &LIS->getRegUnit(*CCUnits.begin());
     CCLiveAtMI = CCLiveRange->liveAt(MISlot);
   }
-  ++CCUnit;
-  assert(!CCUnit.isValid() && "CC only has one reg unit.");
 
   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
     if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
         isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
       // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
       MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
                                       MI.getDebugLoc(), get(SystemZ::AGSI))
         .addFrameIndex(FrameIndex)