[SelectionDAG][AArch64] Legalize FMAXIMUM/FMINIMUM

[anna]

Summary

The missing legalization in SelectionDAG was identified when adding the
intrinsic support for vector reduction for maximum/minimum (D152370).

Fixes PR: https://github.com/llvm/llvm-project/issues/63267

[nikic]

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

4177

These libcalls follow the semantics of FMINNUM/FMAXNUM, we can't reuse them for FMINIMUM/FMAXIMUM.

I don't think there are any libcalls for this, so I think we need to always expand as a fallback, not libcall legalize. Of course, that runs into the problem that we don't even have a default expansion for these nodes...

4958

This part should be fine.

[anna]

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

4177

Yes, I thought this RTLIB call might be a problem... and couldn't find any for maximum/minimum.
I'll document this as an existing bug within the legalization under the original PR and state what you've added here.
This also means the vector reduce legalization for f128 and friends described here would not have legalization. I would like to avoid blocking the introduction of the vector reduction intrinsic on that though.

[nikic]

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

4177

That's fine. For the purpose of introducing the reduction intrinsics, you can just leave the test cases that currently don't work commented out. These are really independent problems.

[anna]

addressed review comment. Left in a comment to explain why we cannot legalize using libcalls for F128 and friends.

[nikic]

LGTM

[anna]

thanks for quick review @nikic!

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

case ISD::TRAP: {
     break;
   }
   case ISD::FMINNUM:
   case ISD::STRICT_FMINNUM:
     ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
                     RTLIB::FMIN_F80, RTLIB::FMIN_F128,
                     RTLIB::FMIN_PPCF128, Results);
     break;
+  // FIXME: We do not have libcalls for FMAXIMUM and FMINIMUM. So, we cannot use
+  // libcall legalization for these nodes, but there is no default expasion for
+  // these nodes either (see PR63267 for example).
   case ISD::FMAXNUM:
   case ISD::STRICT_FMAXNUM:
     ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
                     RTLIB::FMAX_F80, RTLIB::FMAX_F128,
                     RTLIB::FMAX_PPCF128, Results);
     break;
   case ISD::FSQRT:
   case ISD::STRICT_FSQRT:
     ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
                     RTLIB::SQRT_F80, RTLIB::SQRT_F128,
                     RTLIB::SQRT_PPCF128, Results);
     break;
   case ISD::FCBRT:
void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
   }
   case ISD::FADD:
   case ISD::FSUB:
   case ISD::FMUL:
   case ISD::FDIV:
   case ISD::FREM:
   case ISD::FMINNUM:
   case ISD::FMAXNUM:
+  case ISD::FMINIMUM:
+  case ISD::FMAXIMUM:
   case ISD::FPOW:
     Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
     Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
     Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
                        Node->getFlags());
     Results.push_back(
         DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp3,
                     DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)));

llvm/test/CodeGen/AArch64/fmaximum-legalization.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
+
+declare <4 x half> @llvm.maximum.v4f16(<4 x half>, <4 x half>)
+
+declare <2 x fp128> @llvm.maximum.v2f128(<2 x fp128>, <2 x fp128>)
+
+; Fixes PR63267
+define <4 x half> @fmaximum_v4f16(<4 x half> %x, <4 x half> %y) {
+; CHECK-LABEL: fmaximum_v4f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    mov h2, v1.h[1]
+; CHECK-NEXT:    mov h3, v0.h[1]
+; CHECK-NEXT:    fcvt s4, h1
+; CHECK-NEXT:    fcvt s5, h0
+; CHECK-NEXT:    mov h6, v1.h[2]
+; CHECK-NEXT:    mov h7, v0.h[2]
+; CHECK-NEXT:    mov h1, v1.h[3]
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvt s3, h3
+; CHECK-NEXT:    fmax s4, s5, s4
+; CHECK-NEXT:    fcvt s5, h7
+; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    fmax s2, s3, s2
+; CHECK-NEXT:    fcvt s3, h6
+; CHECK-NEXT:    mov h6, v0.h[3]
+; CHECK-NEXT:    fcvt h0, s4
+; CHECK-NEXT:    fcvt h2, s2
+; CHECK-NEXT:    fmax s3, s5, s3
+; CHECK-NEXT:    fcvt s4, h6
+; CHECK-NEXT:    mov v0.h[1], v2.h[0]
+; CHECK-NEXT:    fcvt h2, s3
+; CHECK-NEXT:    fmax s1, s4, s1
+; CHECK-NEXT:    mov v0.h[2], v2.h[0]
+; CHECK-NEXT:    fcvt h1, s1
+; CHECK-NEXT:    mov v0.h[3], v1.h[0]
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    ret
+  %r = call <4 x half> @llvm.maximum.v4f16(<4 x half> %x, <4 x half> %y)
+  ret <4 x half> %r
+}