[AMDGPU] Remove integer division in VOPD checks

[rampitec]

Summary

There is no way any compiler can simplify this division, while
the check is done rather often.

[rampitec]

NB: To have a chance to simplify division here a compiler must fully unroll the loop. With the loop growing it becomes impossible.

[rampitec]

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

564

On a separate note, I do not understand 2 banks for the src2. This should have been checked yet while checking vdst parity. If there is a real src2 it must follow a regular rules for the source banks. At the moment this is simply misleading, the loop will actually exit at the first iteration if the parity is the same. It is a time bomb, but this is a separate patch.

[rampitec]

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

564

In fact this is already broken: D152614. Our own tests verify this is broken and must be broken. Insane.

[rampitec]

I am growing to think that update_*_test_checks scripts are a simulation of testing. Nobody seems to really think what tests are doing now.

[rampitec]

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

564

Please ignore the src2 part, just found an additional restriction.

[Joe_Nash]

LGTM

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

enum Component : unsigned {
   SRC1,
   SRC2,
 
   DST_NUM = 1,
   MAX_SRC_NUM = 3,
   MAX_OPR_NUM = DST_NUM + MAX_SRC_NUM
 };
 
-// Number of VGPR banks per VOPD component operand.
-constexpr unsigned BANKS_NUM[] = {2, 4, 4, 2};
+// LSB mask for VGPR banks per VOPD component operand.
+// 4 banks result in a mask 3, setting 2 lower bits.
+constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};
 
 enum ComponentIndex : unsigned { X = 0, Y = 1 };
 constexpr unsigned COMPONENTS[] = {ComponentIndex::X, ComponentIndex::Y};
 constexpr unsigned COMPONENTS_NUM = 2;
 
 // Properties of VOPD components.
 class ComponentProps {
 private:

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 std::optional<unsigned> InstInfo::getInvalidCompOperandIndex(
     std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
 
   auto OpXRegs = getRegIndices(ComponentIndex::X, GetRegIdx);
   auto OpYRegs = getRegIndices(ComponentIndex::Y, GetRegIdx);
 
   unsigned CompOprIdx;
   for (CompOprIdx = 0; CompOprIdx < Component::MAX_OPR_NUM; ++CompOprIdx) {
-    unsigned BanksNum = BANKS_NUM[CompOprIdx];
+    unsigned BanksMasks = VOPD_VGPR_BANK_MASKS[CompOprIdx];
     if (OpXRegs[CompOprIdx] && OpYRegs[CompOprIdx] &&
-        (OpXRegs[CompOprIdx] % BanksNum == OpYRegs[CompOprIdx] % BanksNum))
+        ((OpXRegs[CompOprIdx] & BanksMasks) ==
+         (OpYRegs[CompOprIdx] & BanksMasks)))
       return CompOprIdx;
   }
 
   return {};
 }
 
 // Return an array of VGPR registers [DST,SRC0,SRC1,SRC2] used
 // by the specified component. If an operand is unused