AMDGPU: Do not not force alwaysinline with calls and module LDS enabled

[arsenm]

Summary

Function calls are now well supported. We used to also need this for
dealing with LDS uses in functions, but now that should also work.
This also removes the stress calls option, which would require moving
the flag to the TargetMachine and I no longer think it's useful.

We should probably drop the amdgpu-function-calls too but I think
hipcc is still using it.

This trims the pass list nicely (I'm surprised this saved a dominator
and alias analysis run).

[scchan]

We should probably drop the amdgpu-function-calls too but I think
hipcc is still using it.

The amdgpu-function-calls switch is needed to disable function calls as a prereq to enable alwaysinline, which I don't understand why.

[arsenm]

In D152414#4406127, @scchan wrote:

We should probably drop the amdgpu-function-calls too but I think
hipcc is still using it.

The amdgpu-function-calls switch is needed to disable function calls as a prereq to enable alwaysinline, which I don't understand why.

I'm failing to parse this sentence

[foad]

Typo in description "not not"

[scchan]

In D152414#4406186, @arsenm wrote:

In D152414#4406127, @scchan wrote:

We should probably drop the amdgpu-function-calls too but I think
hipcc is still using it.

The amdgpu-function-calls switch is needed to disable function calls as a prereq to enable alwaysinline, which I don't understand why.

I'm failing to parse this sentence

hipcc uses this switch because the enablement of alwaysinline requires that the function call support be turned off why do we have to turn off function call?

[arsenm]

In D152414#4406423, @scchan wrote:

hipcc uses this switch because the enablement of alwaysinline requires that the function call support be turned off why do we have to turn off function call?

I'm still confused about what you're asking. Function calls are supposed to always be on, they can't actually be completely avoided. amdgpu-function-calls was for bringup of call support and should be retired. This maintains the flag for the force off usage hipcc was relying on, for now.

[arsenm]

ping

[jmmartinez]

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

977–983

Currently the inliner gives a boost to the inline-threshold for functions that take alloca instructions as arguments (ArgAllocaCost in AMDGPUTargetTransformInfo.cpp).

Should that inline bonus be removed too?

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

977–983

Those would be unrelated. That's just regular inline heuristics, not related to hacking out a call to avoid codegen limitations

[arsenm]

Rebase

[arsenm]

ping

[JonChesterfield]

LG here. Can we get rid of EnableFunctionCalls?

[arsenm]

In D152414#4492691, @JonChesterfield wrote:

LG here. Can we get rid of EnableFunctionCalls?

If we can get rid of hipcc which is still using it

[scchan]

In D152414#4493174, @arsenm wrote:

In D152414#4492691, @JonChesterfield wrote:

LG here. Can we get rid of EnableFunctionCalls?

If we can get rid of hipcc which is still using it

hipcc only needs a way to force EarlyInlineAll but that pass is predicated by !EnableFunctionCalls. If we don't think it's warranted then we can deprecate EnableFunctionCalls by first removing it in hipcc.

llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp

 #include "llvm/IR/Module.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 namespace {
 
-static cl::opt<bool> StressCalls(
-  "amdgpu-stress-function-calls",
-  cl::Hidden,
-  cl::desc("Force all functions to be noinline"),
-  cl::init(false));
-
 class AMDGPUAlwaysInline : public ModulePass {
   bool GlobalOpt;
 
 public:
   static char ID;
 
   AMDGPUAlwaysInline(bool GlobalOpt = false) :
     ModulePass(ID), GlobalOpt(GlobalOpt) { }
for (GlobalVariable &GV : M.globals()) {
     // TODO: Region address
     unsigned AS = GV.getAddressSpace();
     if ((AS == AMDGPUAS::REGION_ADDRESS) ||
         (AS == AMDGPUAS::LOCAL_ADDRESS &&
          (!AMDGPUTargetMachine::EnableLowerModuleLDS)))
       recursivelyVisitUsers(GV, FuncsToAlwaysInline);
   }
 
-  if (!AMDGPUTargetMachine::EnableFunctionCalls || StressCalls) {
-    auto IncompatAttr
-      = StressCalls ? Attribute::AlwaysInline : Attribute::NoInline;
+  if (!AMDGPUTargetMachine::EnableFunctionCalls) {
+    auto IncompatAttr = Attribute::NoInline;
 
     for (Function &F : M) {
       if (!F.isDeclaration() && !F.use_empty() &&
           !F.hasFnAttribute(IncompatAttr)) {
-        if (StressCalls) {
-          if (!FuncsToAlwaysInline.count(&F))
-            FuncsToNoInline.insert(&F);
-        } else
-          FuncsToAlwaysInline.insert(&F);
       }
     }
   }
 
   for (Function *F : FuncsToAlwaysInline)
     F->addFnAttr(Attribute::AlwaysInline);
 
   for (Function *F : FuncsToNoInline)

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

void AMDGPUPassConfig::addIRPasses() {
   disablePass(&StackMapLivenessID);
   disablePass(&FuncletLayoutID);
   disablePass(&PatchableFunctionID);
 
   addPass(createAMDGPUPrintfRuntimeBinding());
   if (LowerCtorDtor)
     addPass(createAMDGPUCtorDtorLoweringLegacyPass());
 
+  if (!AMDGPUTargetMachine::EnableFunctionCalls ||
+      !AMDGPUTargetMachine::EnableLowerModuleLDS) {
     // Function calls are not supported, so make sure we inline everything.
     addPass(createAMDGPUAlwaysInlinePass());
     addPass(createAlwaysInlinerLegacyPass());
+  }
 
   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
   if (TM.getTargetTriple().getArch() == Triple::r600)
     addPass(createR600OpenCLImageTypeLoweringPass());
 
   // Replace OpenCL enqueued block function pointers with global variables.
   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
 
   // Runs before PromoteAlloca so the latter can account for function uses

llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-function-calls -amdgpu-stress-function-calls -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-stress-function-calls -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-function-calls=false -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s
 
 @lds0 = addrspace(3) global i32 undef, align 4
 
 ; GCN-NOT: load_lds_simple
-
 define internal i32 @load_lds_simple() {
   %load = load i32, ptr addrspace(3) @lds0, align 4
   ret i32 %load
 }
 
 ; GCN-LABEL: {{^}}kernel:
 ; GCN: v_mov_b32_e32 [[ADDR:v[0-9]+]], 0
 ; GCN: ds_read_b32 v{{[0-9]+}}, [[ADDR]]
 define amdgpu_kernel void @kernel(ptr addrspace(1) %out) {
   %call = call i32 @load_lds_simple()
   store i32 %call, ptr addrspace(1) %out
   ret void
 }

llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll

 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-always-inline -amdgpu-enable-lower-module-lds=false %s | FileCheck --check-prefix=ALL %s
 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-always-inline -amdgpu-enable-lower-module-lds=false %s | FileCheck --check-prefix=ALL %s
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-stress-function-calls -passes=amdgpu-always-inline -amdgpu-enable-lower-module-lds=false %s | FileCheck --check-prefix=ALL %s
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-stress-function-calls -passes=amdgpu-always-inline -amdgpu-enable-lower-module-lds=false %s | FileCheck --check-prefix=ALL %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-function-calls=0 -passes=amdgpu-always-inline -amdgpu-enable-lower-module-lds=false %s | FileCheck --check-prefix=ALL %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-function-calls=0 -passes=amdgpu-always-inline -amdgpu-enable-lower-module-lds=false %s | FileCheck --check-prefix=ALL %s
 
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
 
 @lds0 = addrspace(3) global i32 undef, align 4
 @lds1 = addrspace(3) global [512 x i32] undef, align 4
 @nested.lds.address = addrspace(1) global ptr addrspace(3) @lds0, align 4
 @gds0 = addrspace(2) global i32 undef, align 4
 

llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

 
 ; REQUIRES: asserts
 
 ; GCN-O0:Target Library Information
 ; GCN-O0-NEXT:Target Pass Configuration
 ; GCN-O0-NEXT:Machine Module Information
 ; GCN-O0-NEXT:Target Transform Information
 ; GCN-O0-NEXT:Assumption Cache Tracker
-; GCN-O0-NEXT:Profile summary info
 ; GCN-O0-NEXT:Argument Register Usage Information Storage
 ; GCN-O0-NEXT:Create Garbage Collector Module Metadata
+; GCN-O0-NEXT:Profile summary info
 ; GCN-O0-NEXT:Register Usage Information Storage
 ; GCN-O0-NEXT:Machine Branch Probability Analysis
 ; GCN-O0-NEXT:  ModulePass Manager
 ; GCN-O0-NEXT:    Pre-ISel Intrinsic Lowering
 ; GCN-O0-NEXT:    FunctionPass Manager
 ; GCN-O0-NEXT:      Expand large div/rem
 ; GCN-O0-NEXT:      Expand large fp convert
 ; GCN-O0-NEXT:    AMDGPU Printf lowering
 ; GCN-O0-NEXT:      FunctionPass Manager
 ; GCN-O0-NEXT:        Dominator Tree Construction
 ; GCN-O0-NEXT:    Lower ctors and dtors for AMDGPU
-; GCN-O0-NEXT:    AMDGPU Inline All Functions
-; GCN-O0-NEXT:    Inliner for always_inline functions
-; GCN-O0-NEXT:      FunctionPass Manager
-; GCN-O0-NEXT:        Dominator Tree Construction
-; GCN-O0-NEXT:        Basic Alias Analysis (stateless AA impl)
-; GCN-O0-NEXT:        Function Alias Analysis Results
 ; GCN-O0-NEXT:    Lower OpenCL enqueued blocks
 ; GCN-O0-NEXT:    Lower uses of LDS variables from non-kernel functions
 ; GCN-O0-NEXT:    FunctionPass Manager
 ; GCN-O0-NEXT:      Expand Atomic instructions
 ; GCN-O0-NEXT:      Lower constant intrinsics
 ; GCN-O0-NEXT:      Remove unreachable blocks from the CFG
 ; GCN-O0-NEXT:      Expand vector predication intrinsics
 ; GCN-O0-NEXT:      Scalarize Masked Memory Intrinsics

 ; GCN-O0-NEXT:  FunctionPass Manager
 ; GCN-O0-NEXT:    Dominator Tree Construction
 
 ; GCN-O1:Target Library Information
 ; GCN-O1-NEXT:Target Pass Configuration
 ; GCN-O1-NEXT:Machine Module Information
 ; GCN-O1-NEXT:Target Transform Information
 ; GCN-O1-NEXT:Assumption Cache Tracker
-; GCN-O1-NEXT:Profile summary info
 ; GCN-O1-NEXT:AMDGPU Address space based Alias Analysis
 ; GCN-O1-NEXT:External Alias Analysis
 ; GCN-O1-NEXT:Type-Based Alias Analysis
 ; GCN-O1-NEXT:Scoped NoAlias Alias Analysis
+; GCN-O1-NEXT:Profile summary info
 ; GCN-O1-NEXT:Argument Register Usage Information Storage
 ; GCN-O1-NEXT:Create Garbage Collector Module Metadata
 ; GCN-O1-NEXT:Machine Branch Probability Analysis
 ; GCN-O1-NEXT:Register Usage Information Storage
 ; GCN-O1-NEXT:Default Regalloc Eviction Advisor
 ; GCN-O1-NEXT:Default Regalloc Priority Advisor
 ; GCN-O1-NEXT:  ModulePass Manager
 ; GCN-O1-NEXT:    Pre-ISel Intrinsic Lowering
 ; GCN-O1-NEXT:    FunctionPass Manager
 ; GCN-O1-NEXT:      Expand large div/rem
 ; GCN-O1-NEXT:      Expand large fp convert
 ; GCN-O1-NEXT:    AMDGPU Printf lowering
 ; GCN-O1-NEXT:      FunctionPass Manager
 ; GCN-O1-NEXT:        Dominator Tree Construction
 ; GCN-O1-NEXT:    Lower ctors and dtors for AMDGPU
-; GCN-O1-NEXT:    AMDGPU Inline All Functions
-; GCN-O1-NEXT:    Inliner for always_inline functions
-; GCN-O1-NEXT:      FunctionPass Manager
-; GCN-O1-NEXT:        Dominator Tree Construction
-; GCN-O1-NEXT:        Basic Alias Analysis (stateless AA impl)
-; GCN-O1-NEXT:        Function Alias Analysis Results
 ; GCN-O1-NEXT:    Lower OpenCL enqueued blocks
 ; GCN-O1-NEXT:    Lower uses of LDS variables from non-kernel functions
 ; GCN-O1-NEXT:    AMDGPU Attributor
 ; GCN-O1-NEXT:      FunctionPass Manager
 ; GCN-O1-NEXT:        Cycle Info Analysis
 ; GCN-O1-NEXT:    FunctionPass Manager
 ; GCN-O1-NEXT:      Infer address spaces
 ; GCN-O1-NEXT:      Expand Atomic instructions

 ; GCN-O1-NEXT:  FunctionPass Manager
 ; GCN-O1-NEXT:    Dominator Tree Construction
 
 ; GCN-O1-OPTS:Target Library Information
 ; GCN-O1-OPTS-NEXT:Target Pass Configuration
 ; GCN-O1-OPTS-NEXT:Machine Module Information
 ; GCN-O1-OPTS-NEXT:Target Transform Information
 ; GCN-O1-OPTS-NEXT:Assumption Cache Tracker
-; GCN-O1-OPTS-NEXT:Profile summary info
 ; GCN-O1-OPTS-NEXT:AMDGPU Address space based Alias Analysis
 ; GCN-O1-OPTS-NEXT:External Alias Analysis
 ; GCN-O1-OPTS-NEXT:Type-Based Alias Analysis
 ; GCN-O1-OPTS-NEXT:Scoped NoAlias Alias Analysis
+; GCN-O1-OPTS-NEXT:Profile summary info
 ; GCN-O1-OPTS-NEXT:Argument Register Usage Information Storage
 ; GCN-O1-OPTS-NEXT:Create Garbage Collector Module Metadata
 ; GCN-O1-OPTS-NEXT:Machine Branch Probability Analysis
 ; GCN-O1-OPTS-NEXT:Register Usage Information Storage
 ; GCN-O1-OPTS-NEXT:Default Regalloc Eviction Advisor
 ; GCN-O1-OPTS-NEXT:Default Regalloc Priority Advisor
 ; GCN-O1-OPTS-NEXT:  ModulePass Manager
 ; GCN-O1-OPTS-NEXT:    Pre-ISel Intrinsic Lowering
 ; GCN-O1-OPTS-NEXT:    FunctionPass Manager
 ; GCN-O1-OPTS-NEXT:      Expand large div/rem
 ; GCN-O1-OPTS-NEXT:      Expand large fp convert
 ; GCN-O1-OPTS-NEXT:    AMDGPU Printf lowering
 ; GCN-O1-OPTS-NEXT:      FunctionPass Manager
 ; GCN-O1-OPTS-NEXT:        Dominator Tree Construction
 ; GCN-O1-OPTS-NEXT:    Lower ctors and dtors for AMDGPU
-; GCN-O1-OPTS-NEXT:    AMDGPU Inline All Functions
-; GCN-O1-OPTS-NEXT:    Inliner for always_inline functions
-; GCN-O1-OPTS-NEXT:      FunctionPass Manager
-; GCN-O1-OPTS-NEXT:        Dominator Tree Construction
-; GCN-O1-OPTS-NEXT:        Basic Alias Analysis (stateless AA impl)
-; GCN-O1-OPTS-NEXT:        Function Alias Analysis Results
 ; GCN-O1-OPTS-NEXT:    Lower OpenCL enqueued blocks
 ; GCN-O1-OPTS-NEXT:    Lower uses of LDS variables from non-kernel functions
 ; GCN-O1-OPTS-NEXT:    AMDGPU Attributor
 ; GCN-O1-OPTS-NEXT:      FunctionPass Manager
 ; GCN-O1-OPTS-NEXT:        Cycle Info Analysis
 ; GCN-O1-OPTS-NEXT:    FunctionPass Manager
 ; GCN-O1-OPTS-NEXT:      Infer address spaces
 ; GCN-O1-OPTS-NEXT:      Expand Atomic instructions

 ; GCN-O1-OPTS-NEXT:  FunctionPass Manager
 ; GCN-O1-OPTS-NEXT:    Dominator Tree Construction
 
 ; GCN-O2:Target Library Information
 ; GCN-O2-NEXT:Target Pass Configuration
 ; GCN-O2-NEXT:Machine Module Information
 ; GCN-O2-NEXT:Target Transform Information
 ; GCN-O2-NEXT:Assumption Cache Tracker
-; GCN-O2-NEXT:Profile summary info
 ; GCN-O2-NEXT:AMDGPU Address space based Alias Analysis
 ; GCN-O2-NEXT:External Alias Analysis
 ; GCN-O2-NEXT:Type-Based Alias Analysis
 ; GCN-O2-NEXT:Scoped NoAlias Alias Analysis
+; GCN-O2-NEXT:Profile summary info
 ; GCN-O2-NEXT:Argument Register Usage Information Storage
 ; GCN-O2-NEXT:Create Garbage Collector Module Metadata
 ; GCN-O2-NEXT:Machine Branch Probability Analysis
 ; GCN-O2-NEXT:Register Usage Information Storage
 ; GCN-O2-NEXT:Default Regalloc Eviction Advisor
 ; GCN-O2-NEXT:Default Regalloc Priority Advisor
 ; GCN-O2-NEXT:  ModulePass Manager
 ; GCN-O2-NEXT:    Pre-ISel Intrinsic Lowering
 ; GCN-O2-NEXT:    FunctionPass Manager
 ; GCN-O2-NEXT:      Expand large div/rem
 ; GCN-O2-NEXT:      Expand large fp convert
 ; GCN-O2-NEXT:    AMDGPU Printf lowering
 ; GCN-O2-NEXT:      FunctionPass Manager
 ; GCN-O2-NEXT:        Dominator Tree Construction
 ; GCN-O2-NEXT:    Lower ctors and dtors for AMDGPU
-; GCN-O2-NEXT:    AMDGPU Inline All Functions
-; GCN-O2-NEXT:    Inliner for always_inline functions
-; GCN-O2-NEXT:      FunctionPass Manager
-; GCN-O2-NEXT:        Dominator Tree Construction
-; GCN-O2-NEXT:        Basic Alias Analysis (stateless AA impl)
-; GCN-O2-NEXT:        Function Alias Analysis Results
 ; GCN-O2-NEXT:    Lower OpenCL enqueued blocks
 ; GCN-O2-NEXT:    Lower uses of LDS variables from non-kernel functions
 ; GCN-O2-NEXT:    AMDGPU Attributor
 ; GCN-O2-NEXT:      FunctionPass Manager
 ; GCN-O2-NEXT:        Cycle Info Analysis
 ; GCN-O2-NEXT:    FunctionPass Manager
 ; GCN-O2-NEXT:      Infer address spaces
 ; GCN-O2-NEXT:      Expand Atomic instructions

 ; GCN-O3-NEXT:    Pre-ISel Intrinsic Lowering
 ; GCN-O3-NEXT:    FunctionPass Manager
 ; GCN-O3-NEXT:      Expand large div/rem
 ; GCN-O3-NEXT:      Expand large fp convert
 ; GCN-O3-NEXT:    AMDGPU Printf lowering
 ; GCN-O3-NEXT:      FunctionPass Manager
 ; GCN-O3-NEXT:        Dominator Tree Construction
 ; GCN-O3-NEXT:    Lower ctors and dtors for AMDGPU
-; GCN-O3-NEXT:    AMDGPU Inline All Functions
-; GCN-O3-NEXT:    Inliner for always_inline functions
-; GCN-O3-NEXT:      FunctionPass Manager
-; GCN-O3-NEXT:        Dominator Tree Construction
-; GCN-O3-NEXT:        Basic Alias Analysis (stateless AA impl)
-; GCN-O3-NEXT:        Function Alias Analysis Results
 ; GCN-O3-NEXT:    Lower OpenCL enqueued blocks
 ; GCN-O3-NEXT:    Lower uses of LDS variables from non-kernel functions
 ; GCN-O3-NEXT:    AMDGPU Attributor
 ; GCN-O3-NEXT:      FunctionPass Manager
 ; GCN-O3-NEXT:        Cycle Info Analysis
 ; GCN-O3-NEXT:    FunctionPass Manager
 ; GCN-O3-NEXT:      Infer address spaces
 ; GCN-O3-NEXT:      Expand Atomic instructions

llvm/test/CodeGen/AMDGPU/smed3.ll

-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
+; RUN: opt -passes=inline -o %t.bc %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %t.bc | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %t.bc | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %t.bc | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
 
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 ; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i32:
 ; GCN: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
 define amdgpu_kernel void @v_test_smed3_r_i_i_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #1 {
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep0 = getelementptr i32, ptr addrspace(1) %aptr, i32 %tid

llvm/test/CodeGen/AMDGPU/stress-calls.ll

-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-stress-function-calls -passes=amdgpu-always-inline %s | FileCheck %s
-
-; CHECK: define internal fastcc i32 @alwaysinline_func(i32 %a) #0 {
-define internal fastcc i32 @alwaysinline_func(i32 %a) alwaysinline {
-entry:
-  %tmp0 = add i32 %a, 1
-  ret i32 %tmp0
-}
-
-; CHECK: define internal fastcc i32 @noinline_func(i32 %a) #1 {
-define internal fastcc i32 @noinline_func(i32 %a) noinline {
-entry:
-  %tmp0 = add i32 %a, 2
-  ret i32 %tmp0
-}
-
-; CHECK: define internal fastcc i32 @unmarked_func(i32 %a) #1 {
-define internal fastcc i32 @unmarked_func(i32 %a) {
-entry:
-  %tmp0 = add i32 %a, 3
-  ret i32 %tmp0
-}
-
-define amdgpu_kernel void @kernel(ptr addrspace(1) %out) {
-entry:
-  %tmp0 = call i32 @alwaysinline_func(i32 1)
-  store volatile i32 %tmp0, ptr addrspace(1) %out
-  %tmp1 = call i32 @noinline_func(i32 1)
-  store volatile i32 %tmp1, ptr addrspace(1) %out
-  %tmp2 = call i32 @unmarked_func(i32 1)
-  store volatile i32 %tmp2, ptr addrspace(1) %out
-  ret void
-}
-
-; CHECK: attributes #0 = { alwaysinline }
-; CHECK: attributes #1 = { noinline }

llvm/test/CodeGen/AMDGPU/umed3.ll

-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN  -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
+; RUN: opt -passes=inline -o %t.bc %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %t.bc | FileCheck -check-prefix=GCN  -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %t.bc | FileCheck -check-prefix=GCN -check-prefix=VI %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %t.bc | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
 
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 ; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i32:
 ; GCN: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
 define amdgpu_kernel void @v_test_umed3_r_i_i_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #1 {
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep0 = getelementptr i32, ptr addrspace(1) %aptr, i32 %tid