[AArch64][NFC] Normalise name of indexed forms of SQRDMLAH/SQRDMLSH

[rjj]

Summary

Most indexed vector instructions are suffixed with v<N><TY>_indexed.

SQRDMLAH/SQRDMLSH are the exception—they are suffixed with <TY>_indexed.
This can complicate matching slightly.

[dmgreen]

Thanks. There is a mention of i32_indexed in llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll that looks like it references the same thing. Other than that I agree this looks better.

Thanks for splitting it out. LGTM.

[rjj]

• Update mention in llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll

[rjj]

In D152161#4396263, @dmgreen wrote:

Thanks. There is a mention of i32_indexed in llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll that looks like it references the same thing. Other than that I agree this looks better.

Thanks for splitting it out. LGTM.

Thanks very much, I've updated llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll too!

llvm/lib/Target/AArch64/AArch64InstrFormats.td

[(set (v4i32 V128:$dst),
           (v4i32 (op (v4i32 V128:$Rd), (v4i32 V128:$Rn),
                      (v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
                                               VectorIndexS:$idx)))))]> {
     bits<2> idx;
     let Inst{11} = idx{1};
     let Inst{21} = idx{0};
   }
 
-  def i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
+  def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
                                           FPR16Op, FPR16Op, V128_lo,
                                           VectorIndexH, asm, ".h", "", "", ".h",
                                           []> {
     bits<3> idx;
     let Inst{11} = idx{2};
     let Inst{21} = idx{1};
     let Inst{20} = idx{0};
   }
 
-  def i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
+  def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
                                           FPR32Op, FPR32Op, V128, VectorIndexS,
                                           asm, ".s", "", "", ".s",
     [(set (i32 FPR32Op:$dst),
           (i32 (op (i32 FPR32Op:$Rd), (i32 FPR32Op:$Rn),
                    (i32 (vector_extract (v4i32 V128:$Rm),
                                         VectorIndexS:$idx)))))]> {
     bits<2> idx;
     let Inst{11} = idx{1};
     let Inst{21} = idx{0};
   }

llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll

; CHECK-NEXT:    ret
   %prod = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %mhs,  i32 %rhs)
   %retval =  call i32 @llvm.aarch64.neon.sqsub.i32(i32 %acc,  i32 %prod)
   ret i32 %retval
 }
 
 ;-----------------------------------------------------------------------------
 ; RDMA Scalar, by element
 ; i16 tests are performed via tests in above chapter, with IR in ACLE style
-; i32 tests are for i32_indexed in SIMDIndexedSQRDMLxHSDTied
+; i32 tests are for v1i32_indexed in SIMDIndexedSQRDMLxHSDTied
 
 define i16 @test_sqrdmlah_extract_i16(i16 %acc, i16 %x, <4 x i16> %y_vec) {
 ; CHECK-LABEL: test_sqrdmlah_extract_i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmov s1, w1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    sqrdmulh v0.4h, v1.4h, v0.h[1]
 ; CHECK-NEXT:    fmov s1, w0