[Analysis][LoongArch] Add sign extension for i32 parameters and returns

[Ami-zhang]

Summary

In LoongArch ABI spec, we can see that in the LP64D ABI, unsigned 32-bit
types, such as unsigned int, are stored in general-purpose registers as
proper sign extensions of their 32-bit values.

Reference:
https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html#_abi_lp64d

[xen0n]

llvm/include/llvm/Analysis/TargetLibraryInfo.h

414–415

The comment should be tweaked accordingly too.

[Ami-zhang]

llvm/include/llvm/Analysis/TargetLibraryInfo.h

414–415

Done.
Thanks for your reminder.

[Ami-zhang]

Modify comments

[SixWeining]

llvm/test/Instrumentation/AddressSanitizer/experiment.ll

123

Better to sort alphabetically.

[SixWeining]

llvm/include/llvm/Analysis/TargetLibraryInfo.h

415–417

Better to sort alphabetically.

[Ami-zhang]

llvm/include/llvm/Analysis/TargetLibraryInfo.h

415–417

Ok.

[Ami-zhang]

slightly adjusted the order

[xen0n]

Thanks!

llvm/include/llvm/Analysis/TargetLibraryInfo.h

static void initExtensionsForTriple(bool &ShouldExtI32Param,
     ShouldSignExtI32Param = ShouldSignExtI32Return = false;
 
     // PowerPC64, Sparc64, SystemZ need signext/zeroext on i32 parameters and
     // returns corresponding to C-level ints and unsigned ints.
     if (T.isPPC64() || T.getArch() == Triple::sparcv9 ||
         T.getArch() == Triple::systemz) {
       ShouldExtI32Param = true;
       ShouldExtI32Return = true;
     }
-    // Mips and riscv64, on the other hand, needs signext on i32 parameters
-    // corresponding to both signed and unsigned ints.
-    if (T.isMIPS() || T.isRISCV64()) {
+    // LoongArch, Mips, and riscv64, on the other hand, need signext on i32
+    // parameters corresponding to both signed and unsigned ints.
+    if (T.isLoongArch() || T.isMIPS() || T.isRISCV64()) {
       ShouldSignExtI32Param = true;
     }
-    // riscv64 needs signext on i32 returns corresponding to both signed and
-    // unsigned ints.
-    if (T.isRISCV64()) {
+    // LoongArch and riscv64 need signext on i32 returns corresponding to both
+    // signed and unsigned ints.
+    if (T.isLoongArch() || T.isRISCV64()) {
       ShouldSignExtI32Return = true;
     }
   }
 
   /// Returns extension attribute kind to be used for i32 parameters
   /// corresponding to C-level int or unsigned int.  May be zeroext, signext,
   /// or none.
 private:

llvm/test/Instrumentation/AddressSanitizer/experiment.ll

 ; Test optimization experiments.
 ; -asan-force-experiment flag turns all memory accesses into experiments.
 ; RUN: opt < %s -passes=asan -asan-force-experiment=42 -S | FileCheck %s
 ; RUN: opt < %s -passes=asan -asan-force-experiment=42 -S -mtriple=s390x-unknown-linux | FileCheck %s --check-prefix=EXT
 ; RUN: opt < %s -passes=asan -asan-force-experiment=42 -S -mtriple=mips-linux-gnu | FileCheck %s --check-prefix=MIPS_EXT
-; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target
+; RUN: opt < %s -passes=asan -asan-force-experiment=42 -S -mtriple=loongarch64-unknown-linux-gnu | FileCheck %s --check-prefix=LA_EXT
+; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target, loongarch-registered-target
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"
 
 define void @load1(ptr %p) sanitize_address {
 entry:
   %t = load i8, ptr %p, align 1
   ret void

 ; CHECK-LABEL: define void @storeN
 ; CHECK: __asan_report_exp_store_n{{.*}} i32 42
 ; CHECK: ret void
 }
 
 ; CHECK:    declare void @__asan_report_exp_load_n(i64, i64, i32)
 ; EXT:      declare void @__asan_report_exp_load_n(i64, i64, i32 zeroext)
 ; MIPS_EXT: declare void @__asan_report_exp_load_n(i64, i64, i32 signext)
+; LA_EXT:   declare void @__asan_report_exp_load_n(i64, i64, i32 signext)
 
 ; CHECK:    declare void @__asan_exp_loadN(i64, i64, i32)
 ; EXT:      declare void @__asan_exp_loadN(i64, i64, i32 zeroext)
 ; MIPS_EXT: declare void @__asan_exp_loadN(i64, i64, i32 signext)
+; LA_EXT:   declare void @__asan_exp_loadN(i64, i64, i32 signext)
 
 ; CHECK:    declare void @__asan_report_exp_load1(i64, i32)
 ; EXT:      declare void @__asan_report_exp_load1(i64, i32 zeroext)
 ; MIPS_EXT: declare void @__asan_report_exp_load1(i64, i32 signext)
+; LA_EXT:   declare void @__asan_report_exp_load1(i64, i32 signext)
 
 ; CHECK:    declare void @__asan_exp_load1(i64, i32)
 ; EXT:      declare void @__asan_exp_load1(i64, i32 zeroext)
 ; MIPS_EXT: declare void @__asan_exp_load1(i64, i32 signext)
+; LA_EXT:   declare void @__asan_exp_load1(i64, i32 signext)

llvm/test/Instrumentation/AddressSanitizer/mem-intrinsics.ll

 ; Test memory intrinsics instrumentation
 
 ; RUN: opt < %s -passes=asan -S | FileCheck --check-prefixes=CHECK,CHECK-PREFIX %s
 ; RUN: opt < %s -passes=asan -asan-kernel -S | FileCheck --check-prefixes=CHECK,CHECK-NOPREFIX %s
 ; RUN: opt < %s -passes=asan -asan-kernel -asan-kernel-mem-intrinsic-prefix -S | FileCheck --check-prefixes=CHECK,CHECK-PREFIX %s
 ; RUN: opt < %s -passes=asan -S -mtriple=s390x-unknown-linux | FileCheck --check-prefix=EXT %s
 ; RUN: opt < %s -passes=asan -S -mtriple=mips-linux-gnu | FileCheck --check-prefix=MIPS_EXT %s
-; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target
+; RUN: opt < %s -passes=asan -S -mtriple=loongarch64-unknown-linux-gnu | FileCheck --check-prefix=LA_EXT %s
+; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target, loongarch-registered-target
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"
 
 declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind
 declare void @llvm.memset.inline.p0.i64(ptr nocapture, i8, i64, i1) nounwind
 declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) nounwind
 declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) nounwind
define void @memintr_element_atomic_test(ptr %a, ptr %b) nounwind uwtable sanitize_address {
   tail call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %a, ptr align 1 %b, i64 100, i32 1)
   tail call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %a, ptr align 1 %b, i64 100, i32 1)
   ret void
 }
 
 ; CHECK-PREFIX: declare ptr @__asan_memset(ptr, i32, i64)
 ; EXT:          declare ptr @__asan_memset(ptr, i32 zeroext, i64)
 ; MIPS_EXT:     declare ptr @__asan_memset(ptr, i32 signext, i64)
+; LA_EXT:       declare ptr @__asan_memset(ptr, i32 signext, i64)

llvm/test/Instrumentation/ThreadSanitizer/atomic.ll

 ; RUN: opt < %s -passes=tsan -S | FileCheck %s
 ; RUN: opt < %s -passes=tsan -S -mtriple=s390x-unknown-linux | FileCheck --check-prefix=EXT %s
 ; RUN: opt < %s -passes=tsan -S -mtriple=mips-linux-gnu | FileCheck --check-prefix=MIPS_EXT %s
-; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target
+; RUN: opt < %s -passes=tsan -S -mtriple=loongarch64-unknown-linux-gnu | FileCheck --check-prefix=LA_EXT %s
+; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target, loongarch-registered-target
 ; Check that atomic memory operations are converted to calls into ThreadSanitizer runtime.
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
 define i8 @atomic8_load_unordered(ptr %a) nounwind uwtable {
 entry:
   %0 = load atomic i8, ptr %a unordered, align 1, !dbg !7
   ret i8 %0, !dbg !7
 }
entry:
   ret void, !dbg !7
 }
 ; CHECK-LABEL: atomic_thread_fence_seq_cst
 ; CHECK: call void @__tsan_atomic_thread_fence(i32 5), !dbg
 
 ; CHECK:    declare void @__tsan_atomic32_store(ptr, i32, i32)
 ; EXT:      declare void @__tsan_atomic32_store(ptr, i32 signext, i32 signext)
 ; MIPS_EXT: declare void @__tsan_atomic32_store(ptr, i32 signext, i32 signext)
+; LA_EXT:   declare void @__tsan_atomic32_store(ptr, i32 signext, i32 signext)
 
 ; CHECK:    declare i32 @__tsan_atomic32_compare_exchange_val(ptr, i32, i32, i32, i32)
 ; EXT:      declare signext i32 @__tsan_atomic32_compare_exchange_val(ptr, i32 signext, i32 signext, i32 signext, i32 signext)
 ; MIPS_EXT: declare i32 @__tsan_atomic32_compare_exchange_val(ptr, i32 signext, i32 signext, i32 signext, i32 signext)
+; LA_EXT:   declare signext i32 @__tsan_atomic32_compare_exchange_val(ptr, i32 signext, i32 signext, i32 signext, i32 signext)
 
 ; CHECK:    declare i64 @__tsan_atomic64_load(ptr, i32)
 ; EXT:      declare i64 @__tsan_atomic64_load(ptr, i32 signext)
 ; MIPS_EXT: declare i64 @__tsan_atomic64_load(ptr, i32 signext)
+; LA_EXT:   declare i64 @__tsan_atomic64_load(ptr, i32 signext)
 
 ; CHECK:    declare void @__tsan_atomic64_store(ptr, i64, i32)
 ; EXT:      declare void @__tsan_atomic64_store(ptr, i64, i32 signext)
 ; MIPS_EXT: declare void @__tsan_atomic64_store(ptr, i64, i32 signext)
+; LA_EXT:   declare void @__tsan_atomic64_store(ptr, i64, i32 signext)
 
 ; CHECK:    declare i64 @__tsan_atomic64_fetch_add(ptr, i64, i32)
 ; EXT:      declare i64 @__tsan_atomic64_fetch_add(ptr, i64, i32 signext)
 ; MIPS_EXT: declare i64 @__tsan_atomic64_fetch_add(ptr, i64, i32 signext)
+; LA_EXT:   declare i64 @__tsan_atomic64_fetch_add(ptr, i64, i32 signext)
 
 ; CHECK:    declare i64 @__tsan_atomic64_compare_exchange_val(ptr, i64, i64, i32, i32)
 ; EXT:      declare i64 @__tsan_atomic64_compare_exchange_val(ptr, i64, i64, i32 signext, i32 signext)
 ; MIPS_EXT: declare i64 @__tsan_atomic64_compare_exchange_val(ptr, i64, i64, i32 signext, i32 signext)
+; LA_EXT:   declare i64 @__tsan_atomic64_compare_exchange_val(ptr, i64, i64, i32 signext, i32 signext)
 
 ; CHECK:    declare void @__tsan_atomic_thread_fence(i32)
 ; EXT:      declare void @__tsan_atomic_thread_fence(i32 signext)
 ; MIPS_EXT: declare void @__tsan_atomic_thread_fence(i32 signext)
+; LA_EXT:   declare void @__tsan_atomic_thread_fence(i32 signext)
 
 ; CHECK:    declare void @__tsan_atomic_signal_fence(i32)
 ; EXT:      declare void @__tsan_atomic_signal_fence(i32 signext)
 ; MIPS_EXT: declare void @__tsan_atomic_signal_fence(i32 signext)
+; LA_EXT:   declare void @__tsan_atomic_signal_fence(i32 signext)
 
 ; CHECK:    declare ptr @__tsan_memset(ptr, i32, i64)
 ; EXT:      declare ptr @__tsan_memset(ptr, i32 signext, i64)
 ; MIPS_EXT: declare ptr @__tsan_memset(ptr, i32 signext, i64)
+; LA_EXT:   declare ptr @__tsan_memset(ptr, i32 signext, i64)
 
 !llvm.module.flags = !{!0, !1, !2}
 !llvm.dbg.cu = !{!8}
 !0 = !{i32 2, !"Dwarf Version", i32 4}
 !1 = !{i32 2, !"Debug Info Version", i32 3}
 !2 = !{i32 1, !"PIC Level", i32 2}
 
 !3 = !{}