[RISCV][NFC] Add isF argument to SchedSEWSet

[• pcwang-thead]

Summary

So that we can remove SchedSEWSetF and simplify some code.

[michaelmaitland]

LGTM with minor comment.

llvm/lib/Target/RISCV/RISCVScheduleV.td

24

Should we add an assert that LMUL should not be M8 for widening?

[• pcwang-thead]

llvm/lib/Target/RISCV/RISCVScheduleV.td

24

Should we add an assert that LMUL should not be M8 for widening?

24

The scalar operand of reductions can be M8, so I think we can't assert that.

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVScheduleV.td

24

What does it mean for a scale operand to be M8? I’m not sure LMUL applies to scalar operands.

24

What does it mean for a scale operand to be M8? I’m not sure LMUL applies to scalar operands.

*Scalar

[craig.topper]

llvm/lib/Target/RISCV/RISCVScheduleV.td

24

The scalar operand is always LMUL=1. But the vector operand of a widening reduction can be LMUL=8 as long at the SEW is less than ELEN. Widening reductions produce a single element result with 2*SEW.

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVScheduleV.td

24

Got it. This change looks good and I have no more questions about this assertion.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

let VLMul = m.value in {
                                  Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVSQR_V {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar sews = SchedSEWSetF<m.MX>.val;
+    defvar sews = SchedSEWSet<m.MX, /*isF*/ 1>.val;
 
     let VLMul = m.value in
       foreach e = sews in {
         defvar suffix = "_" # mx # "_E" # e;
         defvar WriteVFSqrtV_MX_E = !cast<SchedWrite>("WriteVFSqrtV" # suffix);
         defvar ReadVFSqrtV_MX_E = !cast<SchedRead>("ReadVFSqrtV" # suffix);
 
         def "_V" # suffix : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
foreach m = f.MxList in {
                 Sched<[WriteVFMulF_MX, ReadVFMulV_MX, ReadVFMulF_MX, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVFDIV_VV_VF {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar sews = SchedSEWSetF<mx>.val;
+    defvar sews = SchedSEWSet<mx, /*isF*/ 1>.val;
     foreach e = sews in {
       defvar WriteVFDivV_MX_E = !cast<SchedWrite>("WriteVFDivV_" # mx # "_E" # e);
       defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
 
       defm "" : VPseudoBinaryFV_VV_E<m, e>,
                 Sched<[WriteVFDivV_MX_E, ReadVFDivV_MX_E, ReadVFDivV_MX_E, ReadVMask]>;
     }
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar sews = SchedSEWSetF<mx>.val;
+      defvar sews = SchedSEWSet<mx, /*isF*/ 1>.val;
       foreach e = sews in {
         defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
         defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
         defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # e);
 
         defm "" : VPseudoBinaryV_VF_E<m, e, f>,
                   Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
       }
     }
   }
 }
 
 multiclass VPseudoVFRDIV_VF {
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar sews = SchedSEWSetF<mx>.val;
+      defvar sews = SchedSEWSet<mx, /*isF*/ 1>.val;
       foreach e = sews in {
         defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
         defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
         defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # e);
 
         defm "" : VPseudoBinaryV_VF_E<m, e, f>,
                   Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
       }
foreach e = SchedSEWSet<mx>.val in {
                         ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVWRED_VS {
   foreach m = MxListWRed in {
     defvar mx = m.MX;
-    foreach e = SchedSEWSet<mx, 1>.val in {
+    foreach e = SchedSEWSet<mx, /*isF*/ 0, /*isWidening*/ 1>.val in {
       defvar WriteVIWRedV_From_MX_E = !cast<SchedWrite>("WriteVIWRedV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
                  Sched<[WriteVIWRedV_From_MX_E, ReadVIWRedV, ReadVIWRedV,
                         ReadVIWRedV, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVFRED_VS {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    foreach e = SchedSEWSetF<mx>.val in {
+    foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
       defvar WriteVFRedV_From_MX_E = !cast<SchedWrite>("WriteVFRedV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
                  Sched<[WriteVFRedV_From_MX_E, ReadVFRedV, ReadVFRedV, ReadVFRedV,
                         ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVFREDO_VS {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    foreach e = SchedSEWSetF<mx>.val in {
+    foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
       defvar WriteVFRedOV_From_MX_E = !cast<SchedWrite>("WriteVFRedOV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
                  Sched<[WriteVFRedOV_From_MX_E, ReadVFRedOV, ReadVFRedOV,
                         ReadVFRedOV, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVFWRED_VS {
   foreach m = MxListFWRed in {
     defvar mx = m.MX;
-    foreach e = SchedSEWSetF<mx, 1>.val in {
+    foreach e = SchedSEWSet<mx, /*isF*/ 1, /*isWidening*/ 1>.val in {
       defvar WriteVFWRedV_From_MX_E = !cast<SchedWrite>("WriteVFWRedV_From_" # mx # "_E" # e);
       defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
                  Sched<[WriteVFWRedV_From_MX_E, ReadVFWRedV, ReadVFWRedV,
                         ReadVFWRedV, ReadVMask]>;
     }
   }
 }
 

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

foreach mx = SchedMxList in {
   }
   // Mask results can't chain.
   let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVFCmpV",      [SiFive7VA], mx, IsWorstCase>;
     defm "" : LMULWriteResMX<"WriteVFCmpF",      [SiFive7VA], mx, IsWorstCase>;
   }
 }
 foreach mx = SchedMxListF in {
-  foreach sew = SchedSEWSetF<mx>.val in {
+  foreach sew = SchedSEWSet<mx, /*isF*/ 1>.val in {
     defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
                          !div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
     let Latency = Cycles, ResourceCycles = [Cycles] in {
       defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFive7VA], mx, sew, IsWorstCase>;
       defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV",  [SiFive7VA], mx, sew, IsWorstCase>;
       defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF",  [SiFive7VA], mx, sew, IsWorstCase>;
     }

llvm/lib/Target/RISCV/RISCVScheduleV.td

 // Used for widening reductions, which does contain M8.
 defvar SchedMxListWRed = SchedMxList;
 defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
 // Used for floating-point as it doesn't contain MF8.
 defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
 // Used for widening floating-point Reduction as it doesn't contain MF8.
 defvar SchedMxListFWRed = SchedMxListF;
 
-// For widening instructions, SEW will not be 64.
-class SchedSEWSet<string mx, bit isWidening = 0> {
+class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
+  assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
   defvar t = !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
                    !eq(mx, "M2"):  [8, 16, 32, 64],
                    !eq(mx, "M4"):  [8, 16, 32, 64],
                    !eq(mx, "M8"):  [8, 16, 32, 64],
                    !eq(mx, "MF2"): [8, 16, 32],
                    !eq(mx, "MF4"): [8, 16],
                    !eq(mx, "MF8"): [8]);
-  list<int> val = !if(isWidening, !listremove(t, [64]), t);
-}
-
   // For floating-point instructions, SEW won't be 8.
-class SchedSEWSetF<string mx, bit isWidening = 0> {
-  defvar t = !cond(!eq(mx, "M1"):  [16, 32, 64],
-                   !eq(mx, "M2"):  [16, 32, 64],
-                   !eq(mx, "M4"):  [16, 32, 64],
-                   !eq(mx, "M8"):  [16, 32, 64],
-                   !eq(mx, "MF2"): [16, 32],
-                   !eq(mx, "MF4"): [16]);
-  list<int> val = !if(isWidening, !listremove(t, [64]), t);
+  defvar remove8 = !if(isF, !listremove(t, [8]), t);
+  // For widening instructions, SEW will not be 64.
+  defvar remove64 = !if(isWidening, !listremove(remove8, [64]), remove8);
+  list<int> val = remove64;
 }
 
 // Helper function to get the largest LMUL from MxList
 // Precondition: MxList is sorted in ascending LMUL order.
 class LargestLMUL<list<string> MxList> {
   // MX list is sorted from smallest to largest
   string r = !foldl(!head(MxList), MxList, last, curr, curr);
 }
 // Helper function to get the smallest SEW that can be used with LMUL mx
 // Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet<mx>
 class SmallestSEW<string mx, bit isF = 0> {
-  int r = !head(!if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val));
+  int r = !head(SchedSEWSet<mx, isF>.val);
 }
 
 // Creates WriteRes for (name, mx, resources) tuple
 multiclass LMULWriteResMX<string name, list<ProcResourceKind> resources,
                           string mx, bit IsWorstCase> {
   def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
   if IsWorstCase then
     def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;

 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
 // a record that represents the WorseCase behavior for name.
 multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0,
                                   bit isWidening = 0> {
   def name # "_WorstCase" : SchedWrite;
   foreach mx = MxList in {
-    foreach sew = !if(isF, SchedSEWSetF<mx, isWidening>.val,
-                      SchedSEWSet<mx, isWidening>.val) in
+    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
       def name # "_" # mx # "_E" # sew : SchedWrite;
   }
 }
 multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0,
                                  bit isWidening = 0> {
   def name # "_WorstCase" : SchedRead;
   foreach mx = MxList in {
-    foreach sew = !if(isF,SchedSEWSetF<mx, isWidening>.val,
-                      SchedSEWSet<mx, isWidening>.val) in
+    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
       def name # "_" # mx # "_E" # sew : SchedRead;
   }
 }
 multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
                                list<string> MxList, bit isF = 0,
                                bit isWidening = 0> {
   if !exists<SchedWrite>(name # "_WorstCase") then
     def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
   foreach mx = MxList in {
-    foreach sew = !if(isF,SchedSEWSetF<mx, isWidening>.val,
-                      SchedSEWSet<mx, isWidening>.val) in
+    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
       if !exists<SchedWrite>(name # "_" # mx # "_E" # sew) then
         def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
   }
 }
 multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [],
                                   list<string> MxList, bit isF = 0,
                                   bit isWidening = 0> {
   if !exists<SchedRead>(name # "_WorstCase") then
     def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
   foreach mx = MxList in {
-    foreach sew = !if(isF,SchedSEWSetF<mx, isWidening>.val,
-                      SchedSEWSet<mx, isWidening>.val) in
+    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
       if !exists<SchedRead>(name # "_" # mx # "_E" # sew) then
         def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
   }
 }
 // Define classes to define list containing all SchedWrites for each (name, LMUL)
 // pair for each LMUL in each of the SchedMxList variants above and name in
 // argument `names`. These classes can be used to construct a list of existing
 // definitions of writes corresponding to each (name, LMUL) pair, that are needed