[RISCV] Implement storeOfVectorConstantIsCheap hook to prevent store merging at VL=2

[reames]

Summary

In general, VL=2 vectors are very questionable profitability wise. For constants specifically, our inability to materialize many vector constants cheaply biases us strongly towards unprofitability at VL=2.

This hook is very close to the x86 implementation. The difference is that X86 whitelists stores of zeros, and we're better off letting that stay scalar at VL=2.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.h

538

I notice X86 uses > 2 and your patch description talks about VL=2 and mentions being similar to X86, but you've used 4 here. Is 3 supported by store merging?

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.h

538

All the 3 x N types are illegal, and thus not candidates for store merging.

I mostly used 4 here as a bit of future proofing in case we decided to make odd types legal via the VP lowering which got some discussion recently. I'm not sure that we wouldn't want VL=3 to be formed in that case, but I figured it was better not to and then revisit if desired. (All of the cases I have where odd types would be profitable are VL=6. Yes, all of them.)

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.h

public:
   bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
                             bool MathUsed) const override {
     if (VT == MVT::i8 || VT == MVT::i16)
       return false;
 
     return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);
   }
 
+  bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem,
+                                    unsigned AddrSpace) const override {
+    // If we can replace 4 or more scalar stores, there will be a reduction
+    // in instructions even after we add a vector constant load.
+    return NumElem >= 4;
+  }
+
   bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
     return VT.isScalarInteger();
   }
   bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
 
   bool preferZeroCompareBranch() const override { return true; }
 
   bool shouldInsertFencesForAtomic(const Instruction *I) const override {

llvm/test/CodeGen/RISCV/rvv/combine-store.ll

; CHECK-NEXT:    ret
   %gep3 = getelementptr i8, ptr %p, i64 3
   store i8 zeroinitializer, ptr %gep3
   ret void
 }
 
 define void @combine_zero_stores_8xi8(ptr %p) {
 ; RV32-LABEL: combine_zero_stores_8xi8:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vmv.v.i v8, 0
-; RV32-NEXT:    vse32.v v8, (a0)
+; RV32-NEXT:    sw zero, 0(a0)
+; RV32-NEXT:    sw zero, 4(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: combine_zero_stores_8xi8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    sd zero, 0(a0)
 ; RV64-NEXT:    ret
   store i8 zeroinitializer, ptr %p, align 8
   %gep1 = getelementptr i8, ptr %p, i64 1
; CHECK-NEXT:    ret
   %gep = getelementptr i8, ptr %p, i64 2
   store i16 zeroinitializer, ptr %gep
   ret void
 }
 
 define void @combine_zero_stores_4xi16(ptr %p) {
 ; RV32-LABEL: combine_zero_stores_4xi16:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vmv.v.i v8, 0
-; RV32-NEXT:    vse32.v v8, (a0)
+; RV32-NEXT:    sw zero, 0(a0)
+; RV32-NEXT:    sw zero, 4(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: combine_zero_stores_4xi16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    sd zero, 0(a0)
 ; RV64-NEXT:    ret
   store i16 zeroinitializer, ptr %p, align 8
   %gep1 = getelementptr i16, ptr %p, i64 1

 ; RV32-NEXT:    sh zero, 6(a0)
 ; RV32-NEXT:    sw zero, 8(a0)
 ; RV32-NEXT:    sh zero, 12(a0)
 ; RV32-NEXT:    sh zero, 14(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: combine_zero_stores_8xi16:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; RV64-NEXT:    vmv.v.i v8, 0
-; RV64-NEXT:    vse64.v v8, (a0)
+; RV64-NEXT:    sd zero, 0(a0)
+; RV64-NEXT:    sd zero, 8(a0)
 ; RV64-NEXT:    ret
   store i16 zeroinitializer, ptr %p, align 16
   %gep1 = getelementptr i16, ptr %p, i64 1
   store i16 zeroinitializer, ptr %gep1
   %gep2 = getelementptr i16, ptr %p, i64 2
   store i16 zeroinitializer, ptr %gep2
   %gep3 = getelementptr i16, ptr %p, i64 3
   store i16 zeroinitializer, ptr %gep3
   %gep4 = getelementptr i16, ptr %p, i64 4
   store i16 zeroinitializer, ptr %gep4, align 8
   %gep5 = getelementptr i16, ptr %p, i64 5
   store i16 zeroinitializer, ptr %gep5
   %gep6 = getelementptr i16, ptr %p, i64 6
   store i16 zeroinitializer, ptr %gep6
   %gep7 = getelementptr i16, ptr %p, i64 7
   store i16 zeroinitializer, ptr %gep7
   ret void
 }
 
 define void @combine_zero_stores_2xi32(ptr %p) {
 ; RV32-LABEL: combine_zero_stores_2xi32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vmv.v.i v8, 0
-; RV32-NEXT:    vse32.v v8, (a0)
+; RV32-NEXT:    sw zero, 0(a0)
+; RV32-NEXT:    sw zero, 4(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: combine_zero_stores_2xi32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    sd zero, 0(a0)
 ; RV64-NEXT:    ret
   store i32 zeroinitializer, ptr %p, align 8
   %gep = getelementptr i8, ptr %p, i64 4
   store i32 zeroinitializer, ptr %gep
   ret void
 }
 
 define void @combine_zero_stores_4xi32(ptr %p) {
 ; RV32-LABEL: combine_zero_stores_4xi32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; RV32-NEXT:    vmv.v.i v8, 0
 ; RV32-NEXT:    vse32.v v8, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: combine_zero_stores_4xi32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; RV64-NEXT:    vmv.v.i v8, 0
-; RV64-NEXT:    vse64.v v8, (a0)
+; RV64-NEXT:    sd zero, 0(a0)
+; RV64-NEXT:    sd zero, 8(a0)
 ; RV64-NEXT:    ret
   store i32 zeroinitializer, ptr %p, align 16
   %gep1 = getelementptr i32, ptr %p, i64 1
   store i32 zeroinitializer, ptr %gep1
   %gep2 = getelementptr i32, ptr %p, i64 2
   store i32 zeroinitializer, ptr %gep2, align 8
   %gep3 = getelementptr i32, ptr %p, i64 3
   store i32 zeroinitializer, ptr %gep3
; RV64-NEXT:    ret
   %gep6 = getelementptr i32, ptr %p, i64 6
   store i32 zeroinitializer, ptr %gep6, align 8
   %gep7 = getelementptr i32, ptr %p, i64 7
   store i32 zeroinitializer, ptr %gep7
   ret void
 }
 
 define void @combine_zero_stores_2xi32_unaligned(ptr %p) {
-; RV32-LABEL: combine_zero_stores_2xi32_unaligned:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; RV32-NEXT:    vmv.v.i v8, 0
-; RV32-NEXT:    vse32.v v8, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: combine_zero_stores_2xi32_unaligned:
-; RV64:       # %bb.0:
-; RV64-NEXT:    sw zero, 0(a0)
-; RV64-NEXT:    sw zero, 4(a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: combine_zero_stores_2xi32_unaligned:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sw zero, 0(a0)
+; CHECK-NEXT:    sw zero, 4(a0)
+; CHECK-NEXT:    ret
   store i32 zeroinitializer, ptr %p
   %gep = getelementptr i8, ptr %p, i64 4
   store i32 zeroinitializer, ptr %gep
   ret void
 }
 
 define void @combine_zero_stores_2xi64(ptr %p) {
 ; RV32-LABEL: combine_zero_stores_2xi64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    sw zero, 4(a0)
 ; RV32-NEXT:    sw zero, 0(a0)
 ; RV32-NEXT:    sw zero, 12(a0)
 ; RV32-NEXT:    sw zero, 8(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: combine_zero_stores_2xi64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; RV64-NEXT:    vmv.v.i v8, 0
-; RV64-NEXT:    vse64.v v8, (a0)
+; RV64-NEXT:    sd zero, 0(a0)
+; RV64-NEXT:    sd zero, 8(a0)
 ; RV64-NEXT:    ret
   store i64 zeroinitializer, ptr %p
   %gep = getelementptr i8, ptr %p, i64 8
   store i64 zeroinitializer, ptr %gep
   ret void
 }
 
 define void @combine_fp_zero_stores_crash(ptr %ptr)  {
 ; CHECK-LABEL: combine_fp_zero_stores_crash:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, a0, 4
-; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    sw zero, 4(a0)
+; CHECK-NEXT:    sw zero, 8(a0)
 ; CHECK-NEXT:    ret
   %addr1 = getelementptr float, ptr %ptr, i64 1
   %addr2 = getelementptr float, ptr %ptr, i64 2
   store float 0.000000e+00, ptr %addr1, align 4
   store float 0.000000e+00, ptr %addr2, align 4
   ret void
 }