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Differential D150787

[PowerPC] Add DFP multiply and divide instructions.
ClosedPublic

Authored by stefanp on May 17 2023, 8:19 AM.

Details

Reviewers
lei
nemanjai
amyk
power-llvm-team
Commits
rGdf367da5a683: [PowerPC] Add DFP multiply and divide instructions.
Summary

This patch adds the DFP mul and div instructions. This includes both the
double and quad forms of the instructions as well as the record form.

Diff Detail

Unit TestsFailed

TimeTest
60,030 msx64 debian > MLIR.Examples/standalone::test.toy

Event Timeline

stefanp created this revision.May 17 2023, 8:19 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 17 2023, 8:19 AM
Herald added subscribers: shchenz, kbarton, hiraditya. · View Herald Transcript
stefanp requested review of this revision.May 17 2023, 8:19 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 17 2023, 8:19 AM
stefanp added a reviewer: power-llvm-team.May 17 2023, 8:23 AM
stefanp retitled this revision from [PowerPC] Add DFP multiply and add instructions. to [PowerPC] Add DFP multiply and divide instructions..May 17 2023, 8:29 AM
Harbormaster completed remote builds in B232618: Diff 523059.May 17 2023, 9:15 AM
amyk accepted this revision.May 18 2023, 7:12 AM

This LGTM.

This revision is now accepted and ready to land.May 18 2023, 7:12 AM
This revision was landed with ongoing or failed builds.May 18 2023, 7:36 AM
Closed by commit rGdf367da5a683: [PowerPC] Add DFP multiply and divide instructions. (authored by stefanp). · Explain Why
This revision was automatically updated to reflect the committed changes.
stefanp added a commit: rGdf367da5a683: [PowerPC] Add DFP multiply and divide instructions..

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
12 lines
test/
MC/
Disassembler/
PowerPC/
24 lines
PowerPC/
24 lines

Diff 523059

llvm/lib/Target/PowerPC/PPCInstrDFP.td

Show All 18 Lines
defm DADDQ : XForm_28r<63, 2, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB), defm DADDQ : XForm_28r<63, 2, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
"daddq", "$RST, $RA, $RB", IIC_FPGeneral, []>; "daddq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
defm DSUB : XForm_28r<59, 514, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB), defm DSUB : XForm_28r<59, 514, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
"dsub", "$RST, $RA, $RB", IIC_FPGeneral, []>; "dsub", "$RST, $RA, $RB", IIC_FPGeneral, []>;
defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB), defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
"dsubq", "$RST, $RA, $RB", IIC_FPGeneral, []>; "dsubq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
defm DMUL : XForm_28r<59, 34, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
"dmul", "$RST, $RA, $RB", IIC_FPGeneral, []>;
defm DMULQ : XForm_28r<63, 34, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
"dmulq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
defm DDIV : XForm_28r<59, 546, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
"ddiv", "$RST, $RA, $RB", IIC_FPGeneral, []>;
defm DDIVQ : XForm_28r<63, 546, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
"ddivq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
} }

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt

Show All 17 Lines
# CHECK: dsub. 2, 3, 4 # CHECK: dsub. 2, 3, 4
0xec 0x43 0x24 0x05 0xec 0x43 0x24 0x05
# CHECK: dsubq 2, 6, 4 # CHECK: dsubq 2, 6, 4
0xfc 0x46 0x24 0x04 0xfc 0x46 0x24 0x04
# CHECK: dsubq. 2, 6, 4 # CHECK: dsubq. 2, 6, 4
0xfc 0x46 0x24 0x05 0xfc 0x46 0x24 0x05
# CHECK: dmul 2, 3, 4
0xec 0x43 0x20 0x44
# CHECK: dmul. 2, 3, 4
0xec 0x43 0x20 0x45
# CHECK: dmulq 2, 6, 4
0xfc 0x46 0x20 0x44
# CHECK: dmulq. 2, 6, 4
0xfc 0x46 0x20 0x45
# CHECK: ddiv 2, 3, 4
0xec 0x43 0x24 0x44
# CHECK: ddiv. 2, 3, 4
0xec 0x43 0x24 0x45
# CHECK: ddivq 2, 6, 4
0xfc 0x46 0x24 0x44
# CHECK: ddivq. 2, 6, 4
0xfc 0x46 0x24 0x45

llvm/test/MC/PowerPC/ppc64-encoding-dfp.s

Show All 20 Lines
# CHECK-LE: dsub. 2, 3, 4 # encoding: [0x05,0x24,0x43,0xec] # CHECK-LE: dsub. 2, 3, 4 # encoding: [0x05,0x24,0x43,0xec]
dsub. 2, 3, 4 dsub. 2, 3, 4
# CHECK-BE: dsubq 2, 6, 4 # encoding: [0xfc,0x46,0x24,0x04] # CHECK-BE: dsubq 2, 6, 4 # encoding: [0xfc,0x46,0x24,0x04]
# CHECK-LE: dsubq 2, 6, 4 # encoding: [0x04,0x24,0x46,0xfc] # CHECK-LE: dsubq 2, 6, 4 # encoding: [0x04,0x24,0x46,0xfc]
dsubq 2, 6, 4 dsubq 2, 6, 4
# CHECK-BE: dsubq. 2, 6, 4 # encoding: [0xfc,0x46,0x24,0x05] # CHECK-BE: dsubq. 2, 6, 4 # encoding: [0xfc,0x46,0x24,0x05]
# CHECK-LE: dsubq. 2, 6, 4 # encoding: [0x05,0x24,0x46,0xfc] # CHECK-LE: dsubq. 2, 6, 4 # encoding: [0x05,0x24,0x46,0xfc]
dsubq. 2, 6, 4 dsubq. 2, 6, 4
# CHECK-BE: dmul 2, 3, 4 # encoding: [0xec,0x43,0x20,0x44]
# CHECK-LE: dmul 2, 3, 4 # encoding: [0x44,0x20,0x43,0xec]
dmul 2, 3, 4
# CHECK-BE: dmul. 2, 3, 4 # encoding: [0xec,0x43,0x20,0x45]
# CHECK-LE: dmul. 2, 3, 4 # encoding: [0x45,0x20,0x43,0xec]
dmul. 2, 3, 4
# CHECK-BE: dmulq 2, 6, 4 # encoding: [0xfc,0x46,0x20,0x44]
# CHECK-LE: dmulq 2, 6, 4 # encoding: [0x44,0x20,0x46,0xfc]
dmulq 2, 6, 4
# CHECK-BE: dmulq. 2, 6, 4 # encoding: [0xfc,0x46,0x20,0x45]
# CHECK-LE: dmulq. 2, 6, 4 # encoding: [0x45,0x20,0x46,0xfc]
dmulq. 2, 6, 4
# CHECK-BE: ddiv 2, 3, 4 # encoding: [0xec,0x43,0x24,0x44]
# CHECK-LE: ddiv 2, 3, 4 # encoding: [0x44,0x24,0x43,0xec]
ddiv 2, 3, 4
# CHECK-BE: ddiv. 2, 3, 4 # encoding: [0xec,0x43,0x24,0x45]
# CHECK-LE: ddiv. 2, 3, 4 # encoding: [0x45,0x24,0x43,0xec]
ddiv. 2, 3, 4
# CHECK-BE: ddivq 2, 6, 4 # encoding: [0xfc,0x46,0x24,0x44]
# CHECK-LE: ddivq 2, 6, 4 # encoding: [0x44,0x24,0x46,0xfc]
ddivq 2, 6, 4
# CHECK-BE: ddivq. 2, 6, 4 # encoding: [0xfc,0x46,0x24,0x45]
# CHECK-LE: ddivq. 2, 6, 4 # encoding: [0x45,0x24,0x46,0xfc]
ddivq. 2, 6, 4