[PowerPC] Add DFP multiply and divide instructions.

[stefanp]

Summary

This patch adds the DFP mul and div instructions. This includes both the
double and quad forms of the instructions as well as the record form.

[amyk]

This LGTM.

llvm/lib/Target/PowerPC/PPCInstrDFP.td

 defm DADDQ : XForm_28r<63, 2, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
                        "daddq",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
 
 defm DSUB : XForm_28r<59, 514, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
                       "dsub",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
 
 defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
                        "dsubq",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DMUL : XForm_28r<59, 34, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
+                      "dmul",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DMULQ : XForm_28r<63, 34, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
+                       "dmulq",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DDIV : XForm_28r<59, 546, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
+                      "ddiv",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DDIVQ : XForm_28r<63, 546, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
+                       "ddivq",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
 }
 

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt

 # CHECK: dsub. 2, 3, 4
 0xec 0x43 0x24 0x05
 
 # CHECK: dsubq 2, 6, 4
 0xfc 0x46 0x24 0x04
 
 # CHECK: dsubq. 2, 6, 4
 0xfc 0x46 0x24 0x05
+
+# CHECK: dmul 2, 3, 4
+0xec 0x43 0x20 0x44
+
+# CHECK: dmul. 2, 3, 4
+0xec 0x43 0x20 0x45
+
+# CHECK: dmulq 2, 6, 4
+0xfc 0x46 0x20 0x44
+
+# CHECK: dmulq. 2, 6, 4
+0xfc 0x46 0x20 0x45
+
+# CHECK: ddiv 2, 3, 4
+0xec 0x43 0x24 0x44
+
+# CHECK: ddiv. 2, 3, 4
+0xec 0x43 0x24 0x45
+
+# CHECK: ddivq 2, 6, 4
+0xfc 0x46 0x24 0x44
+
+# CHECK: ddivq. 2, 6, 4
+0xfc 0x46 0x24 0x45

llvm/test/MC/PowerPC/ppc64-encoding-dfp.s

 # CHECK-LE: dsub. 2, 3, 4                  # encoding: [0x05,0x24,0x43,0xec]
             dsub. 2, 3, 4
 # CHECK-BE: dsubq 2, 6, 4                  # encoding: [0xfc,0x46,0x24,0x04]
 # CHECK-LE: dsubq 2, 6, 4                  # encoding: [0x04,0x24,0x46,0xfc]
             dsubq 2, 6, 4
 # CHECK-BE: dsubq. 2, 6, 4                 # encoding: [0xfc,0x46,0x24,0x05]
 # CHECK-LE: dsubq. 2, 6, 4                 # encoding: [0x05,0x24,0x46,0xfc]
             dsubq. 2, 6, 4
+# CHECK-BE: dmul 2, 3, 4                   # encoding: [0xec,0x43,0x20,0x44]
+# CHECK-LE: dmul 2, 3, 4                   # encoding: [0x44,0x20,0x43,0xec]
+            dmul 2, 3, 4
+# CHECK-BE: dmul. 2, 3, 4                  # encoding: [0xec,0x43,0x20,0x45]
+# CHECK-LE: dmul. 2, 3, 4                  # encoding: [0x45,0x20,0x43,0xec]
+            dmul. 2, 3, 4
+# CHECK-BE: dmulq 2, 6, 4                  # encoding: [0xfc,0x46,0x20,0x44]
+# CHECK-LE: dmulq 2, 6, 4                  # encoding: [0x44,0x20,0x46,0xfc]
+            dmulq 2, 6, 4
+# CHECK-BE: dmulq. 2, 6, 4                 # encoding: [0xfc,0x46,0x20,0x45]
+# CHECK-LE: dmulq. 2, 6, 4                 # encoding: [0x45,0x20,0x46,0xfc]
+            dmulq. 2, 6, 4
+# CHECK-BE: ddiv 2, 3, 4                   # encoding: [0xec,0x43,0x24,0x44]
+# CHECK-LE: ddiv 2, 3, 4                   # encoding: [0x44,0x24,0x43,0xec]
+            ddiv 2, 3, 4
+# CHECK-BE: ddiv. 2, 3, 4                  # encoding: [0xec,0x43,0x24,0x45]
+# CHECK-LE: ddiv. 2, 3, 4                  # encoding: [0x45,0x24,0x43,0xec]
+            ddiv. 2, 3, 4
+# CHECK-BE: ddivq 2, 6, 4                  # encoding: [0xfc,0x46,0x24,0x44]
+# CHECK-LE: ddivq 2, 6, 4                  # encoding: [0x44,0x24,0x46,0xfc]
+            ddivq 2, 6, 4
+# CHECK-BE: ddivq. 2, 6, 4                 # encoding: [0xfc,0x46,0x24,0x45]
+# CHECK-LE: ddivq. 2, 6, 4                 # encoding: [0x45,0x24,0x46,0xfc]
+            ddivq. 2, 6, 4