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Differential D150612

AMDGPU: Expand casted f16 fmed3 pattern to fmin/fmax on gfx8
ClosedPublic

Authored by arsenm on May 15 2023, 1:59 PM.

Details

Reviewers
foad
Pierre-vh
rampitec
b-sumner
Group Reviewers
Restricted Project
Summary

If we have legal f16 instructions but no f16 med3, we can save
one instruction by expanding out the min/max sequence compared
to casting to f32 and casting back.

Diff Detail

Event Timeline

arsenm created this revision.May 15 2023, 1:59 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 15 2023, 1:59 PM
Herald added subscribers: StephenFan, kerbowa, hiraditya and 5 others. · View Herald Transcript
arsenm requested review of this revision.May 15 2023, 1:59 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 15 2023, 1:59 PM
Herald added a subscriber: wdng. · View Herald Transcript
arsenm added a parent revision: D150195: GlobalISel: Move fconstant matching into tablegen.May 15 2023, 1:59 PM
Harbormaster completed remote builds in B232114: Diff 522333.May 15 2023, 2:00 PM
Pierre-vh added inline comments.May 16 2023, 12:16 AM
llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
391–393
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
5891

nit: also add a complementary comment in the tablegen file (e.g. TODO: match intrinsics, currently we replace the intrinsic in LegalizerInfo to work around it), that way if we add intrinsic matching later, we don't forget to remove this workaround when updating the pattern

llvm/lib/Target/AMDGPU/SIISelLowering.cpp
11139

Here you check for f32 explicitly, but I think in the GISel combine you don't enforce it, why?

arsenm added inline comments.May 16 2023, 12:48 AM
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
11139

It doesn't matter much either way since there's no f64 or vector versions of fmed3.

arsenm updated this revision to Diff 523721.May 19 2023, 3:33 AM
arsenm marked 2 inline comments as done.

Address comments

Harbormaster completed remote builds in B233140: Diff 523721.May 19 2023, 3:33 AM
Pierre-vh added a comment.May 22 2023, 7:01 AM

LGTM, I don't see any regressions but I can't comment on the codegen change, so if you want a second opinion on the codegen logic then I would ask another reviewer :)

Pierre-vh accepted this revision as: Pierre-vh.May 22 2023, 7:01 AM
This revision is now accepted and ready to land.May 22 2023, 7:01 AM
arsenm closed this revision.May 23 2023, 12:50 AM

2f5a116cf70e4717bce20c3d9d4c7a41aa6d89ec

foad added a comment.May 23 2023, 1:16 AM

This is causing:

FAIL: LLVM :: CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir (1 of 1)
******************** TEST 'LLVM :: CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir' FAILED ********************
Script:
--
: 'RUN: at line 2';   /home/jayfoad2/llvm-release/bin/llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir -o - | /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
--
Exit Code: 1

Command Output (stderr):
--
+ : 'RUN: at line 2'
+ /home/jayfoad2/llvm-release/bin/llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir -o -
+ /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
/home/jayfoad2/git/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir:23:16: error: CHECK-NEXT: expected string not found in input
 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]]
               ^
<stdin>:151:30: note: scanning from here
 %3:vgpr(s32) = G_FMUL %0, %2
                             ^
<stdin>:151:30: note: with "FMUL" equal to "%3"
 %3:vgpr(s32) = G_FMUL %0, %2
                             ^
<stdin>:154:2: note: possible intended match here
 %6:vgpr(s32) = COPY %5(s32)
 ^
/home/jayfoad2/git/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir:58:16: error: CHECK-NEXT: expected string not found in input
 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]]
               ^
<stdin>:269:30: note: scanning from here
 %4:vgpr(s16) = G_FMUL %1, %3
                             ^
<stdin>:269:30: note: with "FMUL" equal to "%4"
 %4:vgpr(s16) = G_FMUL %1, %3
                             ^
<stdin>:272:2: note: possible intended match here
 %7:vgpr(s16) = COPY %6(s16)
 ^
/home/jayfoad2/git/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir:96:16: error: CHECK-NEXT: expected string not found in input
 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMINNUM_IEEE]]
               ^
<stdin>:387:38: note: scanning from here
 %4:vgpr(s32) = G_FMINNUM_IEEE %2, %3
                                     ^
<stdin>:387:38: note: with "FMINNUM_IEEE" equal to "%4"
 %4:vgpr(s32) = G_FMINNUM_IEEE %2, %3
                                     ^
<stdin>:390:2: note: possible intended match here
 %7:vgpr(s32) = COPY %6(s32)
 ^
/home/jayfoad2/git/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir:131:16: error: CHECK-NEXT: expected string not found in input
 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]]
               ^
<stdin>:502:30: note: scanning from here
 %3:vgpr(s32) = G_FMUL %0, %2
                             ^
<stdin>:502:30: note: with "FMUL" equal to "%3"
 %3:vgpr(s32) = G_FMUL %0, %2
                             ^
<stdin>:505:2: note: possible intended match here
 %6:vgpr(s32) = COPY %5(s32)
 ^
/home/jayfoad2/git/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir:245:16: error: CHECK-NEXT: expected string not found in input
 ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]]
               ^
<stdin>:849:30: note: scanning from here
 %3:vgpr(s32) = G_FMUL %0, %2
                             ^
<stdin>:849:30: note: with "FMUL" equal to "%3"
 %3:vgpr(s32) = G_FMUL %0, %2
                             ^
<stdin>:852:2: note: possible intended match here
 %6:vgpr(s32) = COPY %5(s32)
 ^

Input file: <stdin>
Check file: /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir

-dump-input=help explains the following input dump.

Input was:
<<<<<<
            .
            .
            .
          111:  waveLimiter: false 
          112:  hasSpilledSGPRs: false 
          113:  hasSpilledVGPRs: false 
          114:  scratchRSrcReg: '$private_rsrc_reg' 
          115:  frameOffsetReg: '$fp_reg' 
          116:  stackPtrOffsetReg: '$sp_reg' 
          117:  bytesInStackArgArea: 0 
          118:  returnsVoid: true 
          119:  argumentInfo: 
          120:  privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 
          121:  dispatchPtr: { reg: '$sgpr4_sgpr5' } 
          122:  queuePtr: { reg: '$sgpr6_sgpr7' } 
          123:  dispatchID: { reg: '$sgpr10_sgpr11' } 
          124:  workGroupIDX: { reg: '$sgpr12' } 
          125:  workGroupIDY: { reg: '$sgpr13' } 
          126:  workGroupIDZ: { reg: '$sgpr14' } 
          127:  LDSKernelId: { reg: '$sgpr15' } 
          128:  implicitArgPtr: { reg: '$sgpr8_sgpr9' } 
          129:  workItemIDX: { reg: '$vgpr31', mask: 1023 } 
          130:  workItemIDY: { reg: '$vgpr31', mask: 1047552 } 
          131:  workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } 
          132:  psInputAddr: 0 
          133:  psInputEnable: 0 
          134:  mode: 
          135:  ieee: true 
          136:  dx10-clamp: true 
          137:  fp32-input-denormals: true 
          138:  fp32-output-denormals: true 
          139:  fp64-fp16-input-denormals: true 
          140:  fp64-fp16-output-denormals: true 
          141:  highBitsOf32BitAddress: 0 
          142:  occupancy: 16 
          143:  vgprForAGPRCopy: '' 
          144: body: | 
          145:  bb.0: 
          146:  liveins: $vgpr0 
          147:   
          148:  %0:vgpr(s32) = COPY $vgpr0 
          149:  %1:sgpr(s32) = G_FCONSTANT float 2.000000e+00 
          150:  %2:vgpr(s32) = COPY %1(s32) 
          151:  %3:vgpr(s32) = G_FMUL %0, %2 
next:23'0                                   X error: no match found
next:23'1                                     with "FMUL" equal to "%3"
          152:  %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00 
next:23'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          153:  %5:sgpr(s32) = G_FCONSTANT float 0.000000e+00 
next:23'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          154:  %6:vgpr(s32) = COPY %5(s32) 
next:23'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
next:23'2       ?                            possible intended match
          155:  %7:vgpr(s32) = COPY %4(s32) 
next:23'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          156:  %8:vgpr(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3(s32), %6(s32), %7(s32) 
next:23'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          157:  $vgpr0 = COPY %8(s32) 
next:23'0      ~~~~~~~~~~~~~~~~~~~~~~~
          158:  
next:23'0      ~
          159: ... 
next:23'0      ~~~~
          160: --- 
next:23'0      ~~~~
          161: name: test_fmed3_f16_known_nnan_ieee_false 
next:23'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          162: alignment: 1 
          163: exposesReturnsTwice: false 
          164: legalized: true 
          165: regBankSelected: true 
          166: selected: false 
          167: failedISel: false 
          168: tracksRegLiveness: true 
          169: hasWinCFI: false 
          170: callsEHReturn: false 
          171: callsUnwindInit: false 
          172: hasEHCatchret: false 
          173: hasEHScopes: false 
          174: hasEHFunclets: false 
          175: isOutlined: false 
          176: debugInstrRef: false 
          177: failsVerification: false 
          178: tracksDebugUserValues: false 
          179: registers: 
          180:  - { id: 0, class: vgpr, preferred-register: '' } 
          181:  - { id: 1, class: vgpr, preferred-register: '' } 
          182:  - { id: 2, class: sgpr, preferred-register: '' } 
          183:  - { id: 3, class: vgpr, preferred-register: '' } 
          184:  - { id: 4, class: vgpr, preferred-register: '' } 
          185:  - { id: 5, class: sgpr, preferred-register: '' } 
          186:  - { id: 6, class: sgpr, preferred-register: '' } 
          187:  - { id: 7, class: vgpr, preferred-register: '' } 
          188:  - { id: 8, class: vgpr, preferred-register: '' } 
          189:  - { id: 9, class: vgpr, preferred-register: '' } 
          190:  - { id: 10, class: vgpr, preferred-register: '' } 
          191: liveins: [] 
          192: frameInfo: 
          193:  isFrameAddressTaken: false 
          194:  isReturnAddressTaken: false 
            .
            .
            .
          229:  hasSpilledSGPRs: false 
          230:  hasSpilledVGPRs: false 
          231:  scratchRSrcReg: '$private_rsrc_reg' 
          232:  frameOffsetReg: '$fp_reg' 
          233:  stackPtrOffsetReg: '$sp_reg' 
          234:  bytesInStackArgArea: 0 
          235:  returnsVoid: true 
          236:  argumentInfo: 
          237:  privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 
          238:  dispatchPtr: { reg: '$sgpr4_sgpr5' } 
          239:  queuePtr: { reg: '$sgpr6_sgpr7' } 
          240:  dispatchID: { reg: '$sgpr10_sgpr11' } 
          241:  workGroupIDX: { reg: '$sgpr12' } 
          242:  workGroupIDY: { reg: '$sgpr13' } 
          243:  workGroupIDZ: { reg: '$sgpr14' } 
          244:  LDSKernelId: { reg: '$sgpr15' } 
          245:  implicitArgPtr: { reg: '$sgpr8_sgpr9' } 
          246:  workItemIDX: { reg: '$vgpr31', mask: 1023 } 
          247:  workItemIDY: { reg: '$vgpr31', mask: 1047552 } 
          248:  workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } 
          249:  psInputAddr: 0 
          250:  psInputEnable: 0 
          251:  mode: 
          252:  ieee: false 
          253:  dx10-clamp: true 
          254:  fp32-input-denormals: true 
          255:  fp32-output-denormals: true 
          256:  fp64-fp16-input-denormals: true 
          257:  fp64-fp16-output-denormals: true 
          258:  highBitsOf32BitAddress: 0 
          259:  occupancy: 16 
          260:  vgprForAGPRCopy: '' 
          261: body: | 
          262:  bb.0: 
          263:  liveins: $vgpr0 
          264:   
          265:  %0:vgpr(s32) = COPY $vgpr0 
          266:  %1:vgpr(s16) = G_TRUNC %0(s32) 
          267:  %2:sgpr(s16) = G_FCONSTANT half 0xH4000 
          268:  %3:vgpr(s16) = COPY %2(s16) 
          269:  %4:vgpr(s16) = G_FMUL %1, %3 
next:58'0                                   X error: no match found
next:58'1                                     with "FMUL" equal to "%4"
          270:  %5:sgpr(s16) = G_FCONSTANT half 0xH3C00 
next:58'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          271:  %6:sgpr(s16) = G_FCONSTANT half 0xH0000 
next:58'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          272:  %7:vgpr(s16) = COPY %6(s16) 
next:58'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
next:58'2       ?                            possible intended match
          273:  %8:vgpr(s16) = COPY %5(s16) 
next:58'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          274:  %9:vgpr(s16) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %4(s16), %7(s16), %8(s16) 
next:58'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          275:  %10:vgpr(s32) = G_ANYEXT %9(s16) 
next:58'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          276:  $vgpr0 = COPY %10(s32) 
next:58'0      ~~~~~~~~~~~~~~~~~~~~~~~~
          277:  
next:58'0      ~
          278: ... 
next:58'0      ~~~~
          279: --- 
next:58'0      ~~~~
          280: name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true 
next:58'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          281: alignment: 1 
          282: exposesReturnsTwice: false 
          283: legalized: true 
          284: regBankSelected: true 
          285: selected: false 
          286: failedISel: false 
          287: tracksRegLiveness: true 
          288: hasWinCFI: false 
          289: callsEHReturn: false 
          290: callsUnwindInit: false 
          291: hasEHCatchret: false 
          292: hasEHScopes: false 
          293: hasEHFunclets: false 
          294: isOutlined: false 
          295: debugInstrRef: false 
          296: failsVerification: false 
          297: tracksDebugUserValues: false 
          298: registers: 
          299:  - { id: 0, class: vgpr, preferred-register: '' } 
          300:  - { id: 1, class: sgpr, preferred-register: '' } 
          301:  - { id: 2, class: vgpr, preferred-register: '' } 
          302:  - { id: 3, class: vgpr, preferred-register: '' } 
          303:  - { id: 4, class: vgpr, preferred-register: '' } 
          304:  - { id: 5, class: sgpr, preferred-register: '' } 
          305:  - { id: 6, class: sgpr, preferred-register: '' } 
          306:  - { id: 7, class: vgpr, preferred-register: '' } 
          307:  - { id: 8, class: vgpr, preferred-register: '' } 
          308:  - { id: 9, class: vgpr, preferred-register: '' } 
          309: liveins: [] 
          310: frameInfo: 
          311:  isFrameAddressTaken: false 
          312:  isReturnAddressTaken: false 
            .
            .
            .
          347:  hasSpilledSGPRs: false 
          348:  hasSpilledVGPRs: false 
          349:  scratchRSrcReg: '$private_rsrc_reg' 
          350:  frameOffsetReg: '$fp_reg' 
          351:  stackPtrOffsetReg: '$sp_reg' 
          352:  bytesInStackArgArea: 0 
          353:  returnsVoid: true 
          354:  argumentInfo: 
          355:  privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 
          356:  dispatchPtr: { reg: '$sgpr4_sgpr5' } 
          357:  queuePtr: { reg: '$sgpr6_sgpr7' } 
          358:  dispatchID: { reg: '$sgpr10_sgpr11' } 
          359:  workGroupIDX: { reg: '$sgpr12' } 
          360:  workGroupIDY: { reg: '$sgpr13' } 
          361:  workGroupIDZ: { reg: '$sgpr14' } 
          362:  LDSKernelId: { reg: '$sgpr15' } 
          363:  implicitArgPtr: { reg: '$sgpr8_sgpr9' } 
          364:  workItemIDX: { reg: '$vgpr31', mask: 1023 } 
          365:  workItemIDY: { reg: '$vgpr31', mask: 1047552 } 
          366:  workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } 
          367:  psInputAddr: 0 
          368:  psInputEnable: 0 
          369:  mode: 
          370:  ieee: true 
          371:  dx10-clamp: true 
          372:  fp32-input-denormals: true 
          373:  fp32-output-denormals: true 
          374:  fp64-fp16-input-denormals: true 
          375:  fp64-fp16-output-denormals: true 
          376:  highBitsOf32BitAddress: 0 
          377:  occupancy: 16 
          378:  vgprForAGPRCopy: '' 
          379: body: | 
          380:  bb.0: 
          381:  liveins: $vgpr0 
          382:   
          383:  %0:vgpr(s32) = COPY $vgpr0 
          384:  %1:sgpr(s32) = G_FCONSTANT float 1.000000e+01 
          385:  %2:vgpr(s32) = G_FCANONICALIZE %0 
          386:  %3:vgpr(s32) = COPY %1(s32) 
          387:  %4:vgpr(s32) = G_FMINNUM_IEEE %2, %3 
next:96'0                                           X error: no match found
next:96'1                                             with "FMINNUM_IEEE" equal to "%4"
          388:  %5:sgpr(s32) = G_FCONSTANT float 1.000000e+00 
next:96'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          389:  %6:sgpr(s32) = G_FCONSTANT float 0.000000e+00 
next:96'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          390:  %7:vgpr(s32) = COPY %6(s32) 
next:96'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
next:96'2       ?                            possible intended match
          391:  %8:vgpr(s32) = COPY %5(s32) 
next:96'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          392:  %9:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %4(s32), %7(s32), %8(s32) 
next:96'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          393:  $vgpr0 = COPY %9(s32) 
next:96'0      ~~~~~~~~~~~~~~~~~~~~~~~
          394:  
next:96'0      ~
          395: ... 
next:96'0      ~~~~
          396: --- 
next:96'0      ~~~~
          397: name: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true 
next:96'0      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          398: alignment: 1 
          399: exposesReturnsTwice: false 
          400: legalized: true 
          401: regBankSelected: true 
          402: selected: false 
          403: failedISel: false 
          404: tracksRegLiveness: true 
          405: hasWinCFI: false 
          406: callsEHReturn: false 
          407: callsUnwindInit: false 
          408: hasEHCatchret: false 
          409: hasEHScopes: false 
          410: hasEHFunclets: false 
          411: isOutlined: false 
          412: debugInstrRef: false 
          413: failsVerification: false 
          414: tracksDebugUserValues: false 
          415: registers: 
          416:  - { id: 0, class: vgpr, preferred-register: '' } 
          417:  - { id: 1, class: sgpr, preferred-register: '' } 
          418:  - { id: 2, class: vgpr, preferred-register: '' } 
          419:  - { id: 3, class: vgpr, preferred-register: '' } 
          420:  - { id: 4, class: sgpr, preferred-register: '' } 
          421:  - { id: 5, class: sgpr, preferred-register: '' } 
          422:  - { id: 6, class: vgpr, preferred-register: '' } 
          423:  - { id: 7, class: vgpr, preferred-register: '' } 
          424:  - { id: 8, class: vgpr, preferred-register: '' } 
          425: liveins: [] 
          426: frameInfo: 
          427:  isFrameAddressTaken: false 
          428:  isReturnAddressTaken: false 
          429:  hasStackMap: false 
          430:  hasPatchPoint: false 
            .
            .
            .
          462:  waveLimiter: false 
          463:  hasSpilledSGPRs: false 
          464:  hasSpilledVGPRs: false 
          465:  scratchRSrcReg: '$private_rsrc_reg' 
          466:  frameOffsetReg: '$fp_reg' 
          467:  stackPtrOffsetReg: '$sp_reg' 
          468:  bytesInStackArgArea: 0 
          469:  returnsVoid: true 
          470:  argumentInfo: 
          471:  privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 
          472:  dispatchPtr: { reg: '$sgpr4_sgpr5' } 
          473:  queuePtr: { reg: '$sgpr6_sgpr7' } 
          474:  dispatchID: { reg: '$sgpr10_sgpr11' } 
          475:  workGroupIDX: { reg: '$sgpr12' } 
          476:  workGroupIDY: { reg: '$sgpr13' } 
          477:  workGroupIDZ: { reg: '$sgpr14' } 
          478:  LDSKernelId: { reg: '$sgpr15' } 
          479:  implicitArgPtr: { reg: '$sgpr8_sgpr9' } 
          480:  workItemIDX: { reg: '$vgpr31', mask: 1023 } 
          481:  workItemIDY: { reg: '$vgpr31', mask: 1047552 } 
          482:  workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } 
          483:  psInputAddr: 0 
          484:  psInputEnable: 0 
          485:  mode: 
          486:  ieee: true 
          487:  dx10-clamp: true 
          488:  fp32-input-denormals: true 
          489:  fp32-output-denormals: true 
          490:  fp64-fp16-input-denormals: true 
          491:  fp64-fp16-output-denormals: true 
          492:  highBitsOf32BitAddress: 0 
          493:  occupancy: 16 
          494:  vgprForAGPRCopy: '' 
          495: body: | 
          496:  bb.0: 
          497:  liveins: $vgpr0 
          498:   
          499:  %0:vgpr(s32) = COPY $vgpr0 
          500:  %1:sgpr(s32) = G_FCONSTANT float 2.000000e+00 
          501:  %2:vgpr(s32) = COPY %1(s32) 
          502:  %3:vgpr(s32) = G_FMUL %0, %2 
next:131'0                                  X error: no match found
next:131'1                                    with "FMUL" equal to "%3"
          503:  %4:sgpr(s32) = G_FCONSTANT float 0.000000e+00 
next:131'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          504:  %5:sgpr(s32) = G_FCONSTANT float 1.000000e+00 
next:131'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          505:  %6:vgpr(s32) = COPY %5(s32) 
next:131'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
next:131'2      ?                            possible intended match
          506:  %7:vgpr(s32) = COPY %4(s32) 
next:131'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          507:  %8:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3(s32), %6(s32), %7(s32) 
next:131'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          508:  $vgpr0 = COPY %8(s32) 
next:131'0     ~~~~~~~~~~~~~~~~~~~~~~~
          509:  
next:131'0     ~
          510: ... 
next:131'0     ~~~~
          511: --- 
next:131'0     ~~~~
          512: name: test_fmed3_f32_maybe_NaN_ieee_false 
next:131'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          513: alignment: 1 
          514: exposesReturnsTwice: false 
          515: legalized: true 
          516: regBankSelected: true 
          517: selected: false 
          518: failedISel: false 
          519: tracksRegLiveness: true 
          520: hasWinCFI: false 
          521: callsEHReturn: false 
          522: callsUnwindInit: false 
          523: hasEHCatchret: false 
          524: hasEHScopes: false 
          525: hasEHFunclets: false 
          526: isOutlined: false 
          527: debugInstrRef: false 
          528: failsVerification: false 
          529: tracksDebugUserValues: false 
          530: registers: 
          531:  - { id: 0, class: vgpr, preferred-register: '' } 
          532:  - { id: 1, class: sgpr, preferred-register: '' } 
          533:  - { id: 2, class: vgpr, preferred-register: '' } 
          534:  - { id: 3, class: vgpr, preferred-register: '' } 
          535:  - { id: 4, class: sgpr, preferred-register: '' } 
          536:  - { id: 5, class: sgpr, preferred-register: '' } 
          537:  - { id: 6, class: vgpr, preferred-register: '' } 
          538:  - { id: 7, class: vgpr, preferred-register: '' } 
          539:  - { id: 8, class: vgpr, preferred-register: '' } 
          540: liveins: [] 
          541: frameInfo: 
          542:  isFrameAddressTaken: false 
          543:  isReturnAddressTaken: false 
          544:  hasStackMap: false 
          545:  hasPatchPoint: false 
            .
            .
            .
          809:  waveLimiter: false 
          810:  hasSpilledSGPRs: false 
          811:  hasSpilledVGPRs: false 
          812:  scratchRSrcReg: '$private_rsrc_reg' 
          813:  frameOffsetReg: '$fp_reg' 
          814:  stackPtrOffsetReg: '$sp_reg' 
          815:  bytesInStackArgArea: 0 
          816:  returnsVoid: true 
          817:  argumentInfo: 
          818:  privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } 
          819:  dispatchPtr: { reg: '$sgpr4_sgpr5' } 
          820:  queuePtr: { reg: '$sgpr6_sgpr7' } 
          821:  dispatchID: { reg: '$sgpr10_sgpr11' } 
          822:  workGroupIDX: { reg: '$sgpr12' } 
          823:  workGroupIDY: { reg: '$sgpr13' } 
          824:  workGroupIDZ: { reg: '$sgpr14' } 
          825:  LDSKernelId: { reg: '$sgpr15' } 
          826:  implicitArgPtr: { reg: '$sgpr8_sgpr9' } 
          827:  workItemIDX: { reg: '$vgpr31', mask: 1023 } 
          828:  workItemIDY: { reg: '$vgpr31', mask: 1047552 } 
          829:  workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } 
          830:  psInputAddr: 0 
          831:  psInputEnable: 0 
          832:  mode: 
          833:  ieee: true 
          834:  dx10-clamp: true 
          835:  fp32-input-denormals: true 
          836:  fp32-output-denormals: true 
          837:  fp64-fp16-input-denormals: true 
          838:  fp64-fp16-output-denormals: true 
          839:  highBitsOf32BitAddress: 0 
          840:  occupancy: 16 
          841:  vgprForAGPRCopy: '' 
          842: body: | 
          843:  bb.0: 
          844:  liveins: $vgpr0 
          845:   
          846:  %0:vgpr(s32) = COPY $vgpr0 
          847:  %1:sgpr(s32) = G_FCONSTANT float 2.000000e+00 
          848:  %2:vgpr(s32) = COPY %1(s32) 
          849:  %3:vgpr(s32) = G_FMUL %0, %2 
next:245'0                                  X error: no match found
next:245'1                                    with "FMUL" equal to "%3"
          850:  %4:sgpr(s32) = G_FCONSTANT float 1.000000e+00 
next:245'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          851:  %5:sgpr(s32) = G_FCONSTANT float 0.000000e+00 
next:245'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          852:  %6:vgpr(s32) = COPY %5(s32) 
next:245'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
next:245'2      ?                            possible intended match
          853:  %7:vgpr(s32) = COPY %4(s32) 
next:245'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          854:  %8:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3(s32), %6(s32), %7(s32) 
next:245'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          855:  $vgpr0 = COPY %8(s32) 
next:245'0     ~~~~~~~~~~~~~~~~~~~~~~~
          856:  
next:245'0     ~
          857: ... 
next:245'0     ~~~~
>>>>>>

--

********************
********************
Failed Tests (1):
  LLVM :: CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines
28 lines
5 lines
53 lines
11 lines
1 line
1 line
70 lines
test/
CodeGen/
AMDGPU/
405 lines

Diff 523721

llvm/lib/Target/AMDGPU/AMDGPU.td

Show First 20 Lines • Show All 1,709 Lines • ▼ Show 20 Lines
def HasTrue16BitInsts : Predicate<"Subtarget->hasTrue16BitInsts()">, def HasTrue16BitInsts : Predicate<"Subtarget->hasTrue16BitInsts()">,
AssemblerPredicate<(all_of FeatureTrue16BitInsts)>; AssemblerPredicate<(all_of FeatureTrue16BitInsts)>;
def NotHasTrue16BitInsts : Predicate<"!Subtarget->hasTrue16BitInsts()">; def NotHasTrue16BitInsts : Predicate<"!Subtarget->hasTrue16BitInsts()">;
def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">, def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
AssemblerPredicate<(all_of FeatureVOP3P)>; AssemblerPredicate<(all_of FeatureVOP3P)>;
def NotHasMed3_16 : Predicate<"!Subtarget->hasMed3_16()">;
def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">; def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">; def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
def HasFminFmaxLegacy : Predicate<"Subtarget->hasFminFmaxLegacy()">; def HasFminFmaxLegacy : Predicate<"Subtarget->hasFminFmaxLegacy()">;
def HasSDWA : Predicate<"Subtarget->hasSDWA()">, def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>; AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
▲ Show 20 Lines • Show All 183 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
def sign_exension_in_reg_matchdata : GIDefMatchData<"MachineInstr *">; def sign_exension_in_reg_matchdata : GIDefMatchData<"MachineInstr *">;
def sign_extension_in_reg : GICombineRule< def sign_extension_in_reg : GICombineRule<
(defs root:$sign_inreg, sign_exension_in_reg_matchdata:$matchinfo), (defs root:$sign_inreg, sign_exension_in_reg_matchdata:$matchinfo),
(match (wip_match_opcode G_SEXT_INREG):$sign_inreg, (match (wip_match_opcode G_SEXT_INREG):$sign_inreg,
[{ return PostLegalizerHelper.matchCombineSignExtendInReg(*${sign_inreg}, ${matchinfo}); }]), [{ return PostLegalizerHelper.matchCombineSignExtendInReg(*${sign_inreg}, ${matchinfo}); }]),
(apply [{ PostLegalizerHelper.applyCombineSignExtendInReg(*${sign_inreg}, ${matchinfo}); }])>; (apply [{ PostLegalizerHelper.applyCombineSignExtendInReg(*${sign_inreg}, ${matchinfo}); }])>;
// Combines which should only apply on SI/VI
let Predicates = [Has16BitInsts, NotHasMed3_16] in {
// For gfx8, expand f16-fmed3-as-f32 into a min/max f16 sequence. This
// saves one instruction compared to the promotion.
//
// FIXME: Should have ComplexPattern like in/out matchers
//
// FIXME: We should be able to match either G_AMDGPU_FMED3 or
// G_INTRINSIC @llvm.amdgcn.fmed3. Currently the legalizer will
// replace the intrinsic with G_AMDGPU_FMED3 since we can't write a
// pattern to match it.
def expand_promoted_fmed3 : GICombineRule<
(defs root:$fptrunc_dst),
(match (G_FPTRUNC $fptrunc_dst, $fmed3_dst):$fptrunc,
(G_AMDGPU_FMED3 $fmed3_dst, $src0, $src1, $src2),
[{ return Helper.matchExpandPromotedF16FMed3(*${fptrunc}, ${src0}.getReg(), ${src1}.getReg(), ${src2}.getReg()); }]),
(apply [{ Helper.applyExpandPromotedF16FMed3(*${fptrunc}, ${src0}.getReg(), ${src1}.getReg(), ${src2}.getReg()); }])
>;
} // End Predicates = [NotHasMed3_16]
// Combines which should only apply on SI/CI
def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>; def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>;
// Combines which should only apply on VI
def gfx8_combines : GICombineGroup<[expand_promoted_fmed3]>;
def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper< def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<
"AMDGPUGenPreLegalizerCombinerHelper", "AMDGPUGenPreLegalizerCombinerHelper",
[all_combines, clamp_i64_to_i16, foldable_fneg]> { [all_combines, clamp_i64_to_i16, foldable_fneg]> {
let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule"; let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule";
let StateClass = "AMDGPUPreLegalizerCombinerHelperState"; let StateClass = "AMDGPUPreLegalizerCombinerHelperState";
let AdditionalArguments = []; let AdditionalArguments = [];
} }
def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper< def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper<
"AMDGPUGenPostLegalizerCombinerHelper", "AMDGPUGenPostLegalizerCombinerHelper",
[all_combines, gfx6gfx7_combines, [all_combines, gfx6gfx7_combines, gfx8_combines,
uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg, uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
rcp_sqrt_to_rsq, sign_extension_in_reg]> { rcp_sqrt_to_rsq, sign_extension_in_reg]> {
let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule"; let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule";
let StateClass = "AMDGPUPostLegalizerCombinerHelperState"; let StateClass = "AMDGPUPostLegalizerCombinerHelperState";
let AdditionalArguments = []; let AdditionalArguments = [];
} }
def AMDGPURegBankCombinerHelper : GICombinerHelper< def AMDGPURegBankCombinerHelper : GICombinerHelper<
"AMDGPUGenRegBankCombinerHelper", "AMDGPUGenRegBankCombinerHelper",
[unmerge_merge, unmerge_cst, unmerge_undef, [unmerge_merge, unmerge_cst, unmerge_undef,
zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain, zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain,
fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp]> { fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp]> {
let DisableRuleOption = "amdgpuregbankcombiner-disable-rule"; let DisableRuleOption = "amdgpuregbankcombiner-disable-rule";
let StateClass = "AMDGPURegBankCombinerHelperState"; let StateClass = "AMDGPURegBankCombinerHelperState";
let AdditionalArguments = []; let AdditionalArguments = [];
} }

llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h

Show All 17 Lines
using namespace llvm; using namespace llvm;
class AMDGPUCombinerHelper : public CombinerHelper { class AMDGPUCombinerHelper : public CombinerHelper {
public: public:
using CombinerHelper::CombinerHelper; using CombinerHelper::CombinerHelper;
bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo); bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo); void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
bool matchExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
Register Src1, Register Src2);
void applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
Register Src1, Register Src2);
}; };

llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp

Show First 20 Lines • Show All 374 Lines • ▼ Show 20 Lines if (MRI.hasOneNonDBGUse(MatchInfoDst)) {
// Recreate non negated value for other uses of old MatchInfoDst // Recreate non negated value for other uses of old MatchInfoDst
auto NextInst = ++MatchInfo->getIterator(); auto NextInst = ++MatchInfo->getIterator();
Builder.setInstrAndDebugLoc(*NextInst); Builder.setInstrAndDebugLoc(*NextInst);
Builder.buildFNeg(MatchInfoDst, NegatedMatchInfo, MI.getFlags()); Builder.buildFNeg(MatchInfoDst, NegatedMatchInfo, MI.getFlags());
} }
MI.eraseFromParent(); MI.eraseFromParent();
} }
// TODO: Should return converted value / extension source and avoid introducing
// intermediate fptruncs in the apply function.
static bool isFPExtFromF16OrConst(const MachineRegisterInfo &MRI,
Register Reg) {
const MachineInstr *Def = MRI.getVRegDef(Reg);
if (Def->getOpcode() == TargetOpcode::G_FPEXT) {
Register SrcReg = Def->getOperand(1).getReg();
return MRI.getType(SrcReg) == LLT::scalar(16);
}
Pierre-vhUnsubmitted
Done
ReplyInline Actions
Register SrcReg = Def->getOperand(1).getReg();
- if (MRI.getType(SrcReg) != LLT::scalar(16))
- return false;
- return true;
+ return MRI.getType(SrcReg) == LLT::scalar(16);
}
if (Def->getOpcode() == TargetOpcode::G_FCONSTANT) {
Pierre-vh:
if (Def->getOpcode() == TargetOpcode::G_FCONSTANT) {
APFloat Val = Def->getOperand(1).getFPImm()->getValueAPF();
bool LosesInfo = true;
Val.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &LosesInfo);
return !LosesInfo;
}
return false;
}
bool AMDGPUCombinerHelper::matchExpandPromotedF16FMed3(MachineInstr &MI,
Register Src0,
Register Src1,
Register Src2) {
assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC);
Register SrcReg = MI.getOperand(1).getReg();
if (!MRI.hasOneNonDBGUse(SrcReg) || MRI.getType(SrcReg) != LLT::scalar(32))
return false;
return isFPExtFromF16OrConst(MRI, Src0) && isFPExtFromF16OrConst(MRI, Src1) &&
isFPExtFromF16OrConst(MRI, Src2);
}
void AMDGPUCombinerHelper::applyExpandPromotedF16FMed3(MachineInstr &MI,
Register Src0,
Register Src1,
Register Src2) {
Builder.setInstrAndDebugLoc(MI);
// We expect fptrunc (fpext x) to fold out, and to constant fold any constant
// sources.
Src0 = Builder.buildFPTrunc(LLT::scalar(16), Src0).getReg(0);
Src1 = Builder.buildFPTrunc(LLT::scalar(16), Src1).getReg(0);
Src2 = Builder.buildFPTrunc(LLT::scalar(16), Src2).getReg(0);
LLT Ty = MRI.getType(Src0);
auto A1 = Builder.buildFMinNumIEEE(Ty, Src0, Src1);
auto B1 = Builder.buildFMaxNumIEEE(Ty, Src0, Src1);
auto C1 = Builder.buildFMaxNumIEEE(Ty, A1, Src2);
Builder.buildFMinNumIEEE(MI.getOperand(0), B1, C1);
MI.eraseFromParent();
}

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 5,879 Lines • ▼ Show 20 Linesbool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
case Intrinsic::amdgcn_rsq_clamp: case Intrinsic::amdgcn_rsq_clamp:
return legalizeRsqClampIntrinsic(MI, MRI, B); return legalizeRsqClampIntrinsic(MI, MRI, B);
case Intrinsic::amdgcn_ds_fadd: case Intrinsic::amdgcn_ds_fadd:
case Intrinsic::amdgcn_ds_fmin: case Intrinsic::amdgcn_ds_fmin:
case Intrinsic::amdgcn_ds_fmax: case Intrinsic::amdgcn_ds_fmax:
return legalizeDSAtomicFPIntrinsic(Helper, MI, IntrID); return legalizeDSAtomicFPIntrinsic(Helper, MI, IntrID);
case Intrinsic::amdgcn_image_bvh_intersect_ray: case Intrinsic::amdgcn_image_bvh_intersect_ray:
return legalizeBVHIntrinsic(MI, B); return legalizeBVHIntrinsic(MI, B);
case Intrinsic::amdgcn_fmed3: {
GISelChangeObserver &Observer = Helper.Observer;
// FIXME: This is to workaround the inability of tablegen match combiners to
Pierre-vhUnsubmitted
Done
ReplyInline Actions

nit: also add a complementary comment in the tablegen file (e.g. TODO: match intrinsics, currently we replace the intrinsic in LegalizerInfo to work around it), that way if we add intrinsic matching later, we don't forget to remove this workaround when updating the pattern

Pierre-vh: nit: also add a complementary comment in the tablegen file (e.g. TODO: match intrinsics…
// match intrinsics in patterns.
Observer.changingInstr(MI);
MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_FMED3));
MI.removeOperand(1);
Observer.changedInstr(MI);
return true;
}
default: { default: {
if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr = if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
AMDGPU::getImageDimIntrinsicInfo(IntrID)) AMDGPU::getImageDimIntrinsicInfo(IntrID))
return legalizeImageIntrinsic(MI, B, Helper.Observer, ImageDimIntr); return legalizeImageIntrinsic(MI, B, Helper.Observer, ImageDimIntr);
return true; return true;
} }
} }
return true; return true;
} }

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 3,756 Lines • ▼ Show 20 LinesAMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_AMDGPU_FMAX_LEGACY: case AMDGPU::G_AMDGPU_FMAX_LEGACY:
case AMDGPU::G_AMDGPU_RCP_IFLAG: case AMDGPU::G_AMDGPU_RCP_IFLAG:
case AMDGPU::G_AMDGPU_CVT_F32_UBYTE0: case AMDGPU::G_AMDGPU_CVT_F32_UBYTE0:
case AMDGPU::G_AMDGPU_CVT_F32_UBYTE1: case AMDGPU::G_AMDGPU_CVT_F32_UBYTE1:
case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2: case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2:
case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3: case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3:
case AMDGPU::G_AMDGPU_CVT_PK_I16_I32: case AMDGPU::G_AMDGPU_CVT_PK_I16_I32:
case AMDGPU::G_AMDGPU_SMED3: case AMDGPU::G_AMDGPU_SMED3:
case AMDGPU::G_AMDGPU_FMED3:
return getDefaultMappingVOP(MI); return getDefaultMappingVOP(MI);
case AMDGPU::G_UMULH: case AMDGPU::G_UMULH:
case AMDGPU::G_SMULH: { case AMDGPU::G_SMULH: {
if (Subtarget.hasScalarMulHiInsts() && isSALUMapping(MI)) if (Subtarget.hasScalarMulHiInsts() && isSALUMapping(MI))
return getDefaultMappingSOP(MI); return getDefaultMappingSOP(MI);
return getDefaultMappingVOP(MI); return getDefaultMappingVOP(MI);
} }
case AMDGPU::G_AMDGPU_MAD_U64_U32: case AMDGPU::G_AMDGPU_MAD_U64_U32:
▲ Show 20 Lines • Show All 1,099 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIISelLowering.h

Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Linesprivate:
SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
SDValue Src, SDValue MinVal, SDValue MaxVal, SDValue Src, SDValue MinVal, SDValue MaxVal,
bool Signed) const; bool Signed) const;
SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
unsigned getFusedOpcode(const SelectionDAG &DAG, unsigned getFusedOpcode(const SelectionDAG &DAG,
const SDNode *N0, const SDNode *N1) const; const SDNode *N0, const SDNode *N1) const;
SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const; SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
▲ Show 20 Lines • Show All 345 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 766 Lines • ▼ Show 20 Lines setTargetDAGCombine({ISD::ADD,
ISD::FCANONICALIZE, ISD::FCANONICALIZE,
ISD::SCALAR_TO_VECTOR, ISD::SCALAR_TO_VECTOR,
ISD::ZERO_EXTEND, ISD::ZERO_EXTEND,
ISD::SIGN_EXTEND_INREG, ISD::SIGN_EXTEND_INREG,
ISD::EXTRACT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
ISD::INSERT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
ISD::FCOPYSIGN}); ISD::FCOPYSIGN});
if (Subtarget->has16BitInsts() && !Subtarget->hasMed3_16())
setTargetDAGCombine(ISD::FP_ROUND);
// All memory operations. Some folding on the pointer operand is done to help // All memory operations. Some folding on the pointer operand is done to help
// matching the constant offsets in the addressing modes. // matching the constant offsets in the addressing modes.
setTargetDAGCombine({ISD::LOAD, setTargetDAGCombine({ISD::LOAD,
ISD::STORE, ISD::STORE,
ISD::ATOMIC_LOAD, ISD::ATOMIC_LOAD,
ISD::ATOMIC_STORE, ISD::ATOMIC_STORE,
ISD::ATOMIC_CMP_SWAP, ISD::ATOMIC_CMP_SWAP,
ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
▲ Show 20 Lines • Show All 10,315 Lines • ▼ Show 20 Lines for (unsigned I = 0, E = VecVT.getVectorNumElements(); I < E; ++I) {
SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC); SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC);
SDValue V = DAG.getSelectCC(SL, Idx, IC, Ins, Elt, ISD::SETEQ); SDValue V = DAG.getSelectCC(SL, Idx, IC, Ins, Elt, ISD::SETEQ);
Ops.push_back(V); Ops.push_back(V);
} }
return DAG.getBuildVector(VecVT, SL, Ops); return DAG.getBuildVector(VecVT, SL, Ops);
} }
/// Return the source of an fp_extend from f16 to f32, or a converted FP
/// constant.
static SDValue strictFPExtFromF16(SelectionDAG &DAG, SDValue Src) {
if (Src.getOpcode() == ISD::FP_EXTEND &&
Src.getOperand(0).getValueType() == MVT::f16) {
return Src.getOperand(0);
}
if (auto *CFP = dyn_cast<ConstantFPSDNode>(Src)) {
APFloat Val = CFP->getValueAPF();
bool LosesInfo = true;
Val.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &LosesInfo);
if (!LosesInfo)
return DAG.getConstantFP(Val, SDLoc(Src), MVT::f16);
}
return SDValue();
}
SDValue SITargetLowering::performFPRoundCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
assert(Subtarget->has16BitInsts() && !Subtarget->hasMed3_16() &&
"combine only useful on gfx8");
SDValue TruncSrc = N->getOperand(0);
EVT VT = N->getValueType(0);
if (VT != MVT::f16)
return SDValue();
if (TruncSrc.getOpcode() != AMDGPUISD::FMED3 ||
TruncSrc.getValueType() != MVT::f32 || !TruncSrc.hasOneUse() ||
Pierre-vhUnsubmitted
Not Done
ReplyInline Actions

Here you check for f32 explicitly, but I think in the GISel combine you don't enforce it, why?

Pierre-vh: Here you check for `f32` explicitly, but I think in the GISel combine you don't enforce it, why?
arsenmAuthorUnsubmitted
Done
ReplyInline Actions

It doesn't matter much either way since there's no f64 or vector versions of fmed3.

arsenm: It doesn't matter much either way since there's no f64 or vector versions of fmed3.
!isNullConstant(N->getOperand(1)))
return SDValue();
SelectionDAG &DAG = DCI.DAG;
SDLoc SL(N);
// Optimize f16 fmed3 pattern performed on f32. On gfx8 there is no f16 fmed3,
// and expanding it with min/max saves 1 instruction vs. casting to f32 and
// casting back.
// fptrunc (f32 (fmed3 (fpext f16:a, fpext f16:b, fpext f16:c))) =>
// fmin(fmax(a, b), fmax(fmin(a, b), c))
SDValue A = strictFPExtFromF16(DAG, TruncSrc.getOperand(0));
if (!A)
return SDValue();
SDValue B = strictFPExtFromF16(DAG, TruncSrc.getOperand(1));
if (!B)
return SDValue();
SDValue C = strictFPExtFromF16(DAG, TruncSrc.getOperand(2));
if (!C)
return SDValue();
// This changes signaling nan behavior. If an input is a signaling nan, it
// would have been quieted by the fpext originally. We don't care because
// these are unconstrained ops. If we needed to insert quieting canonicalizes
// we would be worse off than just doing the promotion.
SDValue A1 = DAG.getNode(ISD::FMINNUM_IEEE, SL, VT, A, B);
SDValue B1 = DAG.getNode(ISD::FMAXNUM_IEEE, SL, VT, A, B);
SDValue C1 = DAG.getNode(ISD::FMAXNUM_IEEE, SL, VT, A1, C);
return DAG.getNode(ISD::FMINNUM_IEEE, SL, VT, B1, C1);
}
unsigned SITargetLowering::getFusedOpcode(const SelectionDAG &DAG, unsigned SITargetLowering::getFusedOpcode(const SelectionDAG &DAG,
const SDNode *N0, const SDNode *N0,
const SDNode *N1) const { const SDNode *N1) const {
EVT VT = N0->getValueType(0); EVT VT = N0->getValueType(0);
// Only do this if we are not trying to support denormals. v_mad_f32 does not // Only do this if we are not trying to support denormals. v_mad_f32 does not
// support denormals ever. // support denormals ever.
if (((VT == MVT::f32 && !hasFP32Denormals(DAG.getMachineFunction())) || if (((VT == MVT::f32 && !hasFP32Denormals(DAG.getMachineFunction())) ||
▲ Show 20 Lines • Show All 739 Lines • ▼ Show 20 Lines case ISD::SCALAR_TO_VECTOR: {
} }
break; break;
} }
case ISD::EXTRACT_VECTOR_ELT: case ISD::EXTRACT_VECTOR_ELT:
return performExtractVectorEltCombine(N, DCI); return performExtractVectorEltCombine(N, DCI);
case ISD::INSERT_VECTOR_ELT: case ISD::INSERT_VECTOR_ELT:
return performInsertVectorEltCombine(N, DCI); return performInsertVectorEltCombine(N, DCI);
case ISD::FP_ROUND:
return performFPRoundCombine(N, DCI);
case ISD::LOAD: { case ISD::LOAD: {
if (SDValue Widended = widenLoad(cast<LoadSDNode>(N), DCI)) if (SDValue Widended = widenLoad(cast<LoadSDNode>(N), DCI))
return Widended; return Widended;
[[fallthrough]]; [[fallthrough]];
} }
default: { default: {
if (!DCI.isBeforeLegalize()) { if (!DCI.isBeforeLegalize()) {
if (MemSDNode *MemNode = dyn_cast<MemSDNode>(N)) if (MemSDNode *MemNode = dyn_cast<MemSDNode>(N))
▲ Show 20 Lines • Show All 1,687 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test no legal f16. Should just keep the cast to f32 and ; Test no legal f16. Should just keep the cast to f32 and
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-SDAG %s ; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-GISEL %s ; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-GISEL %s
; Test legal f16, no f16 fmed3. Should expand to min/max sequence ; Test legal f16, no f16 fmed3. Should expand to min/max sequence
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-SDAG %s ; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s ; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
; Legal f16 med3. InstCombine ought to shrink the f32 op to f16. ; Legal f16 med3. InstCombine ought to shrink the f32 op to f16 so the codegen doesn't really matter for this.
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s ; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s ; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
declare float @llvm.amdgcn.fmed3.f32(float, float, float) #0 declare float @llvm.amdgcn.fmed3.f32(float, float, float) #0
declare float @llvm.fabs.f32(float) #0 declare float @llvm.fabs.f32(float) #0
declare half @llvm.fabs.f16(half) #0 declare half @llvm.fabs.f16(half) #0
Show All 11 Lines
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-SDAG-NEXT: v_max_f16_e32 v3, v0, v1
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v2
; GFX8-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: s_setpc_b64 s[30:31] ;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16: ; GFX9-LABEL: fmed3_f32_fpext_f16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2
Show All 21 Lines
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_flags: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_flags:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-SDAG-NEXT: v_max_f16_e32 v3, v0, v1
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v2
; GFX8-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: s_setpc_b64 s[30:31] ;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_flags:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_flags: ; GFX9-LABEL: fmed3_f32_fpext_f16_flags:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; GFX7-GISEL: ; %bb.0: ; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-GISEL-NEXT: v_med3_f32 v0, 2.0, v0, v1 ; GFX7-GISEL-NEXT: v_med3_f32 v0, 2.0, v0, v1
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_k0: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_k0:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-SDAG-NEXT: v_max_f16_e32 v2, 2.0, v0
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, 2.0, v0
; GFX8-NEXT: v_med3_f32 v0, 2.0, v0, v1 ; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_k0:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_min_f16_e32 v2, 2.0, v0
; GFX8-GISEL-NEXT: v_max_f16_e32 v0, 2.0, v0
; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v2, v1
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_k0: ; GFX9-LABEL: fmed3_f32_fpext_f16_k0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-NEXT: v_med3_f32 v0, 2.0, v0, v1 ; GFX9-NEXT: v_med3_f32 v0, 2.0, v0, v1
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
Show All 18 Lines
; GFX7-GISEL: ; %bb.0: ; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, 2.0, v1 ; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, 2.0, v1
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_k1: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_k1:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-SDAG-NEXT: v_max_f16_e32 v2, 2.0, v0
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, 2.0, v0
; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, v1 ; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_k1:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_min_f16_e32 v2, 2.0, v0
; GFX8-GISEL-NEXT: v_max_f16_e32 v0, 2.0, v0
; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v2, v1
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_k1: ; GFX9-LABEL: fmed3_f32_fpext_f16_k1:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-NEXT: v_med3_f32 v0, v0, 2.0, v1 ; GFX9-NEXT: v_med3_f32 v0, v0, 2.0, v1
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
Show All 18 Lines
; GFX7-GISEL: ; %bb.0: ; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, 2.0 ; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, 2.0
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_k2: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_k2:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-SDAG-NEXT: v_max_f16_e32 v2, v0, v1
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-NEXT: v_med3_f32 v0, v0, v1, 2.0 ; GFX8-SDAG-NEXT: v_max_f16_e32 v0, 2.0, v0
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_k2:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_min_f16_e32 v2, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v1, 2.0, v2
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_k2: ; GFX9-LABEL: fmed3_f32_fpext_f16_k2:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-NEXT: v_med3_f32 v0, v0, v1, 2.0 ; GFX9-NEXT: v_med3_f32 v0, v0, v1, 2.0
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
Show All 19 Lines
; GFX7-GISEL: ; %bb.0: ; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, 0x41800000 ; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, 0x41800000
; GFX7-GISEL-NEXT: v_med3_f32 v0, 0, v1, v0 ; GFX7-GISEL-NEXT: v_med3_f32 v0, 0, v1, v0
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_k0_k1: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_k0_k1:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, 0x4c00
; GFX8-NEXT: v_mov_b32_e32 v1, 0x41800000 ; GFX8-SDAG-NEXT: v_max_f16_e32 v2, 0, v1
; GFX8-NEXT: v_med3_f32 v0, 0, v1, v0 ; GFX8-SDAG-NEXT: v_min_f16_e32 v1, 0, v1
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v2, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_k0_k1:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 0x4c00
; GFX8-GISEL-NEXT: v_min_f16_e32 v2, 0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v1, 0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v2, v0
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v1, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_k0_k1: ; GFX9-LABEL: fmed3_f32_fpext_f16_k0_k1:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x41800000 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x41800000
; GFX9-NEXT: v_med3_f32 v0, 0, v1, v0 ; GFX9-NEXT: v_med3_f32 v0, 0, v1, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
Show All 16 Lines
; GFX7-GISEL-LABEL: fmed3_f32_fpext_f16_k0_k2: ; GFX7-GISEL-LABEL: fmed3_f32_fpext_f16_k0_k2:
; GFX7-GISEL: ; %bb.0: ; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-GISEL-NEXT: v_med3_f32 v0, 0, v0, 2.0 ; GFX7-GISEL-NEXT: v_med3_f32 v0, 0, v0, 2.0
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_k0_k2: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_k0_k2:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-SDAG-NEXT: v_max_f16_e32 v1, 0, v0
; GFX8-NEXT: v_med3_f32 v0, 0, v0, 2.0 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, 0, v0
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_max_f16_e32 v0, 2.0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_k0_k2:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_min_f16_e32 v1, 0, v0
; GFX8-GISEL-NEXT: v_max_f16_e32 v0, 0, v0
; GFX8-GISEL-NEXT: v_max_f16_e32 v1, 2.0, v1
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_k0_k2: ; GFX9-LABEL: fmed3_f32_fpext_f16_k0_k2:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_med3_f32 v0, 0, v0, 2.0 ; GFX9-NEXT: v_med3_f32 v0, 0, v0, 2.0
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
Show All 23 Lines
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v0, |v0| ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v1, |v1| ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v1, |v1|
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v2, |v2| ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v2, |v2|
; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_fabs: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_fabs:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e64 v0, |v0| ; GFX8-SDAG-NEXT: v_max_f16_e64 v3, |v0|, |v1|
; GFX8-NEXT: v_cvt_f32_f16_e64 v1, |v1| ; GFX8-SDAG-NEXT: v_min_f16_e64 v0, |v0|, |v1|
; GFX8-NEXT: v_cvt_f32_f16_e64 v2, |v2| ; GFX8-SDAG-NEXT: v_max_f16_e64 v0, v0, |v2|
; GFX8-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: s_setpc_b64 s[30:31] ;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_fabs:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_min_f16_e64 v3, |v0|, |v1|
; GFX8-GISEL-NEXT: v_max_f16_e64 v0, |v0|, |v1|
; GFX8-GISEL-NEXT: v_max_f16_e64 v1, v3, |v2|
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_fabs: ; GFX9-LABEL: fmed3_f32_fpext_f16_fabs:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e64 v0, |v0| ; GFX9-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; GFX9-NEXT: v_cvt_f32_f16_e64 v1, |v1| ; GFX9-NEXT: v_cvt_f32_f16_e64 v1, |v1|
; GFX9-NEXT: v_cvt_f32_f16_e64 v2, |v2| ; GFX9-NEXT: v_cvt_f32_f16_e64 v2, |v2|
; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v0 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v0
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v1, -v1 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v2, -v2 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v2, -v2
; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_fneg: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_fneg:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e64 v0, -v0 ; GFX8-SDAG-NEXT: v_max_f16_e64 v3, -v0, -v1
; GFX8-NEXT: v_cvt_f32_f16_e64 v1, -v1 ; GFX8-SDAG-NEXT: v_min_f16_e64 v0, -v0, -v1
; GFX8-NEXT: v_cvt_f32_f16_e64 v2, -v2 ; GFX8-SDAG-NEXT: v_max_f16_e64 v0, v0, -v2
; GFX8-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: s_setpc_b64 s[30:31] ;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_fneg:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_min_f16_e64 v3, -v0, -v1
; GFX8-GISEL-NEXT: v_max_f16_e64 v0, -v0, -v1
; GFX8-GISEL-NEXT: v_max_f16_e64 v1, v3, -v2
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_fneg: ; GFX9-LABEL: fmed3_f32_fpext_f16_fneg:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e64 v0, -v0 ; GFX9-NEXT: v_cvt_f32_f16_e64 v0, -v0
; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -v1 ; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX9-NEXT: v_cvt_f32_f16_e64 v2, -v2 ; GFX9-NEXT: v_cvt_f32_f16_e64 v2, -v2
; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -|v0| ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v1, -|v1| ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v1, -|v1|
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v2, -|v2| ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v2, -|v2|
; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_fneg_fabs: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_fneg_fabs:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e64 v0, -|v0| ; GFX8-SDAG-NEXT: v_max_f16_e64 v3, -|v0|, -|v1|
; GFX8-NEXT: v_cvt_f32_f16_e64 v1, -|v1| ; GFX8-SDAG-NEXT: v_min_f16_e64 v0, -|v0|, -|v1|
; GFX8-NEXT: v_cvt_f32_f16_e64 v2, -|v2| ; GFX8-SDAG-NEXT: v_max_f16_e64 v0, v0, -|v2|
; GFX8-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX8-NEXT: s_setpc_b64 s[30:31] ;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_fneg_fabs:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_min_f16_e64 v3, -|v0|, -|v1|
; GFX8-GISEL-NEXT: v_max_f16_e64 v0, -|v0|, -|v1|
; GFX8-GISEL-NEXT: v_max_f16_e64 v1, v3, -|v2|
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_fneg_fabs: ; GFX9-LABEL: fmed3_f32_fpext_f16_fneg_fabs:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e64 v0, -|v0| ; GFX9-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -|v1| ; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -|v1|
; GFX9-NEXT: v_cvt_f32_f16_e64 v2, -|v2| ; GFX9-NEXT: v_cvt_f32_f16_e64 v2, -|v2|
; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX8-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; GFX8-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_fptrunc_bf16: ; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_fptrunc_bf16:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
; GFX8-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_fptrunc_bf16: ; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_fptrunc_bf16:
; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
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; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v1 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v1
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v2 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v2
; GFX7-GISEL-NEXT: flat_store_dword v[3:4], v5 ; GFX7-GISEL-NEXT: flat_store_dword v[3:4], v5
; GFX7-GISEL-NEXT: v_med3_f32 v0, v5, v0, v1 ; GFX7-GISEL-NEXT: v_med3_f32 v0, v5, v0, v1
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_multi_use_0: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_multi_use_0:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v0 ; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v5, v0
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v1 ; GFX8-SDAG-NEXT: flat_store_dword v[3:4], v5
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v2 ; GFX8-SDAG-NEXT: v_max_f16_e32 v3, v0, v1
; GFX8-NEXT: flat_store_dword v[3:4], v5 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-NEXT: v_med3_f32 v0, v5, v0, v1 ; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v2
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_multi_use_0:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v5, v0
; GFX8-GISEL-NEXT: flat_store_dword v[3:4], v5
; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_multi_use_0: ; GFX9-LABEL: fmed3_f32_fpext_f16_multi_use_0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v5, v0
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v1 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v1
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v2 ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v2
; GFX9-NEXT: global_store_dword v[3:4], v5, off ; GFX9-NEXT: global_store_dword v[3:4], v5, off
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; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX7-GISEL-NEXT: flat_store_dword v[3:4], v1 ; GFX7-GISEL-NEXT: flat_store_dword v[3:4], v1
; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_multi_use_1: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_multi_use_1:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v5, v1
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-SDAG-NEXT: flat_store_dword v[3:4], v5
; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-SDAG-NEXT: v_max_f16_e32 v3, v0, v1
; GFX8-NEXT: flat_store_dword v[3:4], v1 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v2
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_multi_use_1:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v5, v1
; GFX8-GISEL-NEXT: flat_store_dword v[3:4], v5
; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_multi_use_1: ; GFX9-LABEL: fmed3_f32_fpext_f16_multi_use_1:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX9-NEXT: global_store_dword v[3:4], v1, off ; GFX9-NEXT: global_store_dword v[3:4], v1, off
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; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX7-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: flat_store_dword v[3:4], v2 ; GFX7-GISEL-NEXT: flat_store_dword v[3:4], v2
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: fmed3_f32_fpext_f16_multi_use_2: ; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_multi_use_2:
; GFX8: ; %bb.0: ; GFX8-SDAG: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v5, v2
; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-SDAG-NEXT: flat_store_dword v[3:4], v5
; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-SDAG-NEXT: v_max_f16_e32 v3, v0, v1
; GFX8-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v2
; GFX8-NEXT: flat_store_dword v[3:4], v2 ; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_multi_use_2:
; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v5, v2
; GFX8-GISEL-NEXT: flat_store_dword v[3:4], v5
; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: fmed3_f32_fpext_f16_multi_use_2: ; GFX9-LABEL: fmed3_f32_fpext_f16_multi_use_2:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX9-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX9-NEXT: v_med3_f32 v0, v0, v1, v2
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; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_bf16: ; GFX8-GISEL-LABEL: fmed3_f32_fpext_bf16:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
; GFX8-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-SDAG-LABEL: fmed3_f32_fpext_bf16: ; GFX9-SDAG-LABEL: fmed3_f32_fpext_bf16:
; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX9-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX9-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_bf16_0: ; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_bf16_0:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
; GFX8-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_bf16_0: ; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_bf16_0:
; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX9-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX9-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2
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; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_bf16_1: ; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_bf16_1:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
; GFX8-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_bf16_1: ; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_bf16_1:
; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX9-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX9-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2
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; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2
; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX8-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_bf16_2: ; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_bf16_2:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2 ; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
; GFX8-GISEL-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_bf16_2: ; GFX9-SDAG-LABEL: fmed3_f32_fpext_f16_bf16_2:
; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2 ; GFX9-SDAG-NEXT: v_med3_f32 v0, v0, v1, v2
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