[ARC] Use backwards scavenging in frame index elimination

[foad]

Summary

This is preferred because it does not rely on accurate kill flags.

[arsenm]

Since there are no required changes, why not just let this take the flip of the default? I think the option should be dropped ASAP and this just increases that diff

[foad]

In D150599#4343332, @arsenm wrote:

Since there are no required changes, why not just let this take the flip of the default? I think the option should be dropped ASAP and this just increases that diff

Because I think there is a faster route to removing RegScavenger::forward that does not require converting all targets to supportsBackwardScavenger. Only the targets that actually scavenge during the replaceFrameIndices loop need to be converted, and there are not too many of those.

[foad]

Might need to use scavengeRegisterBackwards for correctness.

[foad]

Switch to scavengeRegisterBackwards.

llvm/lib/Target/ARC/ARCRegisterInfo.h

public:
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
   bool useFPForScavengingIndex(const MachineFunction &MF) const override;
 
+  bool supportsBackwardScavenger() const override { return true; }
+
   bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID CC) const override;
 
   // Debug information queries.

llvm/lib/Target/ARC/ARCRegisterInfo.cpp

static void replaceFrameIndex(MachineBasicBlock::iterator II,
   if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) {
     // We need to use a scratch register to reach the far-away frame indexes.
     BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass);
     if (!BaseReg) {
       // We can be sure that the scavenged-register slot is within the range
       // of the load offset.
       const TargetRegisterInfo *TRI =
           MBB.getParent()->getSubtarget().getRegisterInfo();
-      BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
+      BaseReg =
+          RS->scavengeRegisterBackwards(ARC::GPR32RegClass, II, false, SPAdj);
       assert(BaseReg && "Register scavenging failed.");
       LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
                         << " for FrameReg=" << printReg(FrameReg, TRI)
                         << "+Offset=" << Offset << "\n");
       (void)TRI;
       RS->setRegUsed(BaseReg);
     }
     unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;