[llvm] Fix include guards

[IncludeGuardian]

Summary

Add missing include guards to LLVM header files that did not previously
have them and update existing include guards to ensure that they enclose
all non-whitespace, non-comment text to enable these headers for the
multiple-include optimization.

[foad]

AMDGPU parts look fine, thanks.

[IncludeGuardian]

Anyone want to give this a final look and approval?

[barannikov88]

LG, thanks

[lattner]

cool thx

llvm/lib/Support/DebugOptions.h

 //===-- DebugOptions.h - Global Command line opt for libSupport  *- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the entry point to initialize the options registered on the
 // command line for libSupport, this is internal to libSupport.
 //
 //===----------------------------------------------------------------------===//
 
+#ifndef LLVM_SUPPORT_DEBUGOPTIONS_H
+#define LLVM_SUPPORT_DEBUGOPTIONS_H
+
 namespace llvm {
 
 // These are invoked internally before parsing command line options.
 // This enables lazy-initialization of all the globals in libSupport, instead
 // of eagerly loading everything on program startup.
 void initDebugCounterOptions();
 void initGraphWriterOptions();
 void initSignalsOptions();
 void initStatisticOptions();
 void initTimerOptions();
 void initTypeSizeOptions();
 void initWithColorOptions();
 void initDebugOptions();
 void initRandomSeedOptions();
 
 } // namespace llvm
+
+#endif // LLVM_SUPPORT_DEBUGOPTIONS_H

llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h

 //===-- AArch64SMEAttributes.h - Helper for interpreting SME attributes -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/IR/Function.h"
-
 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64SMEATTRIBUTES_H
 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64SMEATTRIBUTES_H
+
+#include "llvm/IR/Function.h"
+
 namespace llvm {
 
 class Function;
 class CallBase;
 class AttributeList;
 
 /// SMEAttrs is a utility class to parse the SME ACLE attributes on functions.
 /// It helps determine a function's requirements for PSTATE.ZA and PSTATE.SM. It

llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h

 //=== lib/CodeGen/GlobalISel/AMDGPUCombinerHelper.h -------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This contains common combine transformations that may be used in a combine
 /// pass.
 ///
 //===----------------------------------------------------------------------===//
 
+#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUCOMBINERHELPER_H
+#define LLVM_LIB_TARGET_AMDGPU_AMDGPUCOMBINERHELPER_H
+
 #include "llvm/CodeGen/GlobalISel/Combiner.h"
 #include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
 
 using namespace llvm;
 
 class AMDGPUCombinerHelper : public CombinerHelper {
 public:
   using CombinerHelper::CombinerHelper;
 
   bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
   void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
 
   bool matchExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
                                    Register Src1, Register Src2);
   void applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
                                    Register Src1, Register Src2);
 };
+
+#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUCOMBINERHELPER_H

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h

 // multiple return nodes. It is not desirable to structurize regions with
 // uniform branches, so unifying those to the same return block as divergent
 // branches inhibits use of scalar branching. It still can't deal with the case
 // where one branch goes to return, and one unreachable. Replace unreachable in
 // this case with a return.
 //
 //===----------------------------------------------------------------------===//
 
+#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUUNIFYDIVERGENTEXITNODES_H
+#define LLVM_LIB_TARGET_AMDGPU_AMDGPUUNIFYDIVERGENTEXITNODES_H
+
 #include "AMDGPU.h"
 
 namespace llvm {
 class AMDGPUUnifyDivergentExitNodesPass
     : public PassInfoMixin<AMDGPUUnifyDivergentExitNodesPass> {
 public:
   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
 };
 
 } // end namespace llvm
+
+#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUUNIFYDIVERGENTEXITNODES_H

llvm/lib/Target/DirectX/DXILResourceAnalysis.h

 //===- DXILResourceAnalysis.h   - DXIL Resource analysis-------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file This file contains Analysis for information about DXIL resources.
 ///
 //===----------------------------------------------------------------------===//
 
+#ifndef LLVM_TARGET_DIRECTX_DXILRESOURCEANALYSIS_H
+#define LLVM_TARGET_DIRECTX_DXILRESOURCEANALYSIS_H
+
 #include "DXILResource.h"
 #include "llvm/IR/PassManager.h"
 #include "llvm/Pass.h"
 #include <memory>
 
 namespace llvm {
 /// Analysis pass that exposes the \c DXILResource for a module.
 class DXILResourceAnalysis : public AnalysisInfoMixin<DXILResourceAnalysis> {
public:
   const dxil::Resources &getDXILResource() const { return Resources; }
 
   /// Calculate the DXILResource for the module.
   bool runOnModule(Module &M) override;
 
   void print(raw_ostream &O, const Module *M = nullptr) const override;
 };
 } // namespace llvm
+
+#endif // LLVM_TARGET_DIRECTX_DXILRESOURCEANALYSIS_H

llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.h

 //===- Bitcode/Writer/DXILBitcodeWriter.cpp - DXIL Bitcode Writer ---------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // Bitcode writer implementation.
 //
 //===----------------------------------------------------------------------===//
 
+#ifndef LLVM_DXILWRITER_DXILBITCODEWRITER_H
+#define LLVM_DXILWRITER_DXILBITCODEWRITER_H
+
 #include "llvm/ADT/StringRef.h"
 #include "llvm/IR/ModuleSummaryIndex.h"
 #include "llvm/MC/StringTableBuilder.h"
 #include "llvm/Support/Allocator.h"
 #include "llvm/Support/MemoryBufferRef.h"
 #include <map>
 #include <memory>
 #include <string>

 ///
 /// For streams where it matters, the given stream should be in "binary"
 /// mode.
 void WriteDXILToFile(const Module &M, raw_ostream &Out);
 
 } // namespace dxil
 
 } // namespace llvm
+
+#endif // LLVM_DXILWRITER_DXILBITCODEWRITER_H

llvm/lib/Target/SystemZ/SystemZMachineScheduler.h

 //==- SystemZMachineScheduler.h - SystemZ Scheduler Interface ----*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // -------------------------- Post RA scheduling ---------------------------- //
 // SystemZPostRASchedStrategy is a scheduling strategy which is plugged into
 // the MachineScheduler. It has a sorted Available set of SUs and a pickNode()
 // implementation that looks to optimize decoder grouping and balance the
 // usage of processor resources. Scheduler states are saved for the end
 // region of each MBB, so that a successor block can learn from it.
 //===----------------------------------------------------------------------===//
 
+#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H
+#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H
+
 #include "SystemZHazardRecognizer.h"
 #include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include <set>
 
-#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H
-#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H
-
 using namespace llvm;
 
 namespace llvm {
 
 /// A MachineSchedStrategy implementation for SystemZ post RA scheduling.
 class SystemZPostRASchedStrategy : public MachineSchedStrategy {
 
   const MachineLoopInfo *MLI;