[LegalizeTypes][RISCV][VE] Add a special case to IntegerExpandSetCCOperands.

[craig.topper]

Summary

This code handles splitting setccs where the type is 2x the size of
a legal integer type. For example, i64 on RV32.

For a setcc like (x u< -256U), we used to try to emit
(hi(x) == -1U) ? (lo(x) u< -256U) : (hi(x) u< -1U)

The (hi(x) u< -1U) part simplies to (hi(x) != -1U) since -1U is the largest
unsigned value.

This leaves
(hi(x) == -1U) ? (lo(x) u< -256U) : (hi(x) != -1U)

Notice that the false value is the inverse of the condition. We can
simplify this to ((lo(x) u< -256U) | (hi(x) != -1U)). Add this as a special
case.

I could do this in DAGCombine, but it would probably require more code and
I don't know if this pattern occurs anywhere else.

[craig.topper]

D150286 is an attempt to fix the same issue and seems to get cases this one doesn't.

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (HasSETCCCARRY) {
     SDValue Res = DAG.getNode(ISD::SETCCCARRY, dl, getSetCCResultType(HiVT),
                               LHSHi, RHSHi, LowCmp.getValue(1),
                               DAG.getCondCode(CCCode));
     NewLHS = Res;
     NewRHS = SDValue();
     return;
   }
 
+  // If HiCmp simplified to LHSHi != RHSHi, then we don't need a select and can
+  // use an OR instead.
+  if (HiCmp.getOpcode() == ISD::SETCC &&
+      cast<CondCodeSDNode>(HiCmp.getOperand(2))->get() == ISD::SETNE &&
+      ((HiCmp.getOperand(0) == LHSHi && HiCmp.getOperand(1) == RHSHi) ||
+       (HiCmp.getOperand(0) == RHSHi && HiCmp.getOperand(1) == LHSHi))) {
+    NewLHS = DAG.getNode(ISD::OR, dl, LoCmp.getValueType(), LoCmp, HiCmp);
+    NewRHS = SDValue();
+    return;
+  }
+
   NewLHS = TLI.SimplifySetCC(getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ,
                              false, DagCombineInfo, dl);
   if (!NewLHS.getNode())
     NewLHS =
         DAG.getSetCC(dl, getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ);
   NewLHS = DAG.getSelect(dl, LoCmp.getValueType(), NewLHS, LoCmp, HiCmp);
   NewRHS = SDValue();
 }

llvm/test/CodeGen/RISCV/forced-atomics.ll

 ; RV32-NEXT:    sw a1, 4(sp)
 ; RV32-NEXT:    mv a1, sp
 ; RV32-NEXT:    li a4, 5
 ; RV32-NEXT:    li a5, 5
 ; RV32-NEXT:    mv a0, s0
 ; RV32-NEXT:    call __atomic_compare_exchange_8@plt
 ; RV32-NEXT:    lw a1, 4(sp)
 ; RV32-NEXT:    lw a4, 0(sp)
-; RV32-NEXT:    bnez a0, .LBB51_6
+; RV32-NEXT:    bnez a0, .LBB51_4
 ; RV32-NEXT:  .LBB51_2: # %atomicrmw.start
 ; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32-NEXT:    beqz a1, .LBB51_4
-; RV32-NEXT:  # %bb.3: # %atomicrmw.start
-; RV32-NEXT:    # in Loop: Header=BB51_2 Depth=1
 ; RV32-NEXT:    snez a0, a1
+; RV32-NEXT:    sltiu a2, a4, 2
+; RV32-NEXT:    xori a2, a2, 1
+; RV32-NEXT:    or a0, a2, a0
 ; RV32-NEXT:    mv a2, a4
 ; RV32-NEXT:    bnez a0, .LBB51_1
-; RV32-NEXT:    j .LBB51_5
-; RV32-NEXT:  .LBB51_4: # in Loop: Header=BB51_2 Depth=1
-; RV32-NEXT:    sltiu a0, a4, 2
-; RV32-NEXT:    xori a0, a0, 1
-; RV32-NEXT:    mv a2, a4
-; RV32-NEXT:    bnez a0, .LBB51_1
-; RV32-NEXT:  .LBB51_5: # %atomicrmw.start
+; RV32-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32-NEXT:    # in Loop: Header=BB51_2 Depth=1
 ; RV32-NEXT:    li a2, 1
 ; RV32-NEXT:    j .LBB51_1
-; RV32-NEXT:  .LBB51_6: # %atomicrmw.end
+; RV32-NEXT:  .LBB51_4: # %atomicrmw.end
 ; RV32-NEXT:    mv a0, a4
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-NO-ATOMIC-LABEL: rmw64_umax_seq_cst:
 ; RV64-NO-ATOMIC:       # %bb.0:

llvm/test/CodeGen/RISCV/fpclamptosat.ll

 ; RV32IF-NEXT:    lw a0, 16(sp)
 ; RV32IF-NEXT:    beqz a1, .LBB20_2
 ; RV32IF-NEXT:  # %bb.1: # %entry
 ; RV32IF-NEXT:    slti a2, a1, 0
 ; RV32IF-NEXT:    j .LBB20_3
 ; RV32IF-NEXT:  .LBB20_2:
 ; RV32IF-NEXT:    seqz a2, a0
 ; RV32IF-NEXT:  .LBB20_3: # %entry
-; RV32IF-NEXT:    lw a3, 12(sp)
-; RV32IF-NEXT:    xori a4, a0, 1
-; RV32IF-NEXT:    or a4, a4, a1
-; RV32IF-NEXT:    seqz a4, a4
-; RV32IF-NEXT:    addi a4, a4, -1
-; RV32IF-NEXT:    and a2, a4, a2
-; RV32IF-NEXT:    neg a4, a2
-; RV32IF-NEXT:    bnez a2, .LBB20_5
+; RV32IF-NEXT:    xori a3, a0, 1
+; RV32IF-NEXT:    or a3, a3, a1
+; RV32IF-NEXT:    seqz a3, a3
+; RV32IF-NEXT:    addi a3, a3, -1
+; RV32IF-NEXT:    and a3, a3, a2
+; RV32IF-NEXT:    neg a2, a3
+; RV32IF-NEXT:    bnez a3, .LBB20_5
 ; RV32IF-NEXT:  # %bb.4: # %entry
 ; RV32IF-NEXT:    li a0, 1
 ; RV32IF-NEXT:  .LBB20_5: # %entry
-; RV32IF-NEXT:    lw a5, 8(sp)
-; RV32IF-NEXT:    and a2, a4, a1
-; RV32IF-NEXT:    and a1, a4, a3
-; RV32IF-NEXT:    beqz a2, .LBB20_8
+; RV32IF-NEXT:    lw a3, 8(sp)
+; RV32IF-NEXT:    lw a4, 12(sp)
+; RV32IF-NEXT:    and a5, a2, a1
+; RV32IF-NEXT:    beqz a5, .LBB20_7
 ; RV32IF-NEXT:  # %bb.6: # %entry
-; RV32IF-NEXT:    sgtz a3, a2
-; RV32IF-NEXT:    and a4, a4, a5
-; RV32IF-NEXT:    bnez a1, .LBB20_9
+; RV32IF-NEXT:    sgtz a1, a5
+; RV32IF-NEXT:    j .LBB20_8
 ; RV32IF-NEXT:  .LBB20_7:
-; RV32IF-NEXT:    snez a5, a4
-; RV32IF-NEXT:    or a0, a0, a2
+; RV32IF-NEXT:    snez a1, a0
+; RV32IF-NEXT:  .LBB20_8: # %entry
+; RV32IF-NEXT:    and a4, a2, a4
+; RV32IF-NEXT:    or a0, a0, a5
+; RV32IF-NEXT:    and a2, a2, a3
 ; RV32IF-NEXT:    bnez a0, .LBB20_10
-; RV32IF-NEXT:    j .LBB20_11
-; RV32IF-NEXT:  .LBB20_8:
-; RV32IF-NEXT:    snez a3, a0
-; RV32IF-NEXT:    and a4, a4, a5
-; RV32IF-NEXT:    beqz a1, .LBB20_7
-; RV32IF-NEXT:  .LBB20_9: # %entry
-; RV32IF-NEXT:    snez a5, a1
-; RV32IF-NEXT:    or a0, a0, a2
-; RV32IF-NEXT:    beqz a0, .LBB20_11
+; RV32IF-NEXT:  # %bb.9:
+; RV32IF-NEXT:    or a0, a2, a4
+; RV32IF-NEXT:    snez a1, a0
 ; RV32IF-NEXT:  .LBB20_10: # %entry
-; RV32IF-NEXT:    mv a5, a3
-; RV32IF-NEXT:  .LBB20_11: # %entry
-; RV32IF-NEXT:    neg a2, a5
-; RV32IF-NEXT:    and a0, a2, a4
-; RV32IF-NEXT:    and a1, a2, a1
+; RV32IF-NEXT:    neg a1, a1
+; RV32IF-NEXT:    and a0, a1, a2
+; RV32IF-NEXT:    and a1, a1, a4
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f64i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16

 ; RV32IFD-NEXT:    lw a0, 16(sp)
 ; RV32IFD-NEXT:    beqz a1, .LBB20_2
 ; RV32IFD-NEXT:  # %bb.1: # %entry
 ; RV32IFD-NEXT:    slti a2, a1, 0
 ; RV32IFD-NEXT:    j .LBB20_3
 ; RV32IFD-NEXT:  .LBB20_2:
 ; RV32IFD-NEXT:    seqz a2, a0
 ; RV32IFD-NEXT:  .LBB20_3: # %entry
-; RV32IFD-NEXT:    lw a3, 12(sp)
-; RV32IFD-NEXT:    xori a4, a0, 1
-; RV32IFD-NEXT:    or a4, a4, a1
-; RV32IFD-NEXT:    seqz a4, a4
-; RV32IFD-NEXT:    addi a4, a4, -1
-; RV32IFD-NEXT:    and a2, a4, a2
-; RV32IFD-NEXT:    neg a4, a2
-; RV32IFD-NEXT:    bnez a2, .LBB20_5
+; RV32IFD-NEXT:    xori a3, a0, 1
+; RV32IFD-NEXT:    or a3, a3, a1
+; RV32IFD-NEXT:    seqz a3, a3
+; RV32IFD-NEXT:    addi a3, a3, -1
+; RV32IFD-NEXT:    and a3, a3, a2
+; RV32IFD-NEXT:    neg a2, a3
+; RV32IFD-NEXT:    bnez a3, .LBB20_5
 ; RV32IFD-NEXT:  # %bb.4: # %entry
 ; RV32IFD-NEXT:    li a0, 1
 ; RV32IFD-NEXT:  .LBB20_5: # %entry
-; RV32IFD-NEXT:    lw a5, 8(sp)
-; RV32IFD-NEXT:    and a2, a4, a1
-; RV32IFD-NEXT:    and a1, a4, a3
-; RV32IFD-NEXT:    beqz a2, .LBB20_8
+; RV32IFD-NEXT:    lw a3, 8(sp)
+; RV32IFD-NEXT:    lw a4, 12(sp)
+; RV32IFD-NEXT:    and a5, a2, a1
+; RV32IFD-NEXT:    beqz a5, .LBB20_7
 ; RV32IFD-NEXT:  # %bb.6: # %entry
-; RV32IFD-NEXT:    sgtz a3, a2
-; RV32IFD-NEXT:    and a4, a4, a5
-; RV32IFD-NEXT:    bnez a1, .LBB20_9
+; RV32IFD-NEXT:    sgtz a1, a5
+; RV32IFD-NEXT:    j .LBB20_8
 ; RV32IFD-NEXT:  .LBB20_7:
-; RV32IFD-NEXT:    snez a5, a4
-; RV32IFD-NEXT:    or a0, a0, a2
+; RV32IFD-NEXT:    snez a1, a0
+; RV32IFD-NEXT:  .LBB20_8: # %entry
+; RV32IFD-NEXT:    and a4, a2, a4
+; RV32IFD-NEXT:    or a0, a0, a5
+; RV32IFD-NEXT:    and a2, a2, a3
 ; RV32IFD-NEXT:    bnez a0, .LBB20_10
-; RV32IFD-NEXT:    j .LBB20_11
-; RV32IFD-NEXT:  .LBB20_8:
-; RV32IFD-NEXT:    snez a3, a0
-; RV32IFD-NEXT:    and a4, a4, a5
-; RV32IFD-NEXT:    beqz a1, .LBB20_7
-; RV32IFD-NEXT:  .LBB20_9: # %entry
-; RV32IFD-NEXT:    snez a5, a1
-; RV32IFD-NEXT:    or a0, a0, a2
-; RV32IFD-NEXT:    beqz a0, .LBB20_11
+; RV32IFD-NEXT:  # %bb.9:
+; RV32IFD-NEXT:    or a0, a2, a4
+; RV32IFD-NEXT:    snez a1, a0
 ; RV32IFD-NEXT:  .LBB20_10: # %entry
-; RV32IFD-NEXT:    mv a5, a3
-; RV32IFD-NEXT:  .LBB20_11: # %entry
-; RV32IFD-NEXT:    neg a2, a5
-; RV32IFD-NEXT:    and a0, a2, a4
-; RV32IFD-NEXT:    and a1, a2, a1
+; RV32IFD-NEXT:    neg a1, a1
+; RV32IFD-NEXT:    and a0, a1, a2
+; RV32IFD-NEXT:    and a1, a1, a4
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
 entry:
   %conv = fptosi double %x to i128
   %0 = icmp slt i128 %conv, 18446744073709551616
   %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616
   %1 = icmp sgt i128 %spec.store.select, 0

 ; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    beqz a1, .LBB23_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    slti a2, a1, 0
 ; RV32-NEXT:    j .LBB23_3
 ; RV32-NEXT:  .LBB23_2:
 ; RV32-NEXT:    seqz a2, a0
 ; RV32-NEXT:  .LBB23_3: # %entry
-; RV32-NEXT:    lw a3, 12(sp)
-; RV32-NEXT:    xori a4, a0, 1
-; RV32-NEXT:    or a4, a4, a1
-; RV32-NEXT:    seqz a4, a4
-; RV32-NEXT:    addi a4, a4, -1
-; RV32-NEXT:    and a2, a4, a2
-; RV32-NEXT:    neg a4, a2
-; RV32-NEXT:    bnez a2, .LBB23_5
+; RV32-NEXT:    xori a3, a0, 1
+; RV32-NEXT:    or a3, a3, a1
+; RV32-NEXT:    seqz a3, a3
+; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    and a3, a3, a2
+; RV32-NEXT:    neg a2, a3
+; RV32-NEXT:    bnez a3, .LBB23_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:  .LBB23_5: # %entry
-; RV32-NEXT:    lw a5, 8(sp)
-; RV32-NEXT:    and a2, a4, a1
-; RV32-NEXT:    and a1, a4, a3
-; RV32-NEXT:    beqz a2, .LBB23_8
+; RV32-NEXT:    lw a3, 8(sp)
+; RV32-NEXT:    lw a4, 12(sp)
+; RV32-NEXT:    and a5, a2, a1
+; RV32-NEXT:    beqz a5, .LBB23_7
 ; RV32-NEXT:  # %bb.6: # %entry
-; RV32-NEXT:    sgtz a3, a2
-; RV32-NEXT:    and a4, a4, a5
-; RV32-NEXT:    bnez a1, .LBB23_9
+; RV32-NEXT:    sgtz a1, a5
+; RV32-NEXT:    j .LBB23_8
 ; RV32-NEXT:  .LBB23_7:
-; RV32-NEXT:    snez a5, a4
-; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    snez a1, a0
+; RV32-NEXT:  .LBB23_8: # %entry
+; RV32-NEXT:    and a4, a2, a4
+; RV32-NEXT:    or a0, a0, a5
+; RV32-NEXT:    and a2, a2, a3
 ; RV32-NEXT:    bnez a0, .LBB23_10
-; RV32-NEXT:    j .LBB23_11
-; RV32-NEXT:  .LBB23_8:
-; RV32-NEXT:    snez a3, a0
-; RV32-NEXT:    and a4, a4, a5
-; RV32-NEXT:    beqz a1, .LBB23_7
-; RV32-NEXT:  .LBB23_9: # %entry
-; RV32-NEXT:    snez a5, a1
-; RV32-NEXT:    or a0, a0, a2
-; RV32-NEXT:    beqz a0, .LBB23_11
+; RV32-NEXT:  # %bb.9:
+; RV32-NEXT:    or a0, a2, a4
+; RV32-NEXT:    snez a1, a0
 ; RV32-NEXT:  .LBB23_10: # %entry
-; RV32-NEXT:    mv a5, a3
-; RV32-NEXT:  .LBB23_11: # %entry
-; RV32-NEXT:    neg a2, a5
-; RV32-NEXT:    and a0, a2, a4
-; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    neg a1, a1
+; RV32-NEXT:    and a0, a1, a2
+; RV32-NEXT:    and a1, a1, a4
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f32i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16

 ; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    beqz a1, .LBB26_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    slti a2, a1, 0
 ; RV32-NEXT:    j .LBB26_3
 ; RV32-NEXT:  .LBB26_2:
 ; RV32-NEXT:    seqz a2, a0
 ; RV32-NEXT:  .LBB26_3: # %entry
-; RV32-NEXT:    lw a3, 12(sp)
-; RV32-NEXT:    xori a4, a0, 1
-; RV32-NEXT:    or a4, a4, a1
-; RV32-NEXT:    seqz a4, a4
-; RV32-NEXT:    addi a4, a4, -1
-; RV32-NEXT:    and a2, a4, a2
-; RV32-NEXT:    neg a4, a2
-; RV32-NEXT:    bnez a2, .LBB26_5
+; RV32-NEXT:    xori a3, a0, 1
+; RV32-NEXT:    or a3, a3, a1
+; RV32-NEXT:    seqz a3, a3
+; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    and a3, a3, a2
+; RV32-NEXT:    neg a2, a3
+; RV32-NEXT:    bnez a3, .LBB26_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:  .LBB26_5: # %entry
-; RV32-NEXT:    lw a5, 8(sp)
-; RV32-NEXT:    and a2, a4, a1
-; RV32-NEXT:    and a1, a4, a3
-; RV32-NEXT:    beqz a2, .LBB26_8
+; RV32-NEXT:    lw a3, 8(sp)
+; RV32-NEXT:    lw a4, 12(sp)
+; RV32-NEXT:    and a5, a2, a1
+; RV32-NEXT:    beqz a5, .LBB26_7
 ; RV32-NEXT:  # %bb.6: # %entry
-; RV32-NEXT:    sgtz a3, a2
-; RV32-NEXT:    and a4, a4, a5
-; RV32-NEXT:    bnez a1, .LBB26_9
+; RV32-NEXT:    sgtz a1, a5
+; RV32-NEXT:    j .LBB26_8
 ; RV32-NEXT:  .LBB26_7:
-; RV32-NEXT:    snez a5, a4
-; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    snez a1, a0
+; RV32-NEXT:  .LBB26_8: # %entry
+; RV32-NEXT:    and a4, a2, a4
+; RV32-NEXT:    or a0, a0, a5
+; RV32-NEXT:    and a2, a2, a3
 ; RV32-NEXT:    bnez a0, .LBB26_10
-; RV32-NEXT:    j .LBB26_11
-; RV32-NEXT:  .LBB26_8:
-; RV32-NEXT:    snez a3, a0
-; RV32-NEXT:    and a4, a4, a5
-; RV32-NEXT:    beqz a1, .LBB26_7
-; RV32-NEXT:  .LBB26_9: # %entry
-; RV32-NEXT:    snez a5, a1
-; RV32-NEXT:    or a0, a0, a2
-; RV32-NEXT:    beqz a0, .LBB26_11
+; RV32-NEXT:  # %bb.9:
+; RV32-NEXT:    or a0, a2, a4
+; RV32-NEXT:    snez a1, a0
 ; RV32-NEXT:  .LBB26_10: # %entry
-; RV32-NEXT:    mv a5, a3
-; RV32-NEXT:  .LBB26_11: # %entry
-; RV32-NEXT:    neg a2, a5
-; RV32-NEXT:    and a0, a2, a4
-; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    neg a1, a1
+; RV32-NEXT:    and a0, a1, a2
+; RV32-NEXT:    and a1, a1, a4
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f16i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16

llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll

 
 define i1 @add_ultcmp_i64_i16(i64 %x) nounwind {
 ; RV32I-LABEL: add_ultcmp_i64_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, 1048568
 ; RV32I-NEXT:    add a2, a0, a2
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    beq a0, a1, .LBB10_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltiu a0, a0, -1
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB10_2:
-; RV32I-NEXT:    lui a0, 1048560
-; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    lui a1, 1048560
+; RV32I-NEXT:    sltu a1, a2, a1
+; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: add_ultcmp_i64_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1048568
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    lui a1, 1048560
 ; RV64I-NEXT:    sltu a0, a0, a1

 }
 
 define i1 @add_ultcmp_i64_i8(i64 %x) nounwind {
 ; RV32I-LABEL: add_ultcmp_i64_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, a0, -128
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    beq a0, a1, .LBB11_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltiu a0, a0, -1
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB11_2:
-; RV32I-NEXT:    sltiu a0, a2, -256
+; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:    sltiu a1, a2, -256
+; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64-LABEL: add_ultcmp_i64_i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, a0, -128
 ; RV64-NEXT:    sltiu a0, a0, -256
 ; RV64-NEXT:    ret
 ;
; RV64ZBB-NEXT:    ret
   ret i1 %tmp1
 }
 
 define i1 @add_ugecmp_i64_i8(i64 %x) nounwind {
 ; RV32I-LABEL: add_ugecmp_i64_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, a0, 128
 ; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    add a1, a1, a0
-; RV32I-NEXT:    beqz a1, .LBB18_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    snez a0, a1
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB18_2:
-; RV32I-NEXT:    sltiu a0, a2, 256
-; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:    sltiu a1, a2, 256
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64-LABEL: add_ugecmp_i64_i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    sltiu a0, a0, 256
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret

llvm/test/CodeGen/VE/Scalar/br_cc.ll

4:                                                ; preds = %3, %1
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @br_cc_u128_imm(i128 %0) {
 ; CHECK-LABEL: br_cc_u128_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or %s2, 0, (0)1
-; CHECK-NEXT:    cmps.l %s3, %s1, (0)1
-; CHECK-NEXT:    or %s4, 0, (0)1
-; CHECK-NEXT:    cmov.l.ne %s4, (63)0, %s3
+; CHECK-NEXT:    cmps.l %s1, %s1, (0)1
+; CHECK-NEXT:    or %s3, 0, (0)1
+; CHECK-NEXT:    cmov.l.ne %s3, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, (58)0
 ; CHECK-NEXT:    cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s4, %s2, %s1
-; CHECK-NEXT:    brne.w 0, %s4, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:    or %s0, %s2, %s3
+; CHECK-NEXT:    brne.w 0, %s0, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    b.l.t (, %s10)
   %2 = icmp ult i128 %0, 64
   br i1 %2, label %3, label %4

 4:                                                ; preds = %3, %1
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @br_cc_imm_u128(i128 %0) {
 ; CHECK-LABEL: br_cc_imm_u128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmps.l %s2, %s1, (0)0
+; CHECK-NEXT:    cmps.l %s1, %s1, (0)0
+; CHECK-NEXT:    or %s2, 0, (0)1
 ; CHECK-NEXT:    or %s3, 0, (0)1
-; CHECK-NEXT:    or %s4, 0, (0)1
-; CHECK-NEXT:    cmov.l.ne %s4, (63)0, %s2
+; CHECK-NEXT:    cmov.l.ne %s3, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, (58)1
-; CHECK-NEXT:    cmov.l.lt %s3, (63)0, %s0
-; CHECK-NEXT:    cmpu.l %s0, %s1, (0)0
-; CHECK-NEXT:    cmov.l.eq %s4, %s3, %s0
-; CHECK-NEXT:    brne.w 0, %s4, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:    cmov.l.lt %s2, (63)0, %s0
+; CHECK-NEXT:    or %s0, %s2, %s3
+; CHECK-NEXT:    brne.w 0, %s0, .LBB{{[0-9]+}}_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    b.l.t (, %s10)
   %2 = icmp ugt i128 %0, -65
   br i1 %2, label %3, label %4