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Differential D150238

[RISCV][NFC] Remove LMUL from vmv.s.x and vmv.x.s scheduler classes
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Authored by nitinjohnraj on May 9 2023, 6:01 PM.

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craig.topper
Commits
rG4c6ae6e0aa39: [RISCV][NFC] Remove LMUL from vmv.s.x and vmv.x.s scheduler classes
Summary

These instructions don't read or write register groups. We only pretend they do in intrinsics and pseudoinstructions.

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Event Timeline

nitinjohnraj created this revision.May 9 2023, 6:01 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 9 2023, 6:01 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 29 others. · View Herald Transcript
nitinjohnraj requested review of this revision.May 9 2023, 6:01 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 9 2023, 6:01 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B231004: Diff 520875.May 9 2023, 6:49 PM
craig.topper accepted this revision.May 9 2023, 8:42 PM

LGTM

This revision is now accepted and ready to land.May 9 2023, 8:42 PM
nitinjohnraj updated this revision to Diff 522832.May 16 2023, 4:52 PM

Updated RISCVSchedSiFive7.td, which had been changed since the last revision

nitinjohnraj requested review of this revision.May 16 2023, 4:53 PM
craig.topper accepted this revision.May 16 2023, 5:56 PM

LGTM

This revision is now accepted and ready to land.May 16 2023, 5:56 PM
Harbormaster completed remote builds in B232462: Diff 522832.May 16 2023, 6:09 PM
This revision was landed with ongoing or failed builds.May 17 2023, 3:55 AM
Closed by commit rG4c6ae6e0aa39: [RISCV][NFC] Remove LMUL from vmv.s.x and vmv.x.s scheduler classes (authored by nitinjohnraj). · Explain Why
This revision was automatically updated to reflect the committed changes.
nitinjohnraj added a commit: rG4c6ae6e0aa39: [RISCV][NFC] Remove LMUL from vmv.s.x and vmv.x.s scheduler classes.
evandro removed a subscriber: evandro.May 17 2023, 3:51 PM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
10 lines
18 lines
22 lines
40 lines

Diff 522992

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

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def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd), def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
(ins VMaskOp:$vm), "vid.v", "$vd$vm">, (ins VMaskOp:$vm), "vid.v", "$vd$vm">,
Sched<[WriteVMIdxV_WorstCase, ReadVMask]>; Sched<[WriteVMIdxV_WorstCase, ReadVMask]>;
// Integer Scalar Move Instructions // Integer Scalar Move Instructions
let vm = 1, RVVConstraint = NoConstraint in { let vm = 1, RVVConstraint = NoConstraint in {
def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd), def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
(ins VR:$vs2), "vmv.x.s", "$vd, $vs2">, (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">,
Sched<[WriteVIMovVX_WorstCase, ReadVIMovVX_WorstCase]>; Sched<[WriteVIMovVX, ReadVIMovVX]>;
let Constraints = "$vd = $vd_wb" in let Constraints = "$vd = $vd_wb" in
def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb), def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb),
(ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">, (ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">,
Sched<[WriteVIMovXV_WorstCase, ReadVIMovXV_WorstCase, Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>;
ReadVIMovXX_WorstCase]>;
} }
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVInstructions] } // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF] in { let Predicates = [HasVInstructionsAnyF] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1, let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1,
RVVConstraint = NoConstraint in { RVVConstraint = NoConstraint in {
// Floating-Point Scalar Move Instructions // Floating-Point Scalar Move Instructions
def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd), def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
(ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">, (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">,
Sched<[WriteVFMovVF_WorstCase, ReadVFMovVF_WorstCase]>; Sched<[WriteVFMovVF, ReadVFMovVF]>;
let Constraints = "$vd = $vd_wb" in let Constraints = "$vd = $vd_wb" in
def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb), def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb),
(ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">, (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">,
Sched<[WriteVFMovFV_WorstCase, ReadVFMovFV_WorstCase, Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>;
ReadVFMovFX_WorstCase]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
} // Predicates = [HasVInstructionsAnyF] } // Predicates = [HasVInstructionsAnyF]
let Predicates = [HasVInstructions] in { let Predicates = [HasVInstructions] in {
// Vector Slide Instructions // Vector Slide Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
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llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 16.1. Integer Scalar Move Instructions // 16.1. Integer Scalar Move Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasVInstructions] in { let Predicates = [HasVInstructions] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
foreach m = MxList in { foreach m = MxList in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVIMovVX_MX = !cast<SchedWrite>("WriteVIMovVX_" # mx);
defvar WriteVIMovXV_MX = !cast<SchedWrite>("WriteVIMovXV_" # mx);
defvar ReadVIMovVX_MX = !cast<SchedRead>("ReadVIMovVX_" # mx);
defvar ReadVIMovXV_MX = !cast<SchedRead>("ReadVIMovXV_" # mx);
defvar ReadVIMovXX_MX = !cast<SchedRead>("ReadVIMovXX_" # mx);
let VLMul = m.value in { let VLMul = m.value in {
let HasSEWOp = 1, BaseInstr = VMV_X_S in let HasSEWOp = 1, BaseInstr = VMV_X_S in
def PseudoVMV_X_S # "_" # mx: def PseudoVMV_X_S # "_" # mx:
Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, ixlenimm:$sew), []>, Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, ixlenimm:$sew), []>,
Sched<[WriteVIMovVX_MX, ReadVIMovVX_MX]>, Sched<[WriteVIMovVX, ReadVIMovVX]>,
RISCVVPseudo; RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
Constraints = "$rd = $rs1" in Constraints = "$rd = $rs1" in
def PseudoVMV_S_X # "_" # mx: Pseudo<(outs m.vrclass:$rd), def PseudoVMV_S_X # "_" # mx: Pseudo<(outs m.vrclass:$rd),
(ins m.vrclass:$rs1, GPR:$rs2, (ins m.vrclass:$rs1, GPR:$rs2,
AVL:$vl, ixlenimm:$sew), AVL:$vl, ixlenimm:$sew),
[]>, []>,
Sched<[WriteVIMovXV_MX, ReadVIMovXV_MX, ReadVIMovXX_MX]>, Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>,
RISCVVPseudo; RISCVVPseudo;
} }
} }
} }
} // Predicates = [HasVInstructions] } // Predicates = [HasVInstructions]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 16.2. Floating-Point Scalar Move Instructions // 16.2. Floating-Point Scalar Move Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasVInstructionsAnyF] in { let Predicates = [HasVInstructionsAnyF] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
foreach f = FPList in { foreach f = FPList in {
foreach m = f.MxList in { foreach m = f.MxList in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVFMovVF_MX = !cast<SchedWrite>("WriteVFMovVF_" # mx);
defvar WriteVFMovFV_MX = !cast<SchedWrite>("WriteVFMovFV_" # mx);
defvar ReadVFMovVF_MX = !cast<SchedRead>("ReadVFMovVF_" # mx);
defvar ReadVFMovFV_MX = !cast<SchedRead>("ReadVFMovFV_" # mx);
defvar ReadVFMovFX_MX = !cast<SchedRead>("ReadVFMovFX_" # mx);
let VLMul = m.value in { let VLMul = m.value in {
let HasSEWOp = 1, BaseInstr = VFMV_F_S in let HasSEWOp = 1, BaseInstr = VFMV_F_S in
def "PseudoVFMV_" # f.FX # "_S_" # mx : def "PseudoVFMV_" # f.FX # "_S_" # mx :
Pseudo<(outs f.fprclass:$rd), Pseudo<(outs f.fprclass:$rd),
(ins m.vrclass:$rs2, ixlenimm:$sew), []>, (ins m.vrclass:$rs2, ixlenimm:$sew), []>,
Sched<[WriteVFMovVF_MX, ReadVFMovVF_MX]>, Sched<[WriteVFMovVF, ReadVFMovVF]>,
RISCVVPseudo; RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F,
Constraints = "$rd = $rs1" in Constraints = "$rd = $rs1" in
def "PseudoVFMV_S_" # f.FX # "_" # mx : def "PseudoVFMV_S_" # f.FX # "_" # mx :
Pseudo<(outs m.vrclass:$rd), Pseudo<(outs m.vrclass:$rd),
(ins m.vrclass:$rs1, f.fprclass:$rs2, (ins m.vrclass:$rs1, f.fprclass:$rs2,
AVL:$vl, ixlenimm:$sew), AVL:$vl, ixlenimm:$sew),
[]>, []>,
Sched<[WriteVFMovFV_MX, ReadVFMovFV_MX, ReadVFMovFX_MX]>, Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>,
RISCVVPseudo; RISCVVPseudo;
} }
} }
} }
} }
} // Predicates = [HasVInstructionsAnyF] } // Predicates = [HasVInstructionsAnyF]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Show First 20 Lines • Show All 635 Lines • ▼ Show 20 Linesforeach mx = SchedMxList in {
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c; defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, ResourceCycles = [Cycles] in { let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VA], mx, IsWorstCase>;
} }
} }
// 16. Vector Permutation Instructions // 16. Vector Permutation Instructions
let Latency = 8, ResourceCycles = [1] in {
def : WriteRes<WriteVIMovVX, [SiFive7VA]>;
def : WriteRes<WriteVIMovXV, [SiFive7VA]>;
def : WriteRes<WriteVFMovVF, [SiFive7VA]>;
def : WriteRes<WriteVFMovFV, [SiFive7VA]>;
}
foreach mx = SchedMxList in { foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c; defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c; defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 8, ResourceCycles = [Cycles] in { let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVIMovVX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIMovXV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMovVF", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMovFV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFive7VA], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFive7VA], mx, IsWorstCase>;
} }
} }
foreach mx = SchedMxList in { foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in { foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, sew>.c; defvar Cycles = SiFive7GetCyclesOnePerElement<mx, sew>.c;
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// 16. Vector Mask Instructions // 16. Vector Mask Instructions
defm "" : LMULReadAdvance<"ReadVMALUV", 0>; defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
defm "" : LMULReadAdvance<"ReadVMPopV", 0>; defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
defm "" : LMULReadAdvance<"ReadVMFFSV", 0>; defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMSFSV", 0>; defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMIotV", 0>; defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
// 17. Vector Permutation Instructions // 17. Vector Permutation Instructions
defm "" : LMULReadAdvance<"ReadVIMovVX", 0>; def : ReadAdvance<ReadVIMovVX, 0>;
defm "" : LMULReadAdvance<"ReadVIMovXV", 0>; def : ReadAdvance<ReadVIMovXV, 0>;
defm "" : LMULReadAdvance<"ReadVIMovXX", 0>; def : ReadAdvance<ReadVIMovXX, 0>;
defm "" : LMULReadAdvance<"ReadVFMovVF", 0>; def : ReadAdvance<ReadVFMovVF, 0>;
defm "" : LMULReadAdvance<"ReadVFMovFV", 0>; def : ReadAdvance<ReadVFMovFV, 0>;
defm "" : LMULReadAdvance<"ReadVFMovFX", 0>; def : ReadAdvance<ReadVFMovFX, 0>;
defm "" : LMULReadAdvance<"ReadVISlideV", 0>; defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
defm "" : LMULReadAdvance<"ReadVISlideX", 0>; defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>; defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideF", 0>; defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>; defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>; defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>; defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>; defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
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llvm/lib/Target/RISCV/RISCVScheduleV.td

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defm "" : LMULSchedWrites<"WriteVMSFSV">; defm "" : LMULSchedWrites<"WriteVMSFSV">;
// 15.8. Vector Iota Instruction // 15.8. Vector Iota Instruction
defm "" : LMULSchedWrites<"WriteVMIotV">; defm "" : LMULSchedWrites<"WriteVMIotV">;
// 15.9. Vector Element Index Instruction // 15.9. Vector Element Index Instruction
defm "" : LMULSchedWrites<"WriteVMIdxV">; defm "" : LMULSchedWrites<"WriteVMIdxV">;
// 16. Vector Permutation Instructions // 16. Vector Permutation Instructions
// 16.1. Integer Scalar Move Instructions // 16.1. Integer Scalar Move Instructions
defm "" : LMULSchedWrites<"WriteVIMovVX">; def WriteVIMovVX : SchedWrite;
defm "" : LMULSchedWrites<"WriteVIMovXV">; def WriteVIMovXV : SchedWrite;
// 16.2. Floating-Point Scalar Move Instructions // 16.2. Floating-Point Scalar Move Instructions
defm "" : LMULSchedWrites<"WriteVFMovVF">; def WriteVFMovVF : SchedWrite;
defm "" : LMULSchedWrites<"WriteVFMovFV">; def WriteVFMovFV : SchedWrite;
// 16.3. Vector Slide Instructions // 16.3. Vector Slide Instructions
defm "" : LMULSchedWrites<"WriteVISlideX">; defm "" : LMULSchedWrites<"WriteVISlideX">;
defm "" : LMULSchedWrites<"WriteVISlideI">; defm "" : LMULSchedWrites<"WriteVISlideI">;
defm "" : LMULSchedWrites<"WriteVISlide1X">; defm "" : LMULSchedWrites<"WriteVISlide1X">;
defm "" : LMULSchedWrites<"WriteVFSlide1F">; defm "" : LMULSchedWrites<"WriteVFSlide1F">;
// 16.4. Vector Register Gather Instructions // 16.4. Vector Register Gather Instructions
defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">; defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">;
defm "" : LMULSchedWrites<"WriteVRGatherVX">; defm "" : LMULSchedWrites<"WriteVRGatherVX">;
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// 15.5. Vector Set-Including-First Mask Bit // 15.5. Vector Set-Including-First Mask Bit
// 15.6. Vector Set-only-First Mask Bit // 15.6. Vector Set-only-First Mask Bit
defm "" : LMULSchedReads<"ReadVMSFSV">; defm "" : LMULSchedReads<"ReadVMSFSV">;
// 15.8. Vector Iota Instruction // 15.8. Vector Iota Instruction
defm "" : LMULSchedReads<"ReadVMIotV">; defm "" : LMULSchedReads<"ReadVMIotV">;
// 16. Vector Permutation Instructions // 16. Vector Permutation Instructions
// 16.1. Integer Scalar Move Instructions // 16.1. Integer Scalar Move Instructions
defm "" : LMULSchedReads<"ReadVIMovVX">; def ReadVIMovVX : SchedRead;
defm "" : LMULSchedReads<"ReadVIMovXV">; def ReadVIMovXV : SchedRead;
defm "" : LMULSchedReads<"ReadVIMovXX">; def ReadVIMovXX : SchedRead;
// 16.2. Floating-Point Scalar Move Instructions // 16.2. Floating-Point Scalar Move Instructions
defm "" : LMULSchedReads<"ReadVFMovVF">; def ReadVFMovVF : SchedRead;
defm "" : LMULSchedReads<"ReadVFMovFV">; def ReadVFMovFV : SchedRead;
defm "" : LMULSchedReads<"ReadVFMovFX">; def ReadVFMovFX : SchedRead;
// 16.3. Vector Slide Instructions // 16.3. Vector Slide Instructions
defm "" : LMULSchedReads<"ReadVISlideV">; defm "" : LMULSchedReads<"ReadVISlideV">;
defm "" : LMULSchedReads<"ReadVISlideX">; defm "" : LMULSchedReads<"ReadVISlideX">;
defm "" : LMULSchedReads<"ReadVFSlideV">; defm "" : LMULSchedReads<"ReadVFSlideV">;
defm "" : LMULSchedReads<"ReadVFSlideF">; defm "" : LMULSchedReads<"ReadVFSlideF">;
// 16.4. Vector Register Gather Instructions // 16.4. Vector Register Gather Instructions
defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">; defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">;
defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">; defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">;
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defm "" : LMULWriteRes<"WriteVMALUV", []>; defm "" : LMULWriteRes<"WriteVMALUV", []>;
defm "" : LMULWriteRes<"WriteVMPopV", []>; defm "" : LMULWriteRes<"WriteVMPopV", []>;
defm "" : LMULWriteRes<"WriteVMFFSV", []>; defm "" : LMULWriteRes<"WriteVMFFSV", []>;
defm "" : LMULWriteRes<"WriteVMSFSV", []>; defm "" : LMULWriteRes<"WriteVMSFSV", []>;
defm "" : LMULWriteRes<"WriteVMIotV", []>; defm "" : LMULWriteRes<"WriteVMIotV", []>;
defm "" : LMULWriteRes<"WriteVMIdxV", []>; defm "" : LMULWriteRes<"WriteVMIdxV", []>;
// 16. Vector Permutation Instructions // 16. Vector Permutation Instructions
defm "" : LMULWriteRes<"WriteVIMovVX", []>; def : WriteRes<WriteVIMovVX, []>;
defm "" : LMULWriteRes<"WriteVIMovXV", []>; def : WriteRes<WriteVIMovXV, []>;
defm "" : LMULWriteRes<"WriteVFMovVF", []>; def : WriteRes<WriteVFMovVF, []>;
defm "" : LMULWriteRes<"WriteVFMovFV", []>; def : WriteRes<WriteVFMovFV, []>;
defm "" : LMULWriteRes<"WriteVISlideX", []>; defm "" : LMULWriteRes<"WriteVISlideX", []>;
defm "" : LMULWriteRes<"WriteVISlideI", []>; defm "" : LMULWriteRes<"WriteVISlideI", []>;
defm "" : LMULWriteRes<"WriteVISlide1X", []>; defm "" : LMULWriteRes<"WriteVISlide1X", []>;
defm "" : LMULWriteRes<"WriteVFSlide1F", []>; defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>; defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;
defm "" : LMULWriteRes<"WriteVRGatherVX", []>; defm "" : LMULWriteRes<"WriteVRGatherVX", []>;
defm "" : LMULWriteRes<"WriteVRGatherVI", []>; defm "" : LMULWriteRes<"WriteVRGatherVI", []>;
defm "" : LMULSEWWriteRes<"WriteVCompressV", []>; defm "" : LMULSEWWriteRes<"WriteVCompressV", []>;
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// 15. Vector Mask Instructions // 15. Vector Mask Instructions
defm "" : LMULReadAdvance<"ReadVMALUV", 0>; defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
defm "" : LMULReadAdvance<"ReadVMPopV", 0>; defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
defm "" : LMULReadAdvance<"ReadVMFFSV", 0>; defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMSFSV", 0>; defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMIotV", 0>; defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
// 16. Vector Permutation Instructions // 16. Vector Permutation Instructions
defm "" : LMULReadAdvance<"ReadVIMovVX", 0>; def : ReadAdvance<ReadVIMovVX, 0>;
defm "" : LMULReadAdvance<"ReadVIMovXV", 0>; def : ReadAdvance<ReadVIMovXV, 0>;
defm "" : LMULReadAdvance<"ReadVIMovXX", 0>; def : ReadAdvance<ReadVIMovXX, 0>;
defm "" : LMULReadAdvance<"ReadVFMovVF", 0>; def : ReadAdvance<ReadVFMovVF, 0>;
defm "" : LMULReadAdvance<"ReadVFMovFV", 0>; def : ReadAdvance<ReadVFMovFV, 0>;
defm "" : LMULReadAdvance<"ReadVFMovFX", 0>; def : ReadAdvance<ReadVFMovFX, 0>;
defm "" : LMULReadAdvance<"ReadVISlideV", 0>; defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
defm "" : LMULReadAdvance<"ReadVISlideX", 0>; defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>; defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideF", 0>; defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>; defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>; defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>; defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>; defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
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