[X86] Fix instruction's ports info which is ported from SKL in AlderlakeP model

[HaohaiWen]

Summary

AlderlakeP model is auto generated by D130897 using scheduling data from:
(priority in dsc order):

1. Measured data in uops.info.
2. GoldenCove instruction throughput and latency in intel doc.
3. Existing SkylakeClientModel.

In step 3, some ports functionality has changed and new ports were
addedd from SKL to GLC so we need to map the port number. e.g. Map uop
using port 4 (store) in SKL to port 4,9 in GLC.
The previous port mapping machanism in D130897 didn't work and is fixed now.
Refresh this AlderlakeP model to update ports of instructions which
scheduling info are ported from SKL.

[LuoYuanke]

llvm/lib/Target/X86/X86SchedAlderlakeP.td

527

Where are JMP and RET SchedWrite defined? Why the port change affect this code?

[HaohaiWen]

llvm/lib/Target/X86/X86SchedAlderlakeP.td

527

Before this patch:
JMP with folded mem uses ADLPWriteResGroup2.

def ADLPWriteResGroup2 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
  let Latency = 6;
  let NumMicroOps = 2;
}

After this patch:
JMP uses default WriteJumpLd:

defm : ADLPWriteResPair<WriteJump, [ADLPPort00_06], 1, [1]>;

This multiclass defined WriteJumpLd as port = ADLPPort00_06 + ADLPPort02_03_11, Lat = 1 + 5 = 6.
Same as previous one.

The reason why this code changed is some scheduling info of instructions ported from SKL use SKL store port (4) before this patch and is mapped to port(2,3,11) in this patch. This changes instructions group with same scheduling info thus the inferred code changed.

llvm/lib/Target/X86/X86SchedAlderlakeP.td

 def ADLPPort00_01_05       : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05]>;
 def ADLPPort00_01_05_06    : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05, ADLPPort06]>;
 def ADLPPort00_05          : ProcResGroup<[ADLPPort00, ADLPPort05]>;
 def ADLPPort00_05_06       : ProcResGroup<[ADLPPort00, ADLPPort05, ADLPPort06]>;
 def ADLPPort00_06          : ProcResGroup<[ADLPPort00, ADLPPort06]>;
 def ADLPPort01_05          : ProcResGroup<[ADLPPort01, ADLPPort05]>;
 def ADLPPort01_05_10       : ProcResGroup<[ADLPPort01, ADLPPort05, ADLPPort10]>;
 def ADLPPort02_03          : ProcResGroup<[ADLPPort02, ADLPPort03]>;
-def ADLPPort02_03_07       : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07]>;
 def ADLPPort02_03_11       : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort11]>;
 def ADLPPort07_08          : ProcResGroup<[ADLPPort07, ADLPPort08]>;
 
 // EU has 112 reservation stations.
 def ADLPPort00_01_05_06_10 : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05,
                                            ADLPPort06, ADLPPort10]> {
   let BufferSize = 112;
 }

 defm : ADLPWriteResPair<WriteFCmp, [ADLPPort00_01], 4, [1], 1, 7>;
 defm : ADLPWriteResPair<WriteFCmp64, [ADLPPort00_01], 4, [1], 1, 7>;
 defm : ADLPWriteResPair<WriteFCmp64X, [ADLPPort00_01], 4, [1], 1, 7>;
 defm : ADLPWriteResPair<WriteFCmp64Y, [ADLPPort00_01], 4, [1], 1, 8>;
 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 defm : ADLPWriteResPair<WriteFCmpX, [ADLPPort00_01], 4, [1], 1, 7>;
 defm : ADLPWriteResPair<WriteFCmpY, [ADLPPort00_01], 4, [1], 1, 8>;
 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
-def : WriteRes<WriteFCom, [ADLPPort05]>;
-defm : X86WriteRes<WriteFComLd, [ADLPPort02_03, ADLPPort05], 8, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteFCom, [ADLPPort05], 1, [1], 1, 7>;
 defm : ADLPWriteResPair<WriteFComX, [ADLPPort00], 3, [1]>;
 defm : ADLPWriteResPair<WriteFDiv, [ADLPPort00], 11, [1], 1, 7>;
 defm : ADLPWriteResPair<WriteFDiv64, [ADLPPort00], 14, [1]>;
 defm : ADLPWriteResPair<WriteFDiv64X, [ADLPPort00], 14, [1], 1, 6>;
 defm : ADLPWriteResPair<WriteFDiv64Y, [ADLPPort00], 14, [1], 1, 7>;
 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 defm : ADLPWriteResPair<WriteFDivX, [ADLPPort00], 11, [1], 1, 7>;
 defm : ADLPWriteResPair<WriteFDivY, [ADLPPort00], 11, [1], 1, 8>;

 defm : ADLPWriteResPair<WriteIMul64Reg, [ADLPPort01], 3, [1]>;
 defm : ADLPWriteResPair<WriteIMul8, [ADLPPort01], 3, [1]>;
 def : WriteRes<WriteIMulH, []> {
   let Latency = 3;
 }
 def : WriteRes<WriteIMulHLd, []> {
   let Latency = 3;
 }
-def : WriteRes<WriteJump, [ADLPPort00_06]>;
-defm : X86WriteRes<WriteJumpLd, [ADLPPort00_06, ADLPPort02_03], 6, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteJump, [ADLPPort00_06], 1, [1]>;
 def : WriteRes<WriteLAHFSAHF, [ADLPPort00_06]> {
   let Latency = 3;
 }
 defm : X86WriteRes<WriteLDMXCSR, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11], 7, [1, 1, 1, 1], 4>;
 def : WriteRes<WriteLEA, [ADLPPort01]>;
 defm : ADLPWriteResPair<WriteLZCNT, [ADLPPort01], 3, [1]>;
 def : WriteRes<WriteLoad, [ADLPPort02_03_11]> {
   let Latency = 5;

 defm : X86WriteRes<WriteVecStoreY, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
 defm : ADLPWriteResPair<WriteVecTest, [ADLPPort00, ADLPPort05], 4, [1, 1], 2>;
 defm : ADLPWriteResPair<WriteVecTestY, [ADLPPort00, ADLPPort05], 6, [1, 1], 2, 6>;
 defm : X86WriteRes<WriteXCHG, [ADLPPort00_01_05_06_10], 2, [3], 3>;
 def : WriteRes<WriteZero, []>;
 
 // Infered SchedWriteRes and InstRW definition.
 
-def ADLPWriteResGroup0 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04]> {
+def ADLPWriteResGroup0 : SchedWriteRes<[ADLPPort02_03, ADLPPort02_03_11, ADLPPort04, ADLPPort04_09]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup0], (instregex "^AA(D|N)D64mr$",
                                               "^A(X?)OR64mr$")>;
 
 def ADLPWriteResGroup1 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [2, 1, 1, 1, 1];
   let Latency = 12;
   let NumMicroOps = 6;
 }
 def : InstRW<[ADLPWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;
 
 def ADLPWriteResGroup2 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup2], (instregex "^JMP(16|32|64)m((_NT)?)$",
-                                              "^RET(16|32)$",
-                                              "^RORX(32|64)mi$")>;
+def : InstRW<[ADLPWriteResGroup2], (instregex "^RORX(32|64)mi$")>;
 def : InstRW<[ADLPWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
                                                                                                                                          "^AD(C|O)X(32|64)rm$")>;
 
 def ADLPWriteResGroup3 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 13;
   let NumMicroOps = 5;
 }
 def : InstRW<[ADLPWriteResGroup3], (instregex "^(ADC|SBB)8mi(8?)$")>;
def : InstRW<[ADLPWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^A(D|N)D8mr$",
                                                                                                                             "^(X?)OR8mr$")>;
 def : InstRW<[ADLPWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs SUB8mr)>;
 
 def ADLPWriteResGroup8 : SchedWriteRes<[ADLPPort01_05]> {
   let Latency = 3;
 }
 def : InstRW<[ADLPWriteResGroup8], (instregex "^(V?)(ADD|SUB)SSrr((_Int)?)$")>;
 
-def ADLPWriteResGroup9 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup9 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 10;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup9], (instregex "^ADD_F(32|64)m$",
                                               "^ILD_F(16|32|64)m$",
                                               "^SUB(R?)_F(32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup9, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
+                                                               "^(V?)PCMPGTQrm$")>;
 
-def ADLPWriteResGroup10 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup10 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [1, 2];
   let Latency = 13;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup10], (instregex "^ADD_FI(16|32)m$",
                                                "^SUB(R?)_FI(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup10, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;
 
 def ADLPWriteResGroup11 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
   let Latency = 2;
 }
 def : InstRW<[ADLPWriteResGroup11], (instregex "^AND(8|16|32|64)r(r|i8)$",
                                                "^AND(8|16|32|64)rr_REV$",
                                                "^(AND|TEST)(32|64)i32$",
                                                "^(AND|TEST)(8|32)ri$",
def : InstRW<[ADLPWriteResGroup40], (instrs DEC16r_alt,
                                             ST_FPrr,
                                             SYSCALL)>;
 
 def ADLPWriteResGroup41 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 7;
 }
 def : InstRW<[ADLPWriteResGroup41], (instrs DEC32r_alt)>;
 
-def ADLPWriteResGroup42 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
+def ADLPWriteResGroup42 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
   let Latency = 27;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup42], (instregex "^DIVR_F(32|64)m$")>;
 
-def ADLPWriteResGroup43 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup43 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 30;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup43], (instregex "^DIVR_FI(16|32)m$")>;
 
 def ADLPWriteResGroup44 : SchedWriteRes<[ADLPPort00]> {
   let Latency = 15;
 }
 def : InstRW<[ADLPWriteResGroup44], (instregex "^DIVR_F(P?)rST0$")>;
 def : InstRW<[ADLPWriteResGroup44], (instrs DIVR_FST0r)>;
 
 def ADLPWriteResGroup45 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
   let Latency = 20;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup45, ReadAfterVecLd], (instregex "^(V?)DIVSDrm_Int$")>;
 
-def ADLPWriteResGroup46 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
+def ADLPWriteResGroup46 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
   let Latency = 22;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup46], (instregex "^DIV_F(32|64)m$")>;
 
-def ADLPWriteResGroup47 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup47 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 25;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup47], (instregex "^DIV_FI(16|32)m$")>;
 
 def ADLPWriteResGroup48 : SchedWriteRes<[ADLPPort00]> {
   let Latency = 20;
 }

 
 def ADLPWriteResGroup51 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
   let Latency = 4;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup51], (instregex "^(V?)EXTRACTPSrr$")>;
 def : InstRW<[ADLPWriteResGroup51], (instrs MMX_PEXTRWrr)>;
 
-def ADLPWriteResGroup52 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
+def ADLPWriteResGroup52 : SchedWriteRes<[ADLPPort02_03, ADLPPort02_03_11, ADLPPort04, ADLPPort04_09, ADLPPort06]> {
   let Latency = 7;
   let NumMicroOps = 5;
 }
 def : InstRW<[ADLPWriteResGroup52], (instrs FARCALL64m)>;
 
-def ADLPWriteResGroup53 : SchedWriteRes<[ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup53 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort06]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup53], (instrs FARJMP64m,
                                             JMP64m_REX)>;
 
-def ADLPWriteResGroup54 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]> {
+def ADLPWriteResGroup54 : SchedWriteRes<[ADLPPort04, ADLPPort04_09]> {
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup54], (instregex "^(V?)MASKMOVDQU((64)?)$",
                                                "^ST_FP(32|64|80)m$")>;
 def : InstRW<[ADLPWriteResGroup54], (instrs FBSTPm,
                                             VMPTRSTm)>;
 
 def ADLPWriteResGroup55 : SchedWriteRes<[ADLPPort00_05]> {
   let ResourceCycles = [2];
   let Latency = 2;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup55], (instrs FDECSTP)>;
 
-def ADLPWriteResGroup56 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup56 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [1, 2];
   let Latency = 11;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup56], (instregex "^FICOM(P?)(16|32)m$")>;
 
 def ADLPWriteResGroup57 : SchedWriteRes<[ADLPPort00_05]>;
 def : InstRW<[ADLPWriteResGroup57], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$")>;
 def : InstRW<[ADLPWriteResGroup57], (instrs FINCSTP,
                                             FNOP)>;
 
-def ADLPWriteResGroup58 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort02_03]> {
+def ADLPWriteResGroup58 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort02_03_11]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup58], (instrs FLDCW16m)>;
 
-def ADLPWriteResGroup59 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort02_03]> {
-  let ResourceCycles = [2, 39, 5, 10, 8];
+def ADLPWriteResGroup59 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort00_06, ADLPPort02_03, ADLPPort02_03_11]> {
+  let ResourceCycles = [2, 5, 10, 39, 8];
   let Latency = 62;
   let NumMicroOps = 64;
 }
 def : InstRW<[ADLPWriteResGroup59], (instrs FLDENVm)>;
 
 def ADLPWriteResGroup60 : SchedWriteRes<[ADLPPort00_01_05_06]> {
   let ResourceCycles = [4];
   let Latency = 4;
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup60], (instrs FNCLEX)>;
 
 def ADLPWriteResGroup61 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort05]> {
   let ResourceCycles = [6, 3, 6];
   let Latency = 75;
   let NumMicroOps = 15;
 }
 def : InstRW<[ADLPWriteResGroup61], (instrs FNINIT)>;
 
-def ADLPWriteResGroup62 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
+def ADLPWriteResGroup62 : SchedWriteRes<[ADLPPort04, ADLPPort04_09, ADLPPort06]> {
   let Latency = 2;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup62], (instrs FNSTCW16m)>;
 
 def ADLPWriteResGroup63 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06]> {
   let Latency = 3;
   let NumMicroOps = 2;
 }
 def : InstRW<[ADLPWriteResGroup63], (instrs FNSTSW16r)>;
 
-def ADLPWriteResGroup64 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_07, ADLPPort04]> {
+def ADLPWriteResGroup64 : SchedWriteRes<[ADLPPort00, ADLPPort04, ADLPPort04_09]> {
   let Latency = 3;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup64], (instrs FNSTSWm)>;
 
-def ADLPWriteResGroup65 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
-  let ResourceCycles = [9, 30, 21, 1, 11, 11, 16, 1];
+def ADLPWriteResGroup65 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_06, ADLPPort01, ADLPPort04, ADLPPort04_09, ADLPPort05, ADLPPort06]> {
+  let ResourceCycles = [9, 11, 21, 1, 30, 11, 16, 1];
   let Latency = 106;
   let NumMicroOps = 100;
 }
 def : InstRW<[ADLPWriteResGroup65], (instrs FSTENVm)>;
 
-def ADLPWriteResGroup66 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
-  let ResourceCycles = [4, 47, 1, 2, 1, 33, 2];
+def ADLPWriteResGroup66 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_11, ADLPPort06]> {
+  let ResourceCycles = [4, 1, 2, 1, 47, 33, 2];
   let Latency = 63;
   let NumMicroOps = 90;
 }
 def : InstRW<[ADLPWriteResGroup66], (instrs FXRSTOR)>;
 
-def ADLPWriteResGroup67 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
-  let ResourceCycles = [4, 45, 1, 2, 1, 31, 4];
+def ADLPWriteResGroup67 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_11, ADLPPort06]> {
+  let ResourceCycles = [4, 1, 2, 1, 45, 31, 4];
   let Latency = 63;
   let NumMicroOps = 88;
 }
 def : InstRW<[ADLPWriteResGroup67], (instrs FXRSTOR64)>;
 
 def ADLPWriteResGroup68 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [2, 5, 10, 10, 2, 38, 5, 38];
   let Latency = AlderlakePModel.MaxLatency;

 def ADLPWriteResGroup77 : SchedWriteRes<[ADLPPort00_06]> {
   let NumMicroOps = 4;
 }
 def : InstRW<[ADLPWriteResGroup77], (instrs INC16r_alt)>;
 
 def ADLPWriteResGroup78 : SchedWriteRes<[ADLPPort02_03_11]> {
   let Latency = 7;
 }
-def : InstRW<[ADLPWriteResGroup78], (instregex "^(V?)MOV(D|SH|SL)DUPrm$",
+def : InstRW<[ADLPWriteResGroup78], (instregex "^LD_F(32|64|80)m$",
+                                               "^(V?)MOV(D|SH|SL)DUPrm$",
                                                "^VPBROADCAST(D|Q)rm$")>;
 def : InstRW<[ADLPWriteResGroup78], (instrs INC32r_alt,
                                             VBROADCASTSSrm)>;
 
 def ADLPWriteResGroup79 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [7, 6, 24, 17, 8, 1, 19, 1];
   let Latency = 20;
   let NumMicroOps = 83;

 
 def ADLPWriteResGroup82 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [5, 4, 8, 6, 2, 5, 7, 5];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 42;
 }
 def : InstRW<[ADLPWriteResGroup82], (instrs INVLPG)>;
 
-def ADLPWriteResGroup83 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort05]> {
+def ADLPWriteResGroup83 : SchedWriteRes<[ADLPPort04, ADLPPort04_09, ADLPPort05]> {
   let Latency = 4;
   let NumMicroOps = 3;
 }
 def : InstRW<[ADLPWriteResGroup83], (instregex "^IST(T?)_FP(16|32|64)m$",
                                                "^IST_F(16|32)m$")>;
 
 def ADLPWriteResGroup84 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_06]> {
   let Latency = 2;

 
 def ADLPWriteResGroup91 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
   let Latency = 71;
   let NumMicroOps = 87;
 }
 def : InstRW<[ADLPWriteResGroup91], (instrs LAR64rm)>;
 
-def ADLPWriteResGroup92 : SchedWriteRes<[ADLPPort02_03]> {
-  let Latency = 7;
-}
-def : InstRW<[ADLPWriteResGroup92], (instregex "^LD_F(32|64|80)m$")>;
-
-def ADLPWriteResGroup93 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup92 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup93], (instrs LEA16r)>;
+def : InstRW<[ADLPWriteResGroup92], (instrs LEA16r)>;
 
-def ADLPWriteResGroup94 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup93 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
   let ResourceCycles = [3, 1];
   let Latency = 6;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup94], (instregex "^LODS(B|W)$",
+def : InstRW<[ADLPWriteResGroup93], (instregex "^LODS(B|W)$",
                                                "^SCAS(B|L|Q|W)$")>;
-def : InstRW<[ADLPWriteResGroup94], (instrs LEAVE)>;
+def : InstRW<[ADLPWriteResGroup93], (instrs LEAVE)>;
 
-def ADLPWriteResGroup95 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup94 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
   let ResourceCycles = [2, 1];
   let Latency = 6;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup95], (instrs LEAVE64)>;
+def : InstRW<[ADLPWriteResGroup94], (instrs LEAVE64)>;
 
-def ADLPWriteResGroup96 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup95 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [1, 2, 4, 3, 2, 1, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 14;
 }
-def : InstRW<[ADLPWriteResGroup96], (instrs LGDT64m)>;
+def : InstRW<[ADLPWriteResGroup95], (instrs LGDT64m)>;
 
-def ADLPWriteResGroup97 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup96 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [1, 1, 5, 3, 2, 1, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 14;
 }
-def : InstRW<[ADLPWriteResGroup97], (instrs LIDT64m)>;
+def : InstRW<[ADLPWriteResGroup96], (instrs LIDT64m)>;
 
-def ADLPWriteResGroup98 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup97 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [5, 3, 2, 1, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 12;
 }
-def : InstRW<[ADLPWriteResGroup98], (instrs LLDT16m)>;
+def : InstRW<[ADLPWriteResGroup97], (instrs LLDT16m)>;
 
-def ADLPWriteResGroup99 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup98 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [1, 4, 3, 1, 1, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 11;
 }
-def : InstRW<[ADLPWriteResGroup99], (instrs LLDT16r)>;
+def : InstRW<[ADLPWriteResGroup98], (instrs LLDT16r)>;
 
-def ADLPWriteResGroup100 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup99 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 27;
 }
-def : InstRW<[ADLPWriteResGroup100], (instrs LMSW16m)>;
+def : InstRW<[ADLPWriteResGroup99], (instrs LMSW16m)>;
 
-def ADLPWriteResGroup101 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup100 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [5, 7, 1, 2, 5, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 22;
 }
-def : InstRW<[ADLPWriteResGroup101], (instrs LMSW16r)>;
+def : InstRW<[ADLPWriteResGroup100], (instrs LMSW16r)>;
 
-def ADLPWriteResGroup102 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup101 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
   let ResourceCycles = [2, 1];
   let Latency = 5;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup102], (instregex "^LODS(L|Q)$")>;
+def : InstRW<[ADLPWriteResGroup101], (instregex "^LODS(L|Q)$")>;
 
-def ADLPWriteResGroup103 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup102 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let ResourceCycles = [2, 4, 1];
   let Latency = 3;
   let NumMicroOps = 7;
 }
-def : InstRW<[ADLPWriteResGroup103], (instrs LOOP)>;
+def : InstRW<[ADLPWriteResGroup102], (instrs LOOP)>;
 
-def ADLPWriteResGroup104 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup103 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let ResourceCycles = [4, 6, 1];
   let Latency = 3;
   let NumMicroOps = 11;
 }
-def : InstRW<[ADLPWriteResGroup104], (instrs LOOPE)>;
+def : InstRW<[ADLPWriteResGroup103], (instrs LOOPE)>;
 
-def ADLPWriteResGroup105 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup104 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let ResourceCycles = [4, 6, 1];
   let Latency = 2;
   let NumMicroOps = 11;
 }
-def : InstRW<[ADLPWriteResGroup105], (instrs LOOPNE)>;
+def : InstRW<[ADLPWriteResGroup104], (instrs LOOPNE)>;
 
-def ADLPWriteResGroup106 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup105 : SchedWriteRes<[ADLPPort02_03, ADLPPort02_03_11, ADLPPort06]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup106], (instrs LRET64)>;
+def : InstRW<[ADLPWriteResGroup105], (instrs LRET64)>;
 
-def ADLPWriteResGroup107 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup106 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [1, 5, 3, 3, 1];
   let Latency = 70;
   let NumMicroOps = 13;
 }
-def : InstRW<[ADLPWriteResGroup107], (instregex "^LSL(16|32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup106], (instregex "^LSL(16|32|64)rm$")>;
 
-def ADLPWriteResGroup108 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup107 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [1, 4, 4, 3, 2, 1];
   let Latency = 63;
   let NumMicroOps = 15;
 }
-def : InstRW<[ADLPWriteResGroup108], (instregex "^LSL(16|32|64)rr$")>;
+def : InstRW<[ADLPWriteResGroup107], (instregex "^LSL(16|32|64)rr$")>;
 
-def ADLPWriteResGroup109 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup108 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 24;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup109], (instregex "^MMX_CVT(T?)PD2PIrm$")>;
+def : InstRW<[ADLPWriteResGroup108], (instregex "^MMX_CVT(T?)PD2PIrm$")>;
 
-def ADLPWriteResGroup110 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+def ADLPWriteResGroup109 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
   let Latency = 8;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup110], (instregex "^MMX_CVT(T?)PD2PIrr$")>;
+def : InstRW<[ADLPWriteResGroup109], (instregex "^MMX_CVT(T?)PD2PIrr$")>;
 
-def ADLPWriteResGroup111 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+def ADLPWriteResGroup110 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup111], (instrs MMX_CVTPI2PDrr)>;
+def : InstRW<[ADLPWriteResGroup110], (instrs MMX_CVTPI2PDrr)>;
 
-def ADLPWriteResGroup112 : SchedWriteRes<[ADLPPort00, ADLPPort00_01]> {
+def ADLPWriteResGroup111 : SchedWriteRes<[ADLPPort00, ADLPPort00_01]> {
   let Latency = 7;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup112], (instrs MMX_CVTPI2PSrr)>;
+def : InstRW<[ADLPWriteResGroup111], (instrs MMX_CVTPI2PSrr)>;
 
-def ADLPWriteResGroup113 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+def ADLPWriteResGroup112 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
   let Latency = 13;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup113], (instregex "^MMX_CVT(T?)PS2PIrm$")>;
+def : InstRW<[ADLPWriteResGroup112], (instregex "^MMX_CVT(T?)PS2PIrm$")>;
 
-def ADLPWriteResGroup114 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
+def ADLPWriteResGroup113 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup114], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
+def : InstRW<[ADLPWriteResGroup113], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
 
-def ADLPWriteResGroup115 : SchedWriteRes<[ADLPPort00, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup114 : SchedWriteRes<[ADLPPort00, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [2, 1, 1];
   let Latency = 12;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup115], (instregex "^MMX_MASKMOVQ((64)?)$")>;
+def : InstRW<[ADLPWriteResGroup114], (instregex "^MMX_MASKMOVQ((64)?)$")>;
 
-def ADLPWriteResGroup116 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup115 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 18;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup116], (instrs MMX_MOVD64mr)>;
+def : InstRW<[ADLPWriteResGroup115], (instrs MMX_MOVD64mr)>;
 
-def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup116 : SchedWriteRes<[ADLPPort02_03_11]> {
   let Latency = 8;
 }
-def : InstRW<[ADLPWriteResGroup117], (instregex "^MMX_MOV(D|Q)64rm$",
+def : InstRW<[ADLPWriteResGroup116], (instregex "^MMX_MOV(D|Q)64rm$",
                                                 "^VBROADCAST(F|I)128$",
                                                 "^VBROADCASTS(D|S)Yrm$",
                                                 "^VMOV(D|SH|SL)DUPYrm$",
                                                 "^VPBROADCAST(D|Q)Yrm$")>;
-def : InstRW<[ADLPWriteResGroup117], (instrs MMX_MOVD64to64rm)>;
+def : InstRW<[ADLPWriteResGroup116], (instrs MMX_MOVD64to64rm)>;
 
-def ADLPWriteResGroup118 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_05]> {
+def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_05]> {
   let Latency = 3;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup118], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>;
+def : InstRW<[ADLPWriteResGroup117], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>;
 
-def ADLPWriteResGroup119 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
+def ADLPWriteResGroup118 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
   let Latency = 3;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup119], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
+def : InstRW<[ADLPWriteResGroup118], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
 
-def ADLPWriteResGroup120 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup119 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [1, 2];
   let Latency = 12;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;
-def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
+def : InstRW<[ADLPWriteResGroup119, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;
+def : InstRW<[ADLPWriteResGroup119, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
 
-def ADLPWriteResGroup121 : SchedWriteRes<[ADLPPort05]> {
+def ADLPWriteResGroup120 : SchedWriteRes<[ADLPPort05]> {
   let ResourceCycles = [2];
   let Latency = 4;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup121], (instregex "^MMX_PACKSS(DW|WB)rr$")>;
-def : InstRW<[ADLPWriteResGroup121], (instrs MMX_PACKUSWBrr)>;
-def : InstRW<[ADLPWriteResGroup121, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrr)>;
+def : InstRW<[ADLPWriteResGroup120], (instregex "^MMX_PACKSS(DW|WB)rr$")>;
+def : InstRW<[ADLPWriteResGroup120], (instrs MMX_PACKUSWBrr)>;
+def : InstRW<[ADLPWriteResGroup120, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrr)>;
 
-def ADLPWriteResGroup122 : SchedWriteRes<[ADLPPort00_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup121 : SchedWriteRes<[ADLPPort00_05, ADLPPort02_03_11]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup122, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
+def : InstRW<[ADLPWriteResGroup121, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
 
-def ADLPWriteResGroup123 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup122 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [1, 1, 2];
   let Latency = 11;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup123, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
+def : InstRW<[ADLPWriteResGroup122, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
 
-def ADLPWriteResGroup124 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
+def ADLPWriteResGroup123 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
   let ResourceCycles = [1, 2];
   let Latency = 3;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup124], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
+def : InstRW<[ADLPWriteResGroup123], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
 
-def ADLPWriteResGroup125 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup124 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup125], (instregex "^VPBROADCAST(B|W)Yrm$")>;
-def : InstRW<[ADLPWriteResGroup125, ReadAfterLd], (instrs MMX_PINSRWrm)>;
-def : InstRW<[ADLPWriteResGroup125, ReadAfterVecYLd], (instrs VPALIGNRYrmi)>;
+def : InstRW<[ADLPWriteResGroup124], (instregex "^VPBROADCAST(B|W)Yrm$")>;
+def : InstRW<[ADLPWriteResGroup124, ReadAfterLd], (instrs MMX_PINSRWrm)>;
+def : InstRW<[ADLPWriteResGroup124, ReadAfterVecYLd], (instrs VPALIGNRYrmi)>;
 
-def ADLPWriteResGroup126 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup125 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
   let Latency = 5;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup126], (instregex "^MOV16ao(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup125], (instregex "^MOV16ao(16|32|64)$")>;
 
-def ADLPWriteResGroup127 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup126 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup127], (instregex "^PUSH(F|G)S(16|32)$")>;
-def : InstRW<[ADLPWriteResGroup127], (instrs MOV16ms,
+def : InstRW<[ADLPWriteResGroup126], (instregex "^PUSH(F|G)S(16|32)$")>;
+def : InstRW<[ADLPWriteResGroup126], (instrs MOV16ms,
                                              MOVBE32mr)>;
 
-def ADLPWriteResGroup128 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup127 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup128], (instregex "^MOV(16|32|64)rs$",
+def : InstRW<[ADLPWriteResGroup127], (instregex "^MOV(16|32|64)rs$",
                                                 "^S(TR|LDT)16r$")>;
 
-def ADLPWriteResGroup129 : SchedWriteRes<[ADLPPort02_03_11]>;
-def : InstRW<[ADLPWriteResGroup129], (instregex "^MOV32ao(16|32|64)$")>;
-def : InstRW<[ADLPWriteResGroup129], (instrs MOV64ao64)>;
+def ADLPWriteResGroup128 : SchedWriteRes<[ADLPPort02_03_11]>;
+def : InstRW<[ADLPWriteResGroup128], (instregex "^MOV32ao(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup128], (instrs MOV64ao64)>;
 
-def ADLPWriteResGroup130 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup129 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup130], (instregex "^MOV(8|32)o(16|32)a$",
+def : InstRW<[ADLPWriteResGroup129], (instregex "^MOV(8|32)o(16|32)a$",
                                                 "^MOV(8|32|64)o64a$")>;
 
-def ADLPWriteResGroup131 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+def ADLPWriteResGroup130 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
   let Latency = 0;
 }
-def : InstRW<[ADLPWriteResGroup131], (instregex "^MOV32rr((_REV)?)$",
+def : InstRW<[ADLPWriteResGroup130], (instregex "^MOV32rr((_REV)?)$",
                                                 "^MOVZX(32|64)rr8$")>;
-def : InstRW<[ADLPWriteResGroup131], (instrs MOVZX32rr8_NOREX)>;
+def : InstRW<[ADLPWriteResGroup130], (instrs MOVZX32rr8_NOREX)>;
 
-def ADLPWriteResGroup132 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup131 : SchedWriteRes<[ADLPPort02_03_11]> {
   let Latency = 5;
 }
-def : InstRW<[ADLPWriteResGroup132], (instrs MOV64ao32)>;
+def : InstRW<[ADLPWriteResGroup131], (instrs MOV64ao32)>;
 
-def ADLPWriteResGroup133 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup132 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
   let Latency = 217;
   let NumMicroOps = 48;
 }
-def : InstRW<[ADLPWriteResGroup133], (instrs MOV64dr)>;
+def : InstRW<[ADLPWriteResGroup132], (instrs MOV64dr)>;
 
-def ADLPWriteResGroup134 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup133 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup134], (instrs MOV64o32a)>;
+def : InstRW<[ADLPWriteResGroup133], (instrs MOV64o32a)>;
 
-def ADLPWriteResGroup135 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort05]> {
+def ADLPWriteResGroup134 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort05]> {
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup135], (instrs MOV64rc)>;
+def : InstRW<[ADLPWriteResGroup134], (instrs MOV64rc)>;
 
-def ADLPWriteResGroup136 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
+def ADLPWriteResGroup135 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
   let ResourceCycles = [3, 4, 8, 4, 2, 3];
   let Latency = 181;
   let NumMicroOps = 24;
 }
-def : InstRW<[ADLPWriteResGroup136], (instrs MOV64rd)>;
+def : InstRW<[ADLPWriteResGroup135], (instrs MOV64rd)>;
 
-def ADLPWriteResGroup137 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup136 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup137], (instregex "^MOV8ao(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup136], (instregex "^MOV8ao(16|32|64)$")>;
 
-def ADLPWriteResGroup138 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup137 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 13;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup138], (instregex "^MOV8m(i|r)$")>;
-def : InstRW<[ADLPWriteResGroup138], (instrs MOV8mr_NOREX)>;
+def : InstRW<[ADLPWriteResGroup137], (instregex "^MOV8m(i|r)$")>;
+def : InstRW<[ADLPWriteResGroup137], (instrs MOV8mr_NOREX)>;
 
-def ADLPWriteResGroup139 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup138 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup139], (instrs MOVBE16mr)>;
+def : InstRW<[ADLPWriteResGroup138], (instrs MOVBE16mr)>;
 
-def ADLPWriteResGroup140 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup139 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup140], (instrs MOVBE16rm)>;
+def : InstRW<[ADLPWriteResGroup139], (instrs MOVBE16rm)>;
 
-def ADLPWriteResGroup141 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup140 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup141], (instrs MOVBE32rm)>;
+def : InstRW<[ADLPWriteResGroup140], (instrs MOVBE32rm)>;
 
-def ADLPWriteResGroup142 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup141 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup142], (instrs MOVBE64mr,
+def : InstRW<[ADLPWriteResGroup141], (instrs MOVBE64mr,
                                              PUSHF16,
                                              SLDT16m,
                                              STRm)>;
 
-def ADLPWriteResGroup143 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup142 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup143], (instrs MOVBE64rm)>;
+def : InstRW<[ADLPWriteResGroup142], (instrs MOVBE64rm)>;
 
-def ADLPWriteResGroup144 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup143 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup144], (instregex "^MOVDIR64B(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup143], (instregex "^MOVDIR64B(16|32|64)$")>;
 
-def ADLPWriteResGroup145 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup144 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 511;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup145], (instrs MOVDIRI32)>;
+def : InstRW<[ADLPWriteResGroup144], (instrs MOVDIRI32)>;
 
-def ADLPWriteResGroup146 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup145 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 514;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup146], (instrs MOVDIRI64)>;
+def : InstRW<[ADLPWriteResGroup145], (instrs MOVDIRI64)>;
 
-def ADLPWriteResGroup147 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup146 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
   let Latency = 8;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup147, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$",
+def : InstRW<[ADLPWriteResGroup146, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$",
                                                                  "^(V?)SHUFP(D|S)rmi$")>;
 
-def ADLPWriteResGroup148 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup147 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 512;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup148], (instrs MOVNTDQmr)>;
+def : InstRW<[ADLPWriteResGroup147], (instrs MOVNTDQmr)>;
 
-def ADLPWriteResGroup149 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup148 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 518;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup149], (instrs MOVNTImr)>;
+def : InstRW<[ADLPWriteResGroup148], (instrs MOVNTImr)>;
 
-def ADLPWriteResGroup150 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup149 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [4, 1, 1, 1];
   let Latency = 8;
   let NumMicroOps = 7;
 }
-def : InstRW<[ADLPWriteResGroup150], (instrs MOVSB)>;
+def : InstRW<[ADLPWriteResGroup149], (instrs MOVSB)>;
 
-def ADLPWriteResGroup151 : SchedWriteRes<[ADLPPort00_01_05]>;
-def : InstRW<[ADLPWriteResGroup151], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
+def ADLPWriteResGroup150 : SchedWriteRes<[ADLPPort00_01_05]>;
+def : InstRW<[ADLPWriteResGroup150], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
                                                 "^(V?)P(ADD|SUB)(B|D|Q|W)rr$",
                                                 "^VP(ADD|SUB)(B|D|Q|W)Yrr$")>;
-def : InstRW<[ADLPWriteResGroup151], (instrs VPBLENDDrri)>;
+def : InstRW<[ADLPWriteResGroup150], (instrs VPBLENDDrri)>;
 
-def ADLPWriteResGroup152 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup151 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [4, 1, 1, 1];
   let Latency = 7;
   let NumMicroOps = 7;
 }
-def : InstRW<[ADLPWriteResGroup152], (instregex "^MOVS(L|Q|W)$")>;
+def : InstRW<[ADLPWriteResGroup151], (instregex "^MOVS(L|Q|W)$")>;
 
-def ADLPWriteResGroup153 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup152 : SchedWriteRes<[ADLPPort02_03_11]> {
   let Latency = 6;
 }
-def : InstRW<[ADLPWriteResGroup153], (instregex "^MOVSX(16|32|64)rm(16|32)$",
+def : InstRW<[ADLPWriteResGroup152], (instregex "^MOVSX(16|32|64)rm(16|32)$",
                                                 "^MOVSX(32|64)rm8$")>;
-def : InstRW<[ADLPWriteResGroup153], (instrs MOVSX32rm8_NOREX)>;
+def : InstRW<[ADLPWriteResGroup152], (instrs MOVSX32rm8_NOREX)>;
 
-def ADLPWriteResGroup154 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup153 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup154], (instrs MOVSX16rm8)>;
+def : InstRW<[ADLPWriteResGroup153], (instrs MOVSX16rm8)>;
 
-def ADLPWriteResGroup155 : SchedWriteRes<[ADLPPort01_05_10]>;
-def : InstRW<[ADLPWriteResGroup155], (instregex "^MOVSX(16|32|64)rr(8|16|32)$")>;
-def : InstRW<[ADLPWriteResGroup155], (instrs MOVSX32rr8_NOREX)>;
+def ADLPWriteResGroup154 : SchedWriteRes<[ADLPPort01_05_10]>;
+def : InstRW<[ADLPWriteResGroup154], (instregex "^MOVSX(16|32|64)rr(8|16|32)$")>;
+def : InstRW<[ADLPWriteResGroup154], (instrs MOVSX32rr8_NOREX)>;
 
-def ADLPWriteResGroup156 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
+def ADLPWriteResGroup155 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
   let Latency = 11;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup156], (instregex "^MUL_F(32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup155], (instregex "^MUL_F(32|64)m$")>;
 
-def ADLPWriteResGroup157 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup156 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 14;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup157], (instregex "^MUL_FI(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup156], (instregex "^MUL_FI(16|32)m$")>;
 
-def ADLPWriteResGroup158 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup157 : SchedWriteRes<[ADLPPort00]> {
   let Latency = 4;
 }
-def : InstRW<[ADLPWriteResGroup158], (instregex "^MUL_F(P?)rST0$")>;
-def : InstRW<[ADLPWriteResGroup158], (instrs MUL_FST0r)>;
+def : InstRW<[ADLPWriteResGroup157], (instregex "^MUL_F(P?)rST0$")>;
+def : InstRW<[ADLPWriteResGroup157], (instrs MUL_FST0r)>;
 
-def ADLPWriteResGroup159 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort05, ADLPPort06]> {
+def ADLPWriteResGroup158 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort05, ADLPPort06]> {
   let ResourceCycles = [7, 1, 2];
   let Latency = 20;
   let NumMicroOps = 10;
 }
-def : InstRW<[ADLPWriteResGroup159], (instrs MWAITrr)>;
+def : InstRW<[ADLPWriteResGroup158], (instrs MWAITrr)>;
 
-def ADLPWriteResGroup160 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup159 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
   let Latency = 35;
   let NumMicroOps = 79;
 }
-def : InstRW<[ADLPWriteResGroup160], (instrs OUT16ir)>;
+def : InstRW<[ADLPWriteResGroup159], (instrs OUT16ir)>;
 
-def ADLPWriteResGroup161 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup160 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [6, 6, 27, 15, 7, 1, 16, 1];
   let Latency = 35;
   let NumMicroOps = 79;
 }
-def : InstRW<[ADLPWriteResGroup161], (instrs OUT16rr)>;
+def : InstRW<[ADLPWriteResGroup160], (instrs OUT16rr)>;
 
-def ADLPWriteResGroup162 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup161 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
   let Latency = 35;
   let NumMicroOps = 85;
 }
-def : InstRW<[ADLPWriteResGroup162], (instrs OUT32ir)>;
+def : InstRW<[ADLPWriteResGroup161], (instrs OUT32ir)>;
 
-def ADLPWriteResGroup163 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup162 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [6, 6, 29, 15, 9, 1, 18, 1];
   let Latency = 35;
   let NumMicroOps = 85;
 }
-def : InstRW<[ADLPWriteResGroup163], (instrs OUT32rr)>;
+def : InstRW<[ADLPWriteResGroup162], (instrs OUT32rr)>;
 
-def ADLPWriteResGroup164 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup163 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
   let Latency = 35;
   let NumMicroOps = 73;
 }
-def : InstRW<[ADLPWriteResGroup164], (instrs OUT8ir)>;
+def : InstRW<[ADLPWriteResGroup163], (instrs OUT8ir)>;
 
-def ADLPWriteResGroup165 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup164 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [5, 5, 26, 15, 5, 1, 15, 1];
   let Latency = 35;
   let NumMicroOps = 73;
 }
-def : InstRW<[ADLPWriteResGroup165], (instrs OUT8rr)>;
+def : InstRW<[ADLPWriteResGroup164], (instrs OUT8rr)>;
 
-def ADLPWriteResGroup166 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup165 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [7, 6, 25, 16, 7, 1, 17, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 80;
 }
-def : InstRW<[ADLPWriteResGroup166], (instrs OUTSB)>;
+def : InstRW<[ADLPWriteResGroup165], (instrs OUTSB)>;
 
-def ADLPWriteResGroup167 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup166 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [7, 6, 28, 16, 10, 1, 20, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 89;
 }
-def : InstRW<[ADLPWriteResGroup167], (instrs OUTSL)>;
+def : InstRW<[ADLPWriteResGroup166], (instrs OUTSL)>;
 
-def ADLPWriteResGroup168 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup167 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 83;
 }
-def : InstRW<[ADLPWriteResGroup168], (instrs OUTSW)>;
+def : InstRW<[ADLPWriteResGroup167], (instrs OUTSW)>;
 
-def ADLPWriteResGroup169 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
-  let Latency = 10;
-  let NumMicroOps = 2;
-}
-def : InstRW<[ADLPWriteResGroup169, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
-                                                                 "^(V?)PCMPGTQrm$")>;
-
-def ADLPWriteResGroup170 : SchedWriteRes<[ADLPPort05]> {
+def ADLPWriteResGroup168 : SchedWriteRes<[ADLPPort05]> {
   let Latency = 3;
 }
-def : InstRW<[ADLPWriteResGroup170], (instregex "^(V?)PACK(S|U)S(DW|WB)rr$",
+def : InstRW<[ADLPWriteResGroup168], (instregex "^(V?)PACK(S|U)S(DW|WB)rr$",
                                                 "^(V?)PCMPGTQrr$",
                                                 "^VPACK(S|U)S(DW|WB)Yrr$")>;
-def : InstRW<[ADLPWriteResGroup170], (instrs VPCMPGTQYrr)>;
+def : InstRW<[ADLPWriteResGroup168], (instrs VPCMPGTQYrr)>;
 
-def ADLPWriteResGroup171 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup169 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
   let Latency = 8;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup171, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$")>;
-def : InstRW<[ADLPWriteResGroup171, ReadAfterVecXLd], (instrs VPBLENDDrmi)>;
+def : InstRW<[ADLPWriteResGroup169, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$")>;
+def : InstRW<[ADLPWriteResGroup169, ReadAfterVecXLd], (instrs VPBLENDDrmi)>;
 
-def ADLPWriteResGroup172 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup170 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 8;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup172], (instregex "^VPBROADCAST(B|W)rm$")>;
-def : InstRW<[ADLPWriteResGroup172, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$")>;
+def : InstRW<[ADLPWriteResGroup170], (instregex "^VPBROADCAST(B|W)rm$")>;
+def : InstRW<[ADLPWriteResGroup170, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$")>;
 
-def ADLPWriteResGroup173 : SchedWriteRes<[ADLPPort05]>;
-def : InstRW<[ADLPWriteResGroup173], (instregex "^(V?)PALIGNRrri$",
+def ADLPWriteResGroup171 : SchedWriteRes<[ADLPPort05]>;
+def : InstRW<[ADLPWriteResGroup171], (instregex "^(V?)PALIGNRrri$",
                                                 "^VPBROADCAST(B|D|Q|W)rr$")>;
-def : InstRW<[ADLPWriteResGroup173], (instrs VPALIGNRYrri)>;
+def : InstRW<[ADLPWriteResGroup171], (instrs VPALIGNRYrri)>;
 
-def ADLPWriteResGroup174 : SchedWriteRes<[ADLPPort00_06, ADLPPort05]> {
+def ADLPWriteResGroup172 : SchedWriteRes<[ADLPPort00_06, ADLPPort05]> {
   let Latency = 4;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup174], (instrs PAUSE)>;
+def : InstRW<[ADLPWriteResGroup172], (instrs PAUSE)>;
 
-def ADLPWriteResGroup175 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup173 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
   let Latency = 8;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup175, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup173, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
 
-def ADLPWriteResGroup176 : SchedWriteRes<[ADLPPort01_05, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup174 : SchedWriteRes<[ADLPPort01_05, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup176], (instregex "^(V?)PEXTR(D|Q)mr$")>;
+def : InstRW<[ADLPWriteResGroup174], (instregex "^(V?)PEXTR(D|Q)mr$")>;
 
-def ADLPWriteResGroup177 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup175 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
   let ResourceCycles = [1, 2, 1];
   let Latency = 9;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup177, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
+def : InstRW<[ADLPWriteResGroup175, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
 
-def ADLPWriteResGroup178 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05]> {
+def ADLPWriteResGroup176 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05]> {
   let ResourceCycles = [1, 2];
   let Latency = 2;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup178], (instregex "^(V?)PH(ADD|SUB)SWrr$",
+def : InstRW<[ADLPWriteResGroup176], (instregex "^(V?)PH(ADD|SUB)SWrr$",
                                                 "^VPH(ADD|SUB)SWYrr$")>;
 
-def ADLPWriteResGroup179 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup177 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 12;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup179], (instregex "^POP(16|32|64)rmm$",
+def : InstRW<[ADLPWriteResGroup177], (instregex "^POP(16|32|64)rmm$",
                                                 "^PUSH(16|32)rmm$")>;
 
-def ADLPWriteResGroup180 : SchedWriteRes<[ADLPPort02_03]> {
-  let Latency = 5;
-}
-def : InstRW<[ADLPWriteResGroup180], (instregex "^POPA(16|32)$",
-                                                "^PREFETCHIT(0|1)$")>;
-def : InstRW<[ADLPWriteResGroup180], (instrs POPF32)>;
-
-def ADLPWriteResGroup181 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup178 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
   let ResourceCycles = [6, 2, 1, 1];
   let Latency = 5;
   let NumMicroOps = 10;
 }
-def : InstRW<[ADLPWriteResGroup181], (instrs POPF16)>;
+def : InstRW<[ADLPWriteResGroup178], (instrs POPF16)>;
 
-def ADLPWriteResGroup182 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup179 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
   let ResourceCycles = [2, 1, 1];
   let Latency = 5;
   let NumMicroOps = 7;
 }
-def : InstRW<[ADLPWriteResGroup182], (instrs POPF64)>;
+def : InstRW<[ADLPWriteResGroup179], (instrs POPF64)>;
 
-def ADLPWriteResGroup183 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup180 : SchedWriteRes<[ADLPPort02_03_11]> {
   let Latency = 0;
 }
-def : InstRW<[ADLPWriteResGroup183], (instregex "^PREFETCHT(0|1|2)$")>;
-def : InstRW<[ADLPWriteResGroup183], (instrs PREFETCHNTA)>;
+def : InstRW<[ADLPWriteResGroup180], (instregex "^PREFETCHT(0|1|2)$")>;
+def : InstRW<[ADLPWriteResGroup180], (instrs PREFETCHNTA)>;
 
-def ADLPWriteResGroup184 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
+def ADLPWriteResGroup181 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
   let ResourceCycles = [1, 1, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup184], (instregex "^PTWRITE((64)?)m$")>;
+def : InstRW<[ADLPWriteResGroup181], (instregex "^PTWRITE((64)?)m$")>;
 
-def ADLPWriteResGroup185 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
+def ADLPWriteResGroup182 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
   let ResourceCycles = [1, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup185], (instrs PTWRITE64r)>;
+def : InstRW<[ADLPWriteResGroup182], (instrs PTWRITE64r)>;
 
-def ADLPWriteResGroup186 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
+def ADLPWriteResGroup183 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
   let ResourceCycles = [2, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup186], (instrs PTWRITEr)>;
+def : InstRW<[ADLPWriteResGroup183], (instrs PTWRITEr)>;
 
-def ADLPWriteResGroup187 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup184 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup187], (instregex "^PUSH64r((mr)?)$")>;
+def : InstRW<[ADLPWriteResGroup184], (instregex "^PUSH64r((mr)?)$")>;
 
-def ADLPWriteResGroup188 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup185 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup188], (instrs PUSH64rmm)>;
+def : InstRW<[ADLPWriteResGroup185], (instrs PUSH64rmm)>;
 
-def ADLPWriteResGroup189 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]>;
-def : InstRW<[ADLPWriteResGroup189], (instregex "^PUSHA(16|32)$",
+def ADLPWriteResGroup186 : SchedWriteRes<[ADLPPort04, ADLPPort04_09]>;
+def : InstRW<[ADLPWriteResGroup186], (instregex "^PUSHA(16|32)$",
                                                 "^ST_F(32|64)m$")>;
-def : InstRW<[ADLPWriteResGroup189], (instrs PUSHF32)>;
+def : InstRW<[ADLPWriteResGroup186], (instrs PUSHF32)>;
 
-def ADLPWriteResGroup190 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup187 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 4;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup190], (instrs PUSHF64)>;
+def : InstRW<[ADLPWriteResGroup187], (instrs PUSHF64)>;
 
-def ADLPWriteResGroup191 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup188 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup191], (instregex "^PUSH(F|G)S64$")>;
+def : InstRW<[ADLPWriteResGroup188], (instregex "^PUSH(F|G)S64$")>;
 
-def ADLPWriteResGroup192 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup189 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let ResourceCycles = [2, 3, 2];
   let Latency = 8;
   let NumMicroOps = 7;
 }
-def : InstRW<[ADLPWriteResGroup192], (instregex "^RC(L|R)(16|32|64)rCL$")>;
+def : InstRW<[ADLPWriteResGroup189], (instregex "^RC(L|R)(16|32|64)rCL$")>;
 
-def ADLPWriteResGroup193 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup190 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
   let ResourceCycles = [1, 2];
   let Latency = 13;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup193, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
+def : InstRW<[ADLPWriteResGroup190, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
 
-def ADLPWriteResGroup194 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup191 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let ResourceCycles = [1, 5, 2];
   let Latency = 20;
   let NumMicroOps = 8;
 }
-def : InstRW<[ADLPWriteResGroup194, WriteRMW], (instrs RCL8mCL)>;
+def : InstRW<[ADLPWriteResGroup191, WriteRMW], (instrs RCL8mCL)>;
 
-def ADLPWriteResGroup195 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup192 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let ResourceCycles = [2, 5, 2];
   let Latency = 7;
   let NumMicroOps = 9;
 }
-def : InstRW<[ADLPWriteResGroup195], (instrs RCL8rCL)>;
+def : InstRW<[ADLPWriteResGroup192], (instrs RCL8rCL)>;
 
-def ADLPWriteResGroup196 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup193 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let ResourceCycles = [2, 4, 3];
   let Latency = 20;
   let NumMicroOps = 9;
 }
-def : InstRW<[ADLPWriteResGroup196, WriteRMW], (instrs RCR8mCL)>;
+def : InstRW<[ADLPWriteResGroup193, WriteRMW], (instrs RCR8mCL)>;
 
-def ADLPWriteResGroup197 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup194 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let ResourceCycles = [3, 4, 3];
   let Latency = 9;
   let NumMicroOps = 10;
 }
-def : InstRW<[ADLPWriteResGroup197], (instrs RCR8rCL)>;
+def : InstRW<[ADLPWriteResGroup194], (instrs RCR8rCL)>;
 
-def ADLPWriteResGroup198 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort01_05_10, ADLPPort05]> {
+def ADLPWriteResGroup195 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort01_05_10, ADLPPort05]> {
   let ResourceCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 54;
 }
-def : InstRW<[ADLPWriteResGroup198], (instrs RDMSR)>;
+def : InstRW<[ADLPWriteResGroup195], (instrs RDMSR)>;
 
-def ADLPWriteResGroup199 : SchedWriteRes<[ADLPPort01]> {
+def ADLPWriteResGroup196 : SchedWriteRes<[ADLPPort01]> {
   let Latency = AlderlakePModel.MaxLatency;
 }
-def : InstRW<[ADLPWriteResGroup199], (instrs RDPID64)>;
+def : InstRW<[ADLPWriteResGroup196], (instrs RDPID64)>;
 
-def ADLPWriteResGroup200 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup197 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup200], (instrs RDPKRUr)>;
+def : InstRW<[ADLPWriteResGroup197], (instrs RDPKRUr)>;
 
-def ADLPWriteResGroup201 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup198 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
   let ResourceCycles = [9, 6, 2, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 18;
 }
-def : InstRW<[ADLPWriteResGroup201], (instrs RDPMC)>;
+def : InstRW<[ADLPWriteResGroup198], (instrs RDPMC)>;
 
-def ADLPWriteResGroup202 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup199 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
   let Latency = 1386;
   let NumMicroOps = 25;
 }
-def : InstRW<[ADLPWriteResGroup202], (instrs RDRAND16r)>;
+def : InstRW<[ADLPWriteResGroup199], (instrs RDRAND16r)>;
 
-def ADLPWriteResGroup203 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup200 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 25;
 }
-def : InstRW<[ADLPWriteResGroup203], (instregex "^RDRAND(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup200], (instregex "^RDRAND(32|64)r$")>;
 
-def ADLPWriteResGroup204 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup201 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
   let Latency = 1381;
   let NumMicroOps = 25;
 }
-def : InstRW<[ADLPWriteResGroup204], (instrs RDSEED16r)>;
+def : InstRW<[ADLPWriteResGroup201], (instrs RDSEED16r)>;
 
-def ADLPWriteResGroup205 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup202 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 25;
 }
-def : InstRW<[ADLPWriteResGroup205], (instregex "^RDSEED(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup202], (instregex "^RDSEED(32|64)r$")>;
 
-def ADLPWriteResGroup206 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup203 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
   let ResourceCycles = [5, 6, 3, 1];
   let Latency = 18;
   let NumMicroOps = 15;
 }
-def : InstRW<[ADLPWriteResGroup206], (instrs RDTSC)>;
+def : InstRW<[ADLPWriteResGroup203], (instrs RDTSC)>;
 
-def ADLPWriteResGroup207 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup204 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
   let ResourceCycles = [2, 2, 1, 2, 7, 4, 3];
   let Latency = 42;
   let NumMicroOps = 21;
 }
-def : InstRW<[ADLPWriteResGroup207], (instrs RDTSCP)>;
+def : InstRW<[ADLPWriteResGroup204], (instrs RDTSCP)>;
 
-def ADLPWriteResGroup208 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup205 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
   let Latency = 7;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup208], (instrs RET64)>;
+def : InstRW<[ADLPWriteResGroup205], (instrs RET64)>;
 
-def ADLPWriteResGroup209 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup206 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
   let ResourceCycles = [2, 1];
   let Latency = 6;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup209], (instregex "^RETI(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup206], (instregex "^RETI(16|32|64)$")>;
 
-def ADLPWriteResGroup210 : SchedWriteRes<[]>;
-def : InstRW<[ADLPWriteResGroup210], (instrs REX64_PREFIX)>;
+def ADLPWriteResGroup207 : SchedWriteRes<[]>;
+def : InstRW<[ADLPWriteResGroup207], (instrs REX64_PREFIX)>;
 
-def ADLPWriteResGroup211 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup208 : SchedWriteRes<[ADLPPort00_06]> {
   let ResourceCycles = [2];
   let Latency = 12;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup211, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
+def : InstRW<[ADLPWriteResGroup208, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
 
-def ADLPWriteResGroup212 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup209 : SchedWriteRes<[ADLPPort00_06]> {
   let ResourceCycles = [2];
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup212], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
+def : InstRW<[ADLPWriteResGroup209], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
 
-def ADLPWriteResGroup213 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup210 : SchedWriteRes<[ADLPPort00_06]> {
   let ResourceCycles = [2];
   let Latency = 13;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup213, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
+def : InstRW<[ADLPWriteResGroup210, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
                                                           "^(RO|SH)L8mCL$",
                                                           "^(RO|SA|SH)R8mCL$")>;
 
-def ADLPWriteResGroup214 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup211 : SchedWriteRes<[ADLPPort00_06]> {
   let ResourceCycles = [2];
   let Latency = 4;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup214], (instrs SAHF)>;
+def : InstRW<[ADLPWriteResGroup211], (instrs SAHF)>;
 
-def ADLPWriteResGroup215 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup212 : SchedWriteRes<[ADLPPort00_06]> {
   let Latency = 13;
 }
-def : InstRW<[ADLPWriteResGroup215, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",
+def : InstRW<[ADLPWriteResGroup212, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",
                                                           "^SHL8m(1|i)$")>;
 
-def ADLPWriteResGroup216 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup213 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
   let Latency = 8;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup216, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",
+def : InstRW<[ADLPWriteResGroup213, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",
                                                                                                                               "^SHLX(32|64)rm$")>;
 
-def ADLPWriteResGroup217 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup214 : SchedWriteRes<[ADLPPort00_06]> {
   let Latency = 3;
 }
-def : InstRW<[ADLPWriteResGroup217], (instregex "^S(A|H)RX(32|64)rr$",
+def : InstRW<[ADLPWriteResGroup214], (instregex "^S(A|H)RX(32|64)rr$",
                                                 "^SHLX(32|64)rr$")>;
 
-def ADLPWriteResGroup218 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup215 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [2, 2, 1, 1, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 7;
 }
-def : InstRW<[ADLPWriteResGroup218], (instrs SERIALIZE)>;
+def : InstRW<[ADLPWriteResGroup215], (instrs SERIALIZE)>;
 
-def ADLPWriteResGroup219 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup216 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup219], (instrs SFENCE)>;
+def : InstRW<[ADLPWriteResGroup216], (instrs SFENCE)>;
 
-def ADLPWriteResGroup220 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup217 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [1, 2, 2, 2];
   let Latency = 21;
   let NumMicroOps = 7;
 }
-def : InstRW<[ADLPWriteResGroup220], (instregex "^S(G|I)DT64m$")>;
+def : InstRW<[ADLPWriteResGroup217], (instregex "^S(G|I)DT64m$")>;
 
-def ADLPWriteResGroup221 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup218 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 9;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup221, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;
+def : InstRW<[ADLPWriteResGroup218, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;
 
-def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort05]> {
+def ADLPWriteResGroup219 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort05]> {
   let Latency = 2;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup222], (instrs SHA1MSG1rr)>;
+def : InstRW<[ADLPWriteResGroup219], (instrs SHA1MSG1rr)>;
 
-def ADLPWriteResGroup223 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup220 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11]> {
   let ResourceCycles = [2, 2, 1, 2, 1];
   let Latency = 13;
   let NumMicroOps = 8;
 }
-def : InstRW<[ADLPWriteResGroup223, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
+def : InstRW<[ADLPWriteResGroup220, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
 
-def ADLPWriteResGroup224 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
+def ADLPWriteResGroup221 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
   let ResourceCycles = [2, 2, 1, 2];
   let Latency = 6;
   let NumMicroOps = 7;
 }
-def : InstRW<[ADLPWriteResGroup224], (instrs SHA1MSG2rr)>;
+def : InstRW<[ADLPWriteResGroup221], (instrs SHA1MSG2rr)>;
 
-def ADLPWriteResGroup225 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
   let Latency = 8;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup225, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;
+def : InstRW<[ADLPWriteResGroup222, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;
 
-def ADLPWriteResGroup226 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05]> {
+def ADLPWriteResGroup223 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05]> {
   let Latency = 3;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup226], (instrs SHA1NEXTErr)>;
+def : InstRW<[ADLPWriteResGroup223], (instrs SHA1NEXTErr)>;
 
-def ADLPWriteResGroup227 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup224 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 13;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup227, ReadAfterVecXLd], (instrs SHA1RNDS4rmi,
+def : InstRW<[ADLPWriteResGroup224, ReadAfterVecXLd], (instrs SHA1RNDS4rmi,
                                                               SHA256RNDS2rm)>;
 
-def ADLPWriteResGroup228 : SchedWriteRes<[ADLPPort05]> {
+def ADLPWriteResGroup225 : SchedWriteRes<[ADLPPort05]> {
   let Latency = 6;
 }
-def : InstRW<[ADLPWriteResGroup228], (instrs SHA1RNDS4rri,
+def : InstRW<[ADLPWriteResGroup225], (instrs SHA1RNDS4rri,
                                              SHA256RNDS2rr)>;
 
-def ADLPWriteResGroup229 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup226 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11, ADLPPort05]> {
   let ResourceCycles = [3, 2, 1, 1, 1];
   let Latency = 12;
   let NumMicroOps = 8;
 }
-def : InstRW<[ADLPWriteResGroup229, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
+def : InstRW<[ADLPWriteResGroup226, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
 
-def ADLPWriteResGroup230 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort05]> {
+def ADLPWriteResGroup227 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort05]> {
   let ResourceCycles = [3, 2, 1, 1];
   let Latency = 5;
   let NumMicroOps = 7;
 }
-def : InstRW<[ADLPWriteResGroup230], (instrs SHA256MSG1rr)>;
+def : InstRW<[ADLPWriteResGroup227], (instrs SHA256MSG1rr)>;
 
-def ADLPWriteResGroup231 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
-  let ResourceCycles = [1, 2];
-  let Latency = 13;
-  let NumMicroOps = 3;
-}
-def : InstRW<[ADLPWriteResGroup231, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;
-
-def ADLPWriteResGroup232 : SchedWriteRes<[ADLPPort05]> {
+def ADLPWriteResGroup228 : SchedWriteRes<[ADLPPort05]> {
   let ResourceCycles = [2];
   let Latency = 6;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup232], (instrs SHA256MSG2rr)>;
+def : InstRW<[ADLPWriteResGroup228], (instrs SHA256MSG2rr)>;
 
-def ADLPWriteResGroup233 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup229 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 13;
   let NumMicroOps = 5;
 }
-def : InstRW<[ADLPWriteResGroup233], (instrs SHRD16mri8)>;
+def : InstRW<[ADLPWriteResGroup229], (instrs SHRD16mri8)>;
 
-def ADLPWriteResGroup234 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup230 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup234], (instregex "^SLDT(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup230], (instregex "^SLDT(32|64)r$")>;
 
-def ADLPWriteResGroup235 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
+def ADLPWriteResGroup231 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup235], (instrs SMSW16r)>;
+def : InstRW<[ADLPWriteResGroup231], (instrs SMSW16r)>;
 
-def ADLPWriteResGroup236 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
+def ADLPWriteResGroup232 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup236], (instregex "^SMSW(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup232], (instregex "^SMSW(32|64)r$")>;
 
-def ADLPWriteResGroup237 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+def ADLPWriteResGroup233 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
   let Latency = 24;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup237, ReadAfterVecLd], (instregex "^(V?)SQRTSDm_Int$")>;
+def : InstRW<[ADLPWriteResGroup233, ReadAfterVecLd], (instregex "^(V?)SQRTSDm_Int$")>;
 
-def ADLPWriteResGroup238 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup234 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
   let Latency = 6;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup238], (instrs STD)>;
+def : InstRW<[ADLPWriteResGroup234], (instrs STD)>;
 
-def ADLPWriteResGroup239 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup235 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
   let ResourceCycles = [1, 4, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 6;
 }
-def : InstRW<[ADLPWriteResGroup239], (instrs STI)>;
+def : InstRW<[ADLPWriteResGroup235], (instrs STI)>;
 
-def ADLPWriteResGroup240 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup236 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [2, 1, 1];
   let Latency = 8;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup240], (instrs STOSB)>;
+def : InstRW<[ADLPWriteResGroup236], (instrs STOSB)>;
 
-def ADLPWriteResGroup241 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup237 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
   let ResourceCycles = [2, 1, 1];
   let Latency = 7;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup241], (instregex "^STOS(L|Q|W)$")>;
+def : InstRW<[ADLPWriteResGroup237], (instregex "^STOS(L|Q|W)$")>;
 
-def ADLPWriteResGroup242 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup238 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
   let Latency = 5;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup242], (instregex "^STR(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup238], (instregex "^STR(32|64)r$")>;
 
-def ADLPWriteResGroup243 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup239 : SchedWriteRes<[ADLPPort00]> {
   let Latency = 2;
 }
-def : InstRW<[ADLPWriteResGroup243], (instregex "^(TST|XAM)_F$")>;
-def : InstRW<[ADLPWriteResGroup243], (instrs UCOM_FPPr)>;
+def : InstRW<[ADLPWriteResGroup239], (instregex "^(TST|XAM)_F$")>;
+def : InstRW<[ADLPWriteResGroup239], (instrs UCOM_FPPr)>;
 
-def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup240 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
   let ResourceCycles = [3, 1];
   let Latency = 9;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
-def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
+def : InstRW<[ADLPWriteResGroup240, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
+def : InstRW<[ADLPWriteResGroup240, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
 
-def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00_01_05]> {
+def ADLPWriteResGroup241 : SchedWriteRes<[ADLPPort00_01_05]> {
   let ResourceCycles = [3];
   let Latency = 3;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup245], (instregex "^VBLENDVP(D|S)rr$")>;
-def : InstRW<[ADLPWriteResGroup245], (instrs VPBLENDVBrr)>;
+def : InstRW<[ADLPWriteResGroup241], (instregex "^VBLENDVP(D|S)rr$")>;
+def : InstRW<[ADLPWriteResGroup241], (instrs VPBLENDVBrr)>;
 
-def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup242 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
   let ResourceCycles = [6, 7, 18];
   let Latency = 81;
   let NumMicroOps = 31;
 }
-def : InstRW<[ADLPWriteResGroup246], (instrs VERRm)>;
+def : InstRW<[ADLPWriteResGroup242], (instrs VERRm)>;
 
-def ADLPWriteResGroup247 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup243 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
   let ResourceCycles = [6, 7, 17];
   let Latency = 74;
   let NumMicroOps = 30;
 }
-def : InstRW<[ADLPWriteResGroup247], (instrs VERRr)>;
+def : InstRW<[ADLPWriteResGroup243], (instrs VERRr)>;
 
-def ADLPWriteResGroup248 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
   let ResourceCycles = [5, 8, 21];
   let Latency = 81;
   let NumMicroOps = 34;
 }
-def : InstRW<[ADLPWriteResGroup248], (instrs VERWm)>;
+def : InstRW<[ADLPWriteResGroup244], (instrs VERWm)>;
 
-def ADLPWriteResGroup249 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
   let ResourceCycles = [5, 8, 20];
   let Latency = 74;
   let NumMicroOps = 33;
 }
-def : InstRW<[ADLPWriteResGroup249], (instrs VERWr)>;
+def : InstRW<[ADLPWriteResGroup245], (instrs VERWr)>;
 
-def ADLPWriteResGroup250 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
   let ResourceCycles = [1, 1, 2, 4];
   let Latency = 29;
   let NumMicroOps = 8;
 }
-def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",
+def : InstRW<[ADLPWriteResGroup246, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",
                                                                                "^VPGATHER(D|Q)QYrm$")>;
-def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,
+def : InstRW<[ADLPWriteResGroup246, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,
                                                                             VPGATHERQDYrm)>;
 
-def ADLPWriteResGroup251 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup247 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
   let ResourceCycles = [1, 1, 1, 2];
   let Latency = 20;
   let NumMicroOps = 5;
 }
-def : InstRW<[ADLPWriteResGroup251, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",
+def : InstRW<[ADLPWriteResGroup247, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",
                                                                                "^VPGATHER(D|Q)Qrm$")>;
-def : InstRW<[ADLPWriteResGroup251, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,
+def : InstRW<[ADLPWriteResGroup247, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,
                                                                             VPGATHERQDrm)>;
 
-def ADLPWriteResGroup252 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup248 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
   let ResourceCycles = [1, 1, 2, 8];
   let Latency = 30;
   let NumMicroOps = 12;
 }
-def : InstRW<[ADLPWriteResGroup252, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,
+def : InstRW<[ADLPWriteResGroup248, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,
                                                                             VPGATHERDDYrm)>;
 
-def ADLPWriteResGroup253 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup249 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
   let ResourceCycles = [1, 1, 2, 4];
   let Latency = 28;
   let NumMicroOps = 8;
 }
-def : InstRW<[ADLPWriteResGroup253, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,
+def : InstRW<[ADLPWriteResGroup249, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,
                                                                             VPGATHERDDrm)>;
 
-def ADLPWriteResGroup254 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {
+def ADLPWriteResGroup250 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {
   let ResourceCycles = [1, 2];
   let Latency = 5;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup254], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
+def : InstRW<[ADLPWriteResGroup250], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
 
-def ADLPWriteResGroup255 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup251 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup255, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rm$",
+def : InstRW<[ADLPWriteResGroup251, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rm$",
                                                                  "^VP(ADD|SUB)(B|D|Q|W)Yrm$")>;
 
-def ADLPWriteResGroup256 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup252 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort02_03_11]> {
   let Latency = 7;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup256], (instrs VLDMXCSR)>;
+def : InstRW<[ADLPWriteResGroup252], (instrs VLDMXCSR)>;
 
-def ADLPWriteResGroup257 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
-  let ResourceCycles = [8, 1, 1, 1, 1, 1, 2, 3];
+def ADLPWriteResGroup253 : SchedWriteRes<[ADLPPort01, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_11, ADLPPort04, ADLPPort04_09, ADLPPort05, ADLPPort06]> {
+  let ResourceCycles = [1, 1, 1, 1, 1, 8, 2, 3];
   let Latency = 40;
   let NumMicroOps = 18;
 }
-def : InstRW<[ADLPWriteResGroup257], (instrs VMCLEARm)>;
+def : InstRW<[ADLPWriteResGroup253], (instrs VMCLEARm)>;
 
-def ADLPWriteResGroup258 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup254 : SchedWriteRes<[ADLPPort00]> {
   let Latency = 5;
 }
-def : InstRW<[ADLPWriteResGroup258], (instregex "^VMOVMSKP(D|S)Yrr$")>;
+def : InstRW<[ADLPWriteResGroup254], (instregex "^VMOVMSKP(D|S)Yrr$")>;
 
-def ADLPWriteResGroup259 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup255 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 521;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup259], (instrs VMOVNTDQmr)>;
+def : InstRW<[ADLPWriteResGroup255], (instrs VMOVNTDQmr)>;
 
-def ADLPWriteResGroup260 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup256 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 473;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup260], (instrs VMOVNTPDmr)>;
+def : InstRW<[ADLPWriteResGroup256], (instrs VMOVNTPDmr)>;
 
-def ADLPWriteResGroup261 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup257 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 494;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup261], (instrs VMOVNTPSYmr)>;
+def : InstRW<[ADLPWriteResGroup257], (instrs VMOVNTPSYmr)>;
 
-def ADLPWriteResGroup262 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup258 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
   let Latency = 470;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup262], (instrs VMOVNTPSmr)>;
+def : InstRW<[ADLPWriteResGroup258], (instrs VMOVNTPSmr)>;
 
-def ADLPWriteResGroup263 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup259 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
   let Latency = 11;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$")>;
-def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
-def : InstRW<[ADLPWriteResGroup263, ReadAfterVecXLd], (instrs VPCLMULQDQYrm)>;
+def : InstRW<[ADLPWriteResGroup259, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$")>;
+def : InstRW<[ADLPWriteResGroup259, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
+def : InstRW<[ADLPWriteResGroup259, ReadAfterVecXLd], (instrs VPCLMULQDQYrm)>;
 
-def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup260 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
   let Latency = 9;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>;
-def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;
+def : InstRW<[ADLPWriteResGroup260, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>;
+def : InstRW<[ADLPWriteResGroup260, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;
 
-def ADLPWriteResGroup265 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
-  let Latency = 13;
-  let NumMicroOps = 2;
-}
-def : InstRW<[ADLPWriteResGroup265], (instregex "^VPDP(BU|WS)SD((SY)?)rm$",
-                                                "^VPDP(BU|WS)SD(S|Y)rm$")>;
-
-def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup261 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
   let ResourceCycles = [1, 2, 1];
   let Latency = 10;
   let NumMicroOps = 4;
 }
-def : InstRW<[ADLPWriteResGroup266, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
+def : InstRW<[ADLPWriteResGroup261, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
 
-def ADLPWriteResGroup267 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10]> {
+def ADLPWriteResGroup262 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10]> {
   let ResourceCycles = [1, 2, 3, 3, 1];
   let Latency = 16;
   let NumMicroOps = 10;
 }
-def : InstRW<[ADLPWriteResGroup267], (instrs VZEROALL)>;
+def : InstRW<[ADLPWriteResGroup262], (instrs VZEROALL)>;
 
-def ADLPWriteResGroup268 : SchedWriteRes<[ADLPPort00_01_05_06]> {
+def ADLPWriteResGroup263 : SchedWriteRes<[ADLPPort00_01_05_06]> {
   let ResourceCycles = [2];
   let Latency = 2;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup268], (instrs WAIT)>;
+def : InstRW<[ADLPWriteResGroup263], (instrs WAIT)>;
 
-def ADLPWriteResGroup269 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 144;
 }
-def : InstRW<[ADLPWriteResGroup269], (instrs WRMSR)>;
+def : InstRW<[ADLPWriteResGroup264], (instrs WRMSR)>;
 
-def ADLPWriteResGroup270 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup265 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
   let ResourceCycles = [2, 1, 4, 1];
   let Latency = AlderlakePModel.MaxLatency;
   let NumMicroOps = 8;
 }
-def : InstRW<[ADLPWriteResGroup270], (instrs WRPKRUr)>;
+def : InstRW<[ADLPWriteResGroup265], (instrs WRPKRUr)>;
 
-def ADLPWriteResGroup271 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
   let ResourceCycles = [2];
   let Latency = 12;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup271, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup266, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
 
-def ADLPWriteResGroup272 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+def ADLPWriteResGroup267 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
   let ResourceCycles = [2];
   let Latency = 13;
   let NumMicroOps = 2;
 }
-def : InstRW<[ADLPWriteResGroup272, WriteRMW], (instrs XADD8rm)>;
+def : InstRW<[ADLPWriteResGroup267, WriteRMW], (instrs XADD8rm)>;
 
-def ADLPWriteResGroup273 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup268 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
   let ResourceCycles = [4, 1];
   let Latency = 39;
   let NumMicroOps = 5;
 }
-def : InstRW<[ADLPWriteResGroup273, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
+def : InstRW<[ADLPWriteResGroup268, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
 
-def ADLPWriteResGroup274 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup269 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
   let ResourceCycles = [5, 1];
   let Latency = 39;
   let NumMicroOps = 6;
 }
-def : InstRW<[ADLPWriteResGroup274, WriteRMW], (instrs XCHG64rm)>;
+def : InstRW<[ADLPWriteResGroup269, WriteRMW], (instrs XCHG64rm)>;
 
-def ADLPWriteResGroup275 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup270 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
   let ResourceCycles = [4, 1];
   let Latency = 40;
   let NumMicroOps = 5;
 }
-def : InstRW<[ADLPWriteResGroup275, WriteRMW], (instrs XCHG8rm)>;
+def : InstRW<[ADLPWriteResGroup270, WriteRMW], (instrs XCHG8rm)>;
 
-def ADLPWriteResGroup276 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort01, ADLPPort05, ADLPPort06]> {
+def ADLPWriteResGroup271 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort01, ADLPPort05, ADLPPort06]> {
   let ResourceCycles = [2, 4, 2, 1, 2, 4];
   let Latency = 17;
   let NumMicroOps = 15;
 }
-def : InstRW<[ADLPWriteResGroup276], (instrs XCH_F)>;
+def : InstRW<[ADLPWriteResGroup271], (instrs XCH_F)>;
 
-def ADLPWriteResGroup277 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup272 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01]> {
   let ResourceCycles = [7, 3, 8, 5];
   let Latency = 4;
   let NumMicroOps = 23;
 }
-def : InstRW<[ADLPWriteResGroup277], (instrs XGETBV)>;
+def : InstRW<[ADLPWriteResGroup272], (instrs XGETBV)>;
 
-def ADLPWriteResGroup278 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup273 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
   let ResourceCycles = [2, 1];
   let Latency = 7;
   let NumMicroOps = 3;
 }
-def : InstRW<[ADLPWriteResGroup278], (instrs XLAT)>;
+def : InstRW<[ADLPWriteResGroup273], (instrs XLAT)>;
 
-def ADLPWriteResGroup279 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort02_03, ADLPPort06]> {
-  let ResourceCycles = [21, 1, 1, 8];
+def ADLPWriteResGroup274 : SchedWriteRes<[ADLPPort01, ADLPPort02_03, ADLPPort02_03_11, ADLPPort06]> {
+  let ResourceCycles = [1, 21, 1, 8];
   let Latency = 37;
   let NumMicroOps = 31;
 }
-def : InstRW<[ADLPWriteResGroup279], (instregex "^XRSTOR((S|64)?)$")>;
-def : InstRW<[ADLPWriteResGroup279], (instrs XRSTORS64)>;
+def : InstRW<[ADLPWriteResGroup274], (instregex "^XRSTOR((S|64)?)$")>;
+def : InstRW<[ADLPWriteResGroup274], (instrs XRSTORS64)>;
 
-def ADLPWriteResGroup280 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup275 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
   let Latency = 42;
   let NumMicroOps = 140;
 }
-def : InstRW<[ADLPWriteResGroup280], (instrs XSAVE)>;
+def : InstRW<[ADLPWriteResGroup275], (instrs XSAVE)>;
 
-def ADLPWriteResGroup281 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup276 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
   let Latency = 41;
   let NumMicroOps = 140;
 }
-def : InstRW<[ADLPWriteResGroup281], (instrs XSAVE64)>;
+def : InstRW<[ADLPWriteResGroup276], (instrs XSAVE64)>;
 
-def ADLPWriteResGroup282 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup277 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
   let Latency = 42;
   let NumMicroOps = 151;
 }
-def : InstRW<[ADLPWriteResGroup282], (instrs XSAVEC)>;
+def : InstRW<[ADLPWriteResGroup277], (instrs XSAVEC)>;
 
-def ADLPWriteResGroup283 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup278 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
   let Latency = 42;
   let NumMicroOps = 152;
 }
-def : InstRW<[ADLPWriteResGroup283], (instrs XSAVEC64)>;
+def : InstRW<[ADLPWriteResGroup278], (instrs XSAVEC64)>;
 
-def ADLPWriteResGroup284 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup279 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [25, 35, 52, 27, 4, 1, 10, 1];
   let Latency = 46;
   let NumMicroOps = 155;
 }
-def : InstRW<[ADLPWriteResGroup284], (instrs XSAVEOPT)>;
+def : InstRW<[ADLPWriteResGroup279], (instrs XSAVEOPT)>;
 
-def ADLPWriteResGroup285 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup280 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [25, 35, 53, 27, 4, 1, 10, 1];
   let Latency = 46;
   let NumMicroOps = 156;
 }
-def : InstRW<[ADLPWriteResGroup285], (instrs XSAVEOPT64)>;
+def : InstRW<[ADLPWriteResGroup280], (instrs XSAVEOPT64)>;
 
-def ADLPWriteResGroup286 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup281 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
   let Latency = 42;
   let NumMicroOps = 184;
 }
-def : InstRW<[ADLPWriteResGroup286], (instrs XSAVES)>;
+def : InstRW<[ADLPWriteResGroup281], (instrs XSAVES)>;
 
-def ADLPWriteResGroup287 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup282 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
   let ResourceCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
   let Latency = 42;
   let NumMicroOps = 186;
 }
-def : InstRW<[ADLPWriteResGroup287], (instrs XSAVES64)>;
+def : InstRW<[ADLPWriteResGroup282], (instrs XSAVES64)>;
 
-def ADLPWriteResGroup288 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
+def ADLPWriteResGroup283 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
   let ResourceCycles = [4, 23, 2, 14, 8, 1, 2];
   let Latency = 5;
   let NumMicroOps = 54;
 }
-def : InstRW<[ADLPWriteResGroup288], (instrs XSETBV)>;
+def : InstRW<[ADLPWriteResGroup283], (instrs XSETBV)>;
 
 }

llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s

 # CHECK-NEXT: [8]   - ADLPPort08
 # CHECK-NEXT: [9]   - ADLPPort09
 # CHECK-NEXT: [10]  - ADLPPort10
 # CHECK-NEXT: [11]  - ADLPPort11
 # CHECK-NEXT: [12]  - ADLPPortInvalid
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]
-# CHECK-NEXT: 310.90 275.73 107.33 107.33 19.50  277.73 8.90   18.83  18.50  18.50  0.73   107.00  -
+# CHECK-NEXT: 310.90 275.73 107.00 107.00 20.00  277.73 8.90   18.50  18.50  19.00  0.73   107.00  -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   Instructions:
 # CHECK-NEXT:  -     0.50    -      -      -     0.50    -      -      -      -      -      -      -     vaddpd %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  -     0.50   0.33   0.33    -     0.50    -      -      -      -      -     0.33    -     vaddpd (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  -     0.50    -      -      -     0.50    -      -      -      -      -      -      -     vaddpd %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  -     0.50   0.33   0.33    -     0.50    -      -      -      -      -     0.33    -     vaddpd (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  -     0.50    -      -      -     0.50    -      -      -      -      -      -      -     vaddps %xmm0, %xmm1, %xmm2

 # CHECK-NEXT:  -     0.50   0.33   0.33    -     2.50    -      -      -      -      -     0.33    -     vhsubps  (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     vinsertf128  $1, %xmm0, %ymm1, %ymm2
 # CHECK-NEXT: 0.33   0.33   0.33   0.33    -     0.33    -      -      -      -      -     0.33    -     vinsertf128  $1, (%rax), %ymm1, %ymm2
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     vinsertps  $1, %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     vinsertps  $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  -      -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     vlddqu (%rax), %xmm2
 # CHECK-NEXT:  -      -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     vlddqu (%rax), %ymm2
 # CHECK-NEXT: 1.50    -     0.33   0.33    -      -     0.50    -      -      -      -     0.33    -     vldmxcsr (%rax)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00    -      -     0.33    -      -      -      -      -     vmaskmovdqu  %xmm0, %xmm1
+# CHECK-NEXT:  -      -      -      -     1.50    -      -      -      -     0.50    -      -      -     vmaskmovdqu  %xmm0, %xmm1
 # CHECK-NEXT: 0.33   0.33   0.33   0.33    -     0.33    -      -      -      -      -     0.33    -     vmaskmovpd (%rax), %xmm0, %xmm2
 # CHECK-NEXT: 0.33   0.33   0.33   0.33    -     0.33    -      -      -      -      -     0.33    -     vmaskmovpd (%rax), %ymm0, %ymm2
 # CHECK-NEXT: 1.00    -      -      -     0.50    -      -     0.50   0.50   0.50    -      -      -     vmaskmovpd %xmm0, %xmm1, (%rax)
 # CHECK-NEXT: 1.00    -      -      -     0.50    -      -     0.50   0.50   0.50    -      -      -     vmaskmovpd %ymm0, %ymm1, (%rax)
 # CHECK-NEXT: 0.33   0.33   0.33   0.33    -     0.33    -      -      -      -      -     0.33    -     vmaskmovps (%rax), %xmm0, %xmm2
 # CHECK-NEXT: 0.33   0.33   0.33   0.33    -     0.33    -      -      -      -      -     0.33    -     vmaskmovps (%rax), %ymm0, %ymm2
 # CHECK-NEXT: 1.00    -      -      -     0.50    -      -     0.50   0.50   0.50    -      -      -     vmaskmovps %xmm0, %xmm1, (%rax)
 # CHECK-NEXT: 1.00    -      -      -     0.50    -      -     0.50   0.50   0.50    -      -      -     vmaskmovps %ymm0, %ymm1, (%rax)

llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s

 # CHECK-NEXT: [8]   - ADLPPort08
 # CHECK-NEXT: [9]   - ADLPPort09
 # CHECK-NEXT: [10]  - ADLPPort10
 # CHECK-NEXT: [11]  - ADLPPort11
 # CHECK-NEXT: [12]  - ADLPPortInvalid
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]
-# CHECK-NEXT: 107.70 99.20  39.33  39.33  8.50   71.70  1.20   7.83   7.50   7.50   0.20   39.00   -
+# CHECK-NEXT: 107.70 99.20  39.00  39.00  9.00   71.70  1.20   7.50   7.50   8.00   0.20   39.00   -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   Instructions:
 # CHECK-NEXT:  -     0.50    -      -      -     0.50    -      -      -      -      -      -      -     addpd  %xmm0, %xmm2
 # CHECK-NEXT:  -     0.50   0.33   0.33    -     0.50    -      -      -      -      -     0.33    -     addpd  (%rax), %xmm2
 # CHECK-NEXT:  -     0.50    -      -      -     0.50    -      -      -      -      -      -      -     addsd  %xmm0, %xmm2
 # CHECK-NEXT:  -     0.50   0.33   0.33    -     0.50    -      -      -      -      -     0.33    -     addsd  (%rax), %xmm2
 # CHECK-NEXT: 0.33   0.33    -      -      -     0.33    -      -      -      -      -      -      -     andnpd %xmm0, %xmm2

 # CHECK-NEXT: 1.50   0.50    -      -      -      -      -      -      -      -      -      -      -     cvttsd2si  %xmm0, %rcx
 # CHECK-NEXT: 1.50   0.50   0.33   0.33    -      -      -      -      -      -      -     0.33    -     cvttsd2si  (%rax), %ecx
 # CHECK-NEXT: 1.50   0.50   0.33   0.33    -      -      -      -      -      -      -     0.33    -     cvttsd2si  (%rax), %rcx
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     divpd  %xmm0, %xmm2
 # CHECK-NEXT: 1.00    -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     divpd  (%rax), %xmm2
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     divsd  %xmm0, %xmm2
 # CHECK-NEXT: 1.00    -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     divsd  (%rax), %xmm2
 # CHECK-NEXT: 0.50    -      -      -      -      -     0.50    -      -      -      -      -      -     lfence
-# CHECK-NEXT:  -      -     0.33   0.33   1.00    -      -     0.33    -      -      -      -      -     maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT:  -      -      -      -     1.50    -      -      -      -     0.50    -      -      -     maskmovdqu %xmm0, %xmm1
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -      -     maxpd  %xmm0, %xmm2
 # CHECK-NEXT: 0.50   0.50   0.33   0.33    -      -      -      -      -      -      -     0.33    -     maxpd  (%rax), %xmm2
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -      -     maxsd  %xmm0, %xmm2
 # CHECK-NEXT: 0.50   0.50   0.33   0.33    -      -      -      -      -      -      -     0.33    -     maxsd  (%rax), %xmm2
 # CHECK-NEXT:  -      -      -      -     0.50    -      -     0.50   0.50   0.50    -      -      -     mfence
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -      -     minpd  %xmm0, %xmm2
 # CHECK-NEXT: 0.50   0.50   0.33   0.33    -      -      -      -      -      -      -     0.33    -     minpd  (%rax), %xmm2
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -      -     minsd  %xmm0, %xmm2

llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x87.s

 # CHECK-NEXT:  3      4     1.00           *      U     fistl (%ecx)
 # CHECK-NEXT:  3      4     1.00           *      U     fistps  (%edx)
 # CHECK-NEXT:  3      4     1.00           *      U     fistpl  (%ecx)
 # CHECK-NEXT:  3      4     1.00           *      U     fistpll (%eax)
 # CHECK-NEXT:  3      4     1.00           *      U     fisttps (%edx)
 # CHECK-NEXT:  3      4     1.00           *      U     fisttpl (%ecx)
 # CHECK-NEXT:  3      4     1.00           *      U     fisttpll  (%eax)
 # CHECK-NEXT:  1      1     0.25                  U     fld %st(0)
-# CHECK-NEXT:  1      7     0.50    *             U     flds  (%edx)
-# CHECK-NEXT:  1      7     0.50    *             U     fldl  (%ecx)
-# CHECK-NEXT:  1      7     0.50    *             U     fldt  (%eax)
+# CHECK-NEXT:  1      7     0.33    *             U     flds  (%edx)
+# CHECK-NEXT:  1      7     0.33    *             U     fldl  (%ecx)
+# CHECK-NEXT:  1      7     0.33    *             U     fldt  (%eax)
 # CHECK-NEXT:  3      7     1.00    *             U     fldcw (%eax)
-# CHECK-NEXT:  64     62    14.00   *             U     fldenv  (%eax)
+# CHECK-NEXT:  64     62    19.50   *             U     fldenv  (%eax)
 # CHECK-NEXT:  2      1     1.00                  U     fld1
 # CHECK-NEXT:  2      1     1.00                  U     fldl2e
 # CHECK-NEXT:  2      1     1.00                  U     fldl2t
 # CHECK-NEXT:  2      1     1.00                  U     fldlg2
 # CHECK-NEXT:  2      1     1.00                  U     fldln2
 # CHECK-NEXT:  2      1     1.00                  U     fldpi
 # CHECK-NEXT:  1      1     0.50                  U     fldz
 # CHECK-NEXT:  1      4     1.00                  U     fmul  %st, %st(1)

 # CHECK-NEXT:  1      1     0.25                  U     fst %st(0)
 # CHECK-NEXT:  1      1     1.00           *      U     fsts  (%edx)
 # CHECK-NEXT:  1      1     1.00           *      U     fstl  (%ecx)
 # CHECK-NEXT:  1      1     0.25                  U     fstp  %st(0)
 # CHECK-NEXT:  2      1     1.00           *      U     fstpl (%edx)
 # CHECK-NEXT:  2      1     1.00           *      U     fstpl (%ecx)
 # CHECK-NEXT:  2      1     1.00           *      U     fstpt (%eax)
 # CHECK-NEXT:  3      2     1.00           *      U     fnstcw  (%eax)
-# CHECK-NEXT:  100    106   19.50          *      U     fnstenv (%eax)
+# CHECK-NEXT:  100    106   30.00          *      U     fnstenv (%eax)
 # CHECK-NEXT:  3      3     1.00           *      U     fnstsw  (%eax)
 # CHECK-NEXT:  1      100   0.25    *             U     frstor  (%eax)
 # CHECK-NEXT:  2      2     0.50                  U     wait
 # CHECK-NEXT:  1      100   0.25           *      U     fnsave  (%eax)
 # CHECK-NEXT:  1      3     1.00                  U     fsub  %st, %st(1)
 # CHECK-NEXT:  1      3     1.00                  U     fsub  %st(2), %st
 # CHECK-NEXT:  2      10    1.00    *             U     fsubs (%ecx)
 # CHECK-NEXT:  2      10    1.00    *             U     fsubl (%eax)

 # CHECK-NEXT:  1      1     1.00                  U     fucomp  %st(3)
 # CHECK-NEXT:  1      2     1.00                  U     fucompp
 # CHECK-NEXT:  1      1     1.00                  U     fucomi  %st(3), %st
 # CHECK-NEXT:  1      1     1.00                  U     fucompi %st(3), %st
 # CHECK-NEXT:  2      2     0.50                  U     wait
 # CHECK-NEXT:  1      2     1.00                  U     fxam
 # CHECK-NEXT:  15     17    4.00                  U     fxch  %st(1)
 # CHECK-NEXT:  15     17    4.00                  U     fxch  %st(3)
-# CHECK-NEXT:  90     63    16.50   *      *      U     fxrstor (%eax)
+# CHECK-NEXT:  90     63    26.67   *      *      U     fxrstor (%eax)
 # CHECK-NEXT:  110    100   19.00   *      *      U     fxsave  (%eax)
 # CHECK-NEXT:  1      100   0.25                  U     fxtract
 # CHECK-NEXT:  1      100   0.25                  U     fyl2x
 # CHECK-NEXT:  1      100   0.25                  U     fyl2xp1
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - ADLPPort00
 # CHECK-NEXT: [1]   - ADLPPort01
 # CHECK-NEXT: [2]   - ADLPPort02
 # CHECK-NEXT: [3]   - ADLPPort03
 # CHECK-NEXT: [4]   - ADLPPort04
 # CHECK-NEXT: [5]   - ADLPPort05
 # CHECK-NEXT: [6]   - ADLPPort06
 # CHECK-NEXT: [7]   - ADLPPort07
 # CHECK-NEXT: [8]   - ADLPPort08
 # CHECK-NEXT: [9]   - ADLPPort09
 # CHECK-NEXT: [10]  - ADLPPort10
 # CHECK-NEXT: [11]  - ADLPPort11
 # CHECK-NEXT: [12]  - ADLPPortInvalid
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]
-# CHECK-NEXT: 131.25 62.75  49.67  49.67  46.00  159.25 74.75  28.00  19.00  19.00  1.00   0.67   7.00
+# CHECK-NEXT: 105.00 36.50  70.33  70.33  78.50  133.00 48.50  19.00  19.00  32.50  1.00   27.33  7.00
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   Instructions:
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     f2xm1
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fabs
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fadd %st, %st(1)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fadd %st(2), %st
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fadds  (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     faddl  (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fadds  (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     faddl  (%ecx)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     faddp  %st, %st(1)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     faddp  %st, %st(2)
-# CHECK-NEXT:  -      -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     fiadds (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     fiaddl (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     2.00    -      -      -      -      -     0.33    -     fiadds (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     2.00    -      -      -      -      -     0.33    -     fiaddl (%ecx)
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fbld (%ecx)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00    -      -     0.33    -      -      -      -      -     fbstp  (%eax)
+# CHECK-NEXT:  -      -      -      -     1.50    -      -      -      -     0.50    -      -      -     fbstp  (%eax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fchs
 # CHECK-NEXT: 1.00   1.00    -      -      -     1.00   1.00    -      -      -      -      -      -     fnclex
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     fcmovb %st(1), %st
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     fcmovbe  %st(1), %st
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     fcmove %st(1), %st
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     fcmovnb  %st(1), %st
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     fcmovnbe %st(1), %st
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     fcmovne  %st(1), %st
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     fcmovnu  %st(1), %st
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     fcmovu %st(1), %st
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fcom %st(1)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fcom %st(3)
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fcoms  (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fcoml  (%eax)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fcoms  (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fcoml  (%eax)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fcomp  %st(1)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fcomp  %st(3)
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fcomps (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fcompl (%eax)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fcomps (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fcompl (%eax)
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fcompp
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fcomi  %st(3), %st
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fcompi %st(3), %st
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fcos
 # CHECK-NEXT: 1.00    -      -      -      -     1.00    -      -      -      -      -      -      -     fdecstp
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fdiv %st, %st(1)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fdiv %st(2), %st
-# CHECK-NEXT: 1.00    -     0.50   0.50    -      -      -      -      -      -      -      -      -     fdivs  (%ecx)
-# CHECK-NEXT: 1.00    -     0.50   0.50    -      -      -      -      -      -      -      -      -     fdivl  (%eax)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     fdivs  (%ecx)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     fdivl  (%eax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fdivp  %st, %st(1)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fdivp  %st, %st(2)
-# CHECK-NEXT: 1.00    -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fidivs (%ecx)
-# CHECK-NEXT: 1.00    -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fidivl (%eax)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fidivs (%ecx)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fidivl (%eax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fdivr  %st, %st(1)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fdivr  %st(2), %st
-# CHECK-NEXT: 1.00    -     0.50   0.50    -      -      -      -      -      -      -      -      -     fdivrs (%ecx)
-# CHECK-NEXT: 1.00    -     0.50   0.50    -      -      -      -      -      -      -      -      -     fdivrl (%eax)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     fdivrs (%ecx)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     fdivrl (%eax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fdivrp %st, %st(1)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fdivrp %st, %st(2)
-# CHECK-NEXT: 1.00    -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fidivrs  (%ecx)
-# CHECK-NEXT: 1.00    -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fidivrl  (%eax)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fidivrs  (%ecx)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fidivrl  (%eax)
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     ffree  %st(0)
-# CHECK-NEXT:  -      -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     ficoms (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     ficoml (%eax)
-# CHECK-NEXT:  -      -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     ficomps  (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     ficompl  (%eax)
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     filds  (%edx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fildl  (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fildll (%eax)
+# CHECK-NEXT:  -      -     0.33   0.33    -     2.00    -      -      -      -      -     0.33    -     ficoms (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     2.00    -      -      -      -      -     0.33    -     ficoml (%eax)
+# CHECK-NEXT:  -      -     0.33   0.33    -     2.00    -      -      -      -      -     0.33    -     ficomps  (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     2.00    -      -      -      -      -     0.33    -     ficompl  (%eax)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     filds  (%edx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fildl  (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fildll (%eax)
 # CHECK-NEXT: 0.50    -      -      -      -     0.50    -      -      -      -      -      -      -     fincstp
 # CHECK-NEXT: 3.00   1.50    -      -      -     9.00   1.50    -      -      -      -      -      -     fninit
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   1.00    -     0.33    -      -      -      -      -     fists  (%edx)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   1.00    -     0.33    -      -      -      -      -     fistl  (%ecx)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   1.00    -     0.33    -      -      -      -      -     fistps (%edx)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   1.00    -     0.33    -      -      -      -      -     fistpl (%ecx)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   1.00    -     0.33    -      -      -      -      -     fistpll  (%eax)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   1.00    -     0.33    -      -      -      -      -     fisttps  (%edx)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   1.00    -     0.33    -      -      -      -      -     fisttpl  (%ecx)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   1.00    -     0.33    -      -      -      -      -     fisttpll (%eax)
+# CHECK-NEXT:  -      -      -      -     1.50   1.00    -      -      -     0.50    -      -      -     fists  (%edx)
+# CHECK-NEXT:  -      -      -      -     1.50   1.00    -      -      -     0.50    -      -      -     fistl  (%ecx)
+# CHECK-NEXT:  -      -      -      -     1.50   1.00    -      -      -     0.50    -      -      -     fistps (%edx)
+# CHECK-NEXT:  -      -      -      -     1.50   1.00    -      -      -     0.50    -      -      -     fistpl (%ecx)
+# CHECK-NEXT:  -      -      -      -     1.50   1.00    -      -      -     0.50    -      -      -     fistpll  (%eax)
+# CHECK-NEXT:  -      -      -      -     1.50   1.00    -      -      -     0.50    -      -      -     fisttps  (%edx)
+# CHECK-NEXT:  -      -      -      -     1.50   1.00    -      -      -     0.50    -      -      -     fisttpl  (%ecx)
+# CHECK-NEXT:  -      -      -      -     1.50   1.00    -      -      -     0.50    -      -      -     fisttpll (%eax)
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fld  %st(0)
-# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -      -      -      -      -      -     flds (%edx)
-# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -      -      -      -      -      -     fldl (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -      -      -      -      -      -     fldt (%eax)
-# CHECK-NEXT: 1.50    -     0.50   0.50    -     0.50    -      -      -      -      -      -      -     fldcw  (%eax)
-# CHECK-NEXT: 19.25  9.75   4.00   4.00    -     12.25  14.75   -      -      -      -      -      -     fldenv (%eax)
+# CHECK-NEXT:  -      -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     flds (%edx)
+# CHECK-NEXT:  -      -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     fldl (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     fldt (%eax)
+# CHECK-NEXT: 1.50    -     0.33   0.33    -     0.50    -      -      -      -      -     0.33    -     fldcw  (%eax)
+# CHECK-NEXT: 9.50    -     22.17  22.17   -     2.50   5.00    -      -      -      -     2.67    -     fldenv (%eax)
 # CHECK-NEXT: 1.00    -      -      -      -     1.00    -      -      -      -      -      -      -     fld1
 # CHECK-NEXT: 1.00    -      -      -      -     1.00    -      -      -      -      -      -      -     fldl2e
 # CHECK-NEXT: 1.00    -      -      -      -     1.00    -      -      -      -      -      -      -     fldl2t
 # CHECK-NEXT: 1.00    -      -      -      -     1.00    -      -      -      -      -      -      -     fldlg2
 # CHECK-NEXT: 1.00    -      -      -      -     1.00    -      -      -      -      -      -      -     fldln2
 # CHECK-NEXT: 1.00    -      -      -      -     1.00    -      -      -      -      -      -      -     fldpi
 # CHECK-NEXT: 0.50    -      -      -      -     0.50    -      -      -      -      -      -      -     fldz
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fmul %st, %st(1)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fmul %st(2), %st
-# CHECK-NEXT: 1.00    -     0.50   0.50    -      -      -      -      -      -      -      -      -     fmuls  (%ecx)
-# CHECK-NEXT: 1.00    -     0.50   0.50    -      -      -      -      -      -      -      -      -     fmull  (%eax)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     fmuls  (%ecx)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -      -      -      -      -      -      -     0.33    -     fmull  (%eax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fmulp  %st, %st(1)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fmulp  %st, %st(2)
-# CHECK-NEXT: 1.00    -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fimuls (%ecx)
-# CHECK-NEXT: 1.00    -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fimull (%eax)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fimuls (%ecx)
+# CHECK-NEXT: 1.00    -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fimull (%eax)
 # CHECK-NEXT: 0.50    -      -      -      -     0.50    -      -      -      -      -      -      -     fnop
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fpatan
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fprem
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fprem1
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fptan
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     frndint
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     frstor (%eax)
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fnsave (%eax)
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fscale
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fsin
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fsincos
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -     7.00   fsqrt
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fst  %st(0)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00    -      -     0.33    -      -      -      -      -     fsts (%edx)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00    -      -     0.33    -      -      -      -      -     fstl (%ecx)
+# CHECK-NEXT:  -      -      -      -     1.50    -      -      -      -     0.50    -      -      -     fsts (%edx)
+# CHECK-NEXT:  -      -      -      -     1.50    -      -      -      -     0.50    -      -      -     fstl (%ecx)
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fstp %st(0)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00    -      -     0.33    -      -      -      -      -     fstpl  (%edx)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00    -      -     0.33    -      -      -      -      -     fstpl  (%ecx)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00    -      -     0.33    -      -      -      -      -     fstpt  (%eax)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00    -     1.00   0.33    -      -      -      -      -     fnstcw (%eax)
-# CHECK-NEXT: 27.00  8.50   3.67   3.67   11.00  23.50  19.00  3.67    -      -      -      -      -     fnstenv  (%eax)
-# CHECK-NEXT: 1.00    -     0.33   0.33   1.00    -      -     0.33    -      -      -      -      -     fnstsw (%eax)
+# CHECK-NEXT:  -      -      -      -     1.50    -      -      -      -     0.50    -      -      -     fstpl  (%edx)
+# CHECK-NEXT:  -      -      -      -     1.50    -      -      -      -     0.50    -      -      -     fstpl  (%ecx)
+# CHECK-NEXT:  -      -      -      -     1.50    -      -      -      -     0.50    -      -      -     fstpt  (%eax)
+# CHECK-NEXT:  -      -      -      -     1.50    -     1.00    -      -     0.50    -      -      -     fnstcw (%eax)
+# CHECK-NEXT: 22.25  3.75    -      -     35.50  18.75  14.25   -      -     5.50    -      -      -     fnstenv  (%eax)
+# CHECK-NEXT: 1.00    -      -      -     1.50    -      -      -      -     0.50    -      -      -     fnstsw (%eax)
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     frstor (%eax)
 # CHECK-NEXT: 0.50   0.50    -      -      -     0.50   0.50    -      -      -      -      -      -     wait
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fnsave (%eax)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fsub %st, %st(1)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fsub %st(2), %st
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fsubs  (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fsubl  (%eax)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fsubs  (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fsubl  (%eax)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fsubp  %st, %st(1)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fsubp  %st, %st(2)
-# CHECK-NEXT:  -      -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     fisubs (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     fisubl (%eax)
+# CHECK-NEXT:  -      -     0.33   0.33    -     2.00    -      -      -      -      -     0.33    -     fisubs (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     2.00    -      -      -      -      -     0.33    -     fisubl (%eax)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fsubr  %st, %st(1)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fsubr  %st(2), %st
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fsubrs (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     1.00    -      -      -      -      -      -      -     fsubrl (%eax)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fsubrs (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     1.00    -      -      -      -      -     0.33    -     fsubrl (%eax)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fsubrp %st, %st(1)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fsubrp %st, %st(2)
-# CHECK-NEXT:  -      -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     fisubrs  (%ecx)
-# CHECK-NEXT:  -      -     0.50   0.50    -     2.00    -      -      -      -      -      -      -     fisubrl  (%eax)
+# CHECK-NEXT:  -      -     0.33   0.33    -     2.00    -      -      -      -      -     0.33    -     fisubrs  (%ecx)
+# CHECK-NEXT:  -      -     0.33   0.33    -     2.00    -      -      -      -      -     0.33    -     fisubrl  (%eax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     ftst
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fucom  %st(1)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fucom  %st(3)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fucomp %st(1)
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fucomp %st(3)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fucompp
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fucomi %st(3), %st
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -      -      -     fucompi  %st(3), %st
 # CHECK-NEXT: 0.50   0.50    -      -      -     0.50   0.50    -      -      -      -      -      -     wait
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     fxam
 # CHECK-NEXT: 4.00   2.00    -      -      -     4.00   5.00    -      -      -      -      -      -     fxch %st(1)
 # CHECK-NEXT: 4.00   2.00    -      -      -     4.00   5.00    -      -      -      -      -      -     fxch %st(3)
-# CHECK-NEXT: 17.25  12.25  16.50  16.50   -     12.75  14.75   -      -      -      -      -      -     fxrstor  (%eax)
+# CHECK-NEXT: 5.50   0.50   34.50  34.50   -     1.00   3.00    -      -      -      -     11.00   -     fxrstor  (%eax)
 # CHECK-NEXT: 8.00   11.00  0.67   0.67   19.00  6.00   6.00   19.00  19.00  19.00  1.00   0.67    -     fxsave (%eax)
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fxtract
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fyl2x
 # CHECK-NEXT: 0.25   0.25    -      -      -     0.25   0.25    -      -      -      -      -      -     fyl2xp1

llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-xsave.s

 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  23     4     5.00                  U     xgetbv
-# CHECK-NEXT:  31     37    8.00    *      *      U     xrstor  (%rax)
-# CHECK-NEXT:  31     37    8.00    *      *      U     xrstors (%rax)
+# CHECK-NEXT:  31     37    10.50   *      *      U     xrstor  (%rax)
+# CHECK-NEXT:  31     37    10.50   *      *      U     xrstors (%rax)
 # CHECK-NEXT:  140    42    33.50   *      *      U     xsave (%rax)
 # CHECK-NEXT:  54     5     10.80   *      *      U     xsetbv
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - ADLPPort00
 # CHECK-NEXT: [1]   - ADLPPort01
 # CHECK-NEXT: [2]   - ADLPPort02
 # CHECK-NEXT: [3]   - ADLPPort03
 # CHECK-NEXT: [4]   - ADLPPort04
 # CHECK-NEXT: [5]   - ADLPPort05
 # CHECK-NEXT: [6]   - ADLPPort06
 # CHECK-NEXT: [7]   - ADLPPort07
 # CHECK-NEXT: [8]   - ADLPPort08
 # CHECK-NEXT: [9]   - ADLPPort09
 # CHECK-NEXT: [10]  - ADLPPort10
 # CHECK-NEXT: [11]  - ADLPPort11
 # CHECK-NEXT: [12]  - ADLPPortInvalid
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]
-# CHECK-NEXT: 72.00  71.67  2.33   2.33   0.50   53.83  67.17  0.50   0.50   0.50   6.33   1.33    -
+# CHECK-NEXT: 61.50  61.17  23.00  23.00  0.50   43.33  56.67  0.50   0.50   0.50   6.33   2.00    -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   Instructions:
 # CHECK-NEXT: 6.40   6.40    -      -      -     2.40   6.40    -      -      -     1.40    -      -     xgetbv
-# CHECK-NEXT: 5.25   6.25   0.50   0.50    -     5.25   13.25   -      -      -      -      -      -     xrstor (%rax)
-# CHECK-NEXT: 5.25   6.25   0.50   0.50    -     5.25   13.25   -      -      -      -      -      -     xrstors  (%rax)
+# CHECK-NEXT:  -     1.00   10.83  10.83   -      -     8.00    -      -      -      -     0.33    -     xrstor (%rax)
+# CHECK-NEXT:  -     1.00   10.83  10.83   -      -     8.00    -      -      -      -     0.33    -     xrstors  (%rax)
 # CHECK-NEXT: 41.50  38.50  1.33   1.33   0.50   32.00  22.00  0.50   0.50   0.50    -     1.33    -     xsave  (%rax)
 # CHECK-NEXT: 13.60  14.27   -      -      -     8.93   12.27   -      -      -     4.93    -      -     xsetbv