[RISCV] Optimize i32 range checks

[dtcxzyw]

Summary

This patch improves instruction selection for i32 range check patterns like INT_MIN <= x && x <= INT_MAX and its alternatives.
On rv32: GCC: https://godbolt.org/z/1zKjfMqax Alive2: https://alive2.llvm.org/ce/z/FPc4ss
On rv64: GCC: https://godbolt.org/z/ezTsv8cEo Alive2: https://alive2.llvm.org/ce/z/ZkF7Er

I am unsure whether it is suitable to do the pattern match in ISel. I also have an alternative that does pattern match in RISCVCodeGenPrepare.

[craig.topper]

My suggested patch lifted from AArch64/X86 with i8/i16 removed.

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index c020b27edf3e..f8fe17a9cfe3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -550,6 +550,23 @@ public:
     return ISD::SIGN_EXTEND;
   }
 
+  bool shouldTransformSignedTruncationCheck(EVT XVT,
+                                            unsigned KeptBits) const override {
+    // For vectors, we don't have a preference..
+    if (XVT.isVector())
+      return false;
+
+    auto VTIsOk = [](EVT VT) -> bool {
+      return VT == MVT::i32 || VT == MVT::i64;
+    };
+
+    // We are ok with KeptBitsVT being byte/word/dword, what sext.w supports.
+    // XVT will be larger than KeptBitsVT.
+    // FIXME: Support Zbb?
+    MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
+    return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
+  }
+
   TargetLowering::ShiftLegalizationStrategy
   preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
                                      unsigned ExpansionFactor) const override {

[craig.topper]

In D149814#4320593, @craig.topper wrote:

My suggested patch lifted from AArch64/X86 with i8/i16 removed.

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index c020b27edf3e..f8fe17a9cfe3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -550,6 +550,23 @@ public:
     return ISD::SIGN_EXTEND;
   }
 
+  bool shouldTransformSignedTruncationCheck(EVT XVT,
+                                            unsigned KeptBits) const override {
+    // For vectors, we don't have a preference..
+    if (XVT.isVector())
+      return false;
+
+    auto VTIsOk = [](EVT VT) -> bool {
+      return VT == MVT::i32 || VT == MVT::i64;
+    };
+
+    // We are ok with KeptBitsVT being byte/word/dword, what sext.w supports.
+    // XVT will be larger than KeptBitsVT.
+    // FIXME: Support Zbb?
+    MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
+    return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
+  }
+
   TargetLowering::ShiftLegalizationStrategy
   preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
                                      unsigned ExpansionFactor) const override {

Posted as https://reviews.llvm.org/D149977

llvm/lib/Target/RISCV/RISCVInstrInfo.td

class binop_oneuse<SDPatternOperator operator>
     : PatFrag<(ops node:$A, node:$B),
               (operator node:$A, node:$B), [{
   return N->hasOneUse();
 }]>;
 
 def and_oneuse : binop_oneuse<and>;
 def add_oneuse : binop_oneuse<add>;
 def mul_oneuse : binop_oneuse<mul>;
+def srl_oneuse : binop_oneuse<srl>;
 
 def mul_const_oneuse : PatFrag<(ops node:$A, node:$B),
                                (mul node:$A, node:$B), [{
   if (auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
     return N1C->hasOneUse();
   return false;
 }]>;
 

 
 // RISC-V doesn't have general instructions for integer setne/seteq, but we can
 // check for equality with 0. These ComplexPatterns rewrite the setne/seteq into
 // something that can be compared with 0.
 // These ComplexPatterns must be used in pairs.
 def riscv_setne : ComplexPattern<XLenVT, 1, "selectSETNE", [setcc]>;
 def riscv_seteq : ComplexPattern<XLenVT, 1, "selectSETEQ", [setcc]>;
 
+// i32 range checks
+let Predicates = [IsRV64] in {
+// Select ADDIW on rv64
+def : Pat<(seteq (srl_oneuse (add_oneuse GPR:$rs1, (i64 2147483648)), (i64 32)), (i64 0)),
+          (SLTIU (XOR $rs1, (ADDIW $rs1, 0)), 1)>;
+}
+let Predicates = [IsRV32] in {
+// Select SRAI on rv32
+def : Pat<(seteq (add_oneuse GPR:$rs1, (binop_oneuse<setult> (add_oneuse GPR:$rs2, (i32 -2147483648)), GPR:$rs2)), (i32 0)),
+          (SLTIU (XOR (SRAI $rs2, 31), $rs1), 1)>;
+}
+
 // Define pattern expansions for setcc operations that aren't directly
 // handled by a RISC-V instruction.
 def : Pat<(riscv_seteq GPR:$rs1), (SLTIU GPR:$rs1, 1)>;
 def : Pat<(riscv_setne GPR:$rs1), (SLTU X0, GPR:$rs1)>;
 def : Pat<(setne GPR:$rs1, -1), (SLTIU GPR:$rs1, -1)>;
 
 def IntCCtoRISCVCC : SDNodeXForm<riscv_selectcc, [{
   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();

llvm/test/CodeGen/RISCV/setcc-logic.ll

 
 7:                                                ; preds = %4
   tail call void @bar()
   br label %8
 
 8:                                                ; preds = %8, %4
   ret void
 }
+
+define i32 @i32_range_check(i64 %0) {
+; RV32I-LABEL: i32_range_check:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srai a0, a0, 31
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: i32_range_check:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    ret
+  %2 = add i64 %0, 2147483648
+  %3 = icmp ult i64 %2, 4294967296
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}