This is an archive of the discontinued LLVM Phabricator instance.

Differential D149497

[RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td
ClosedPublic

Authored by michaelmaitland on Apr 28 2023, 4:16 PM.

Details

Reviewers
craig.topper
kito-cheng
reames
Commits
rGf9fa8a599704: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td
rGcd02b69e75dd: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td
Summary

Based on the following description from Andrew W.

  • Instructions not mentioned here behave the same as integer ALU ops
  • rev8 only executes in the late-A and late-B ALUs
  • shNadd[.uw] only execute on the early-B and late-B ALUs
  • clz[w], ctz[w], and orc.b and all rotates only execute in the late-B ALU
  • pcnt[w] looks exactly like integer multiply

This patch does not account for early/late ALU in the model. It is coded based
on the pipes only.

Co-Authored-By: topperc <craig.topper@sifive.com>

Diff Detail

Event Timeline

michaelmaitland created this revision.Apr 28 2023, 4:16 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2023, 4:16 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 28 others. · View Herald Transcript
michaelmaitland requested review of this revision.Apr 28 2023, 4:16 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptApr 28 2023, 4:16 PM
Herald added subscribers: llvm-commits, cfe-commits, • pcwang-thead and 2 others. · View Herald Transcript
Harbormaster completed remote builds in B228947: Diff 518083.Apr 28 2023, 4:16 PM
craig.topper added inline comments.Apr 28 2023, 5:10 PM
llvm/lib/Target/RISCV/RISCVProcessors.td
181 ↗(On Diff #518083)

This makes the patch dependent on adding sifive-x280

michaelmaitland added a parent revision: D149495: [RISCV] Add support for V extension in SiFive7.Apr 28 2023, 5:11 PM
michaelmaitland marked an inline comment as done.
michaelmaitland added inline comments.
llvm/lib/Target/RISCV/RISCVProcessors.td
181 ↗(On Diff #518083)

Added parent revision.

craig.topper accepted this revision.Apr 28 2023, 5:37 PM

LGTM

This revision is now accepted and ready to land.Apr 28 2023, 5:37 PM
michaelmaitland updated this revision to Diff 518924.May 2 2023, 5:46 PM
michaelmaitland marked an inline comment as done.

Rebase.

michaelmaitland removed a parent revision: D149495: [RISCV] Add support for V extension in SiFive7.May 2 2023, 5:53 PM
Harbormaster completed remote builds in B229579: Diff 518924.May 2 2023, 6:53 PM
Closed by commit rGcd02b69e75dd: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td (authored by michaelmaitland). · Explain WhyMay 5 2023, 7:55 AM
This revision was automatically updated to reflect the committed changes.
michaelmaitland added a commit: rGcd02b69e75dd: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td.
michaelmaitland added a reverting change: rG139ece35d893: Revert "[RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7..May 5 2023, 8:02 AM
michaelmaitland added a comment.May 5 2023, 10:15 AM

This revision needs to be reopened because it was committed with changes that are not relevant to this patch.

michaelmaitland reopened this revision.May 5 2023, 10:15 AM
This revision is now accepted and ready to land.May 5 2023, 10:15 AM
michaelmaitland updated this revision to Diff 519921.May 5 2023, 10:16 AM

Rebase.

This revision was landed with ongoing or failed builds.May 5 2023, 10:16 AM
Closed by commit rGf9fa8a599704: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td (authored by michaelmaitland). · Explain Why
This revision was automatically updated to reflect the committed changes.
michaelmaitland added a commit: rGf9fa8a599704: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td.
Harbormaster completed remote builds in B230288: Diff 519921.May 5 2023, 10:53 AM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
210 lines

Diff 519854

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Linesdef : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
let Latency = 16; let Latency = 16;
let ResourceCycles = [1, 15]; let ResourceCycles = [1, 15];
} }
def : WriteRes<WriteIDiv32, [SiFive7PipeB, SiFive7IDiv]> { def : WriteRes<WriteIDiv32, [SiFive7PipeB, SiFive7IDiv]> {
let Latency = 16; let Latency = 16;
let ResourceCycles = [1, 15]; let ResourceCycles = [1, 15];
} }
// Bitmanip
let Latency = 3 in {
// Rotates are in the late-B ALU.
def : WriteRes<WriteRotateImm, [SiFive7PipeB]>;
def : WriteRes<WriteRotateImm32, [SiFive7PipeB]>;
def : WriteRes<WriteRotateReg, [SiFive7PipeB]>;
def : WriteRes<WriteRotateReg32, [SiFive7PipeB]>;
// clz[w]/ctz[w] are in the late-B ALU.
def : WriteRes<WriteCLZ, [SiFive7PipeB]>;
def : WriteRes<WriteCLZ32, [SiFive7PipeB]>;
def : WriteRes<WriteCTZ, [SiFive7PipeB]>;
def : WriteRes<WriteCTZ32, [SiFive7PipeB]>;
// cpop[w] look exactly like multiply.
def : WriteRes<WriteCPOP, [SiFive7PipeB]>;
def : WriteRes<WriteCPOP32, [SiFive7PipeB]>;
// orc.b is in the late-B ALU.
def : WriteRes<WriteORCB, [SiFive7PipeB]>;
// rev8 is in the late-A and late-B ALUs.
def : WriteRes<WriteREV8, [SiFive7PipeAB]>;
// shNadd[.uw] is on the early-B and late-B ALUs.
def : WriteRes<WriteSHXADD, [SiFive7PipeB]>;
def : WriteRes<WriteSHXADD32, [SiFive7PipeB]>;
}
// Memory // Memory
def : WriteRes<WriteSTB, [SiFive7PipeA]>; def : WriteRes<WriteSTB, [SiFive7PipeA]>;
def : WriteRes<WriteSTH, [SiFive7PipeA]>; def : WriteRes<WriteSTH, [SiFive7PipeA]>;
def : WriteRes<WriteSTW, [SiFive7PipeA]>; def : WriteRes<WriteSTW, [SiFive7PipeA]>;
def : WriteRes<WriteSTD, [SiFive7PipeA]>; def : WriteRes<WriteSTD, [SiFive7PipeA]>;
def : WriteRes<WriteFST32, [SiFive7PipeA]>; def : WriteRes<WriteFST32, [SiFive7PipeA]>;
def : WriteRes<WriteFST64, [SiFive7PipeA]>; def : WriteRes<WriteFST64, [SiFive7PipeA]>;
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
def : ReadAdvance<ReadFMovI32ToF32, 0>; def : ReadAdvance<ReadFMovI32ToF32, 0>;
def : ReadAdvance<ReadFMovF64ToI64, 0>; def : ReadAdvance<ReadFMovF64ToI64, 0>;
def : ReadAdvance<ReadFMovI64ToF64, 0>; def : ReadAdvance<ReadFMovI64ToF64, 0>;
def : ReadAdvance<ReadFClass32, 0>; def : ReadAdvance<ReadFClass32, 0>;
def : ReadAdvance<ReadFClass64, 0>; def : ReadAdvance<ReadFClass64, 0>;
def : ReadAdvance<ReadSFB, 0>; def : ReadAdvance<ReadSFB, 0>;
// 6. Configuration-Setting Instructions
def : ReadAdvance<ReadVSETVLI, 2>;
def : ReadAdvance<ReadVSETVL, 2>;
// 7. Vector Loads and Stores
def : ReadAdvance<ReadVLDX, 0>;
def : ReadAdvance<ReadVSTX, 0>;
defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
defm "" : LMULReadAdvance<"ReadVSTM", 0>;
def : ReadAdvance<ReadVLDSX, 0>;
def : ReadAdvance<ReadVSTSX, 0>;
defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
// LMUL Aware
def : ReadAdvance<ReadVST1R, 0>;
def : ReadAdvance<ReadVST2R, 0>;
def : ReadAdvance<ReadVST4R, 0>;
def : ReadAdvance<ReadVST8R, 0>;
// 12. Vector Integer Arithmetic Instructions
defm : LMULReadAdvance<"ReadVIALUV", 0>;
defm : LMULReadAdvance<"ReadVIALUX", 0>;
defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;
defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;
defm : LMULReadAdvance<"ReadVExtV", 0>;
defm : LMULReadAdvance<"ReadVICALUV", 0>;
defm : LMULReadAdvance<"ReadVICALUX", 0>;
defm : LMULReadAdvance<"ReadVShiftV", 0>;
defm : LMULReadAdvance<"ReadVShiftX", 0>;
defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;
defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;
defm : LMULReadAdvance<"ReadVICmpV", 0>;
defm : LMULReadAdvance<"ReadVICmpX", 0>;
defm : LMULReadAdvance<"ReadVIMulV", 0>;
defm : LMULReadAdvance<"ReadVIMulX", 0>;
defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;
defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;
defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;
defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;
defm : LMULReadAdvance<"ReadVIMulAddV", 0>;
defm : LMULReadAdvance<"ReadVIMulAddX", 0>;
defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
defm : LMULReadAdvance<"ReadVIMergeV", 0>;
defm : LMULReadAdvance<"ReadVIMergeX", 0>;
defm : LMULReadAdvance<"ReadVIMovV", 0>;
defm : LMULReadAdvance<"ReadVIMovX", 0>;
// 13. Vector Fixed-Point Arithmetic Instructions
defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
// 14. Vector Floating-Point Instructions
defm "" : LMULReadAdvance<"ReadVFALUV", 0>;
defm "" : LMULReadAdvance<"ReadVFALUF", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>;
defm "" : LMULReadAdvance<"ReadVFMulV", 0>;
defm "" : LMULReadAdvance<"ReadVFMulF", 0>;
defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>;
defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>;
defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>;
defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
defm "" : LMULReadAdvance<"ReadVFRecpV", 0>;
defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>;
defm "" : LMULReadAdvance<"ReadVFSgnjF", 0>;
defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>;
defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
// 15. Vector Reduction Operations
def : ReadAdvance<ReadVIRedV, 0>;
def : ReadAdvance<ReadVIRedV0, 0>;
def : ReadAdvance<ReadVIWRedV, 0>;
def : ReadAdvance<ReadVIWRedV0, 0>;
def : ReadAdvance<ReadVFRedV, 0>;
def : ReadAdvance<ReadVFRedV0, 0>;
def : ReadAdvance<ReadVFRedOV, 0>;
def : ReadAdvance<ReadVFRedOV0, 0>;
def : ReadAdvance<ReadVFWRedV, 0>;
def : ReadAdvance<ReadVFWRedV0, 0>;
def : ReadAdvance<ReadVFWRedOV, 0>;
def : ReadAdvance<ReadVFWRedOV0, 0>;
// 16. Vector Mask Instructions
defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
// 17. Vector Permutation Instructions
defm "" : LMULReadAdvance<"ReadVIMovVX", 0>;
defm "" : LMULReadAdvance<"ReadVIMovXV", 0>;
defm "" : LMULReadAdvance<"ReadVIMovXX", 0>;
defm "" : LMULReadAdvance<"ReadVFMovVF", 0>;
defm "" : LMULReadAdvance<"ReadVFMovFV", 0>;
defm "" : LMULReadAdvance<"ReadVFMovFX", 0>;
defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
// LMUL Aware
def : ReadAdvance<ReadVMov1V, 0>;
def : ReadAdvance<ReadVMov2V, 0>;
def : ReadAdvance<ReadVMov4V, 0>;
def : ReadAdvance<ReadVMov8V, 0>;
// Others
def : ReadAdvance<ReadVMask, 0>;
// Bitmanip
def : ReadAdvance<ReadRotateImm, 0>;
def : ReadAdvance<ReadRotateImm32, 0>;
def : ReadAdvance<ReadRotateReg, 0>;
def : ReadAdvance<ReadRotateReg32, 0>;
def : ReadAdvance<ReadCLZ, 0>;
def : ReadAdvance<ReadCLZ32, 0>;
def : ReadAdvance<ReadCTZ, 0>;
def : ReadAdvance<ReadCTZ32, 0>;
def : ReadAdvance<ReadCPOP, 0>;
def : ReadAdvance<ReadCPOP32, 0>;
def : ReadAdvance<ReadORCB, 0>;
def : ReadAdvance<ReadREV8, 0>;
def : ReadAdvance<ReadSHXADD, 0>;
def : ReadAdvance<ReadSHXADD32, 0>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Unsupported extensions // Unsupported extensions
defm : UnsupportedSchedV; defm : UnsupportedSchedV;
defm : UnsupportedSchedZba;
defm : UnsupportedSchedZbb;
defm : UnsupportedSchedZbc; defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbs; defm : UnsupportedSchedZbs;
defm : UnsupportedSchedZbkb; defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx; defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfa; defm : UnsupportedSchedZfa;
defm : UnsupportedSchedZfh; defm : UnsupportedSchedZfh;
} }