This is an archive of the discontinued LLVM Phabricator instance.

Differential D149415

[ValueTracking] Add logic for `isKnownNonZero(umax X, Y)`
ClosedPublic

Authored by goldstein.w.n on Apr 27 2023, 11:21 PM.

Details

Reviewers
StephenFan
nikic
spatel
Commits
rG883daa7ac411: [ValueTracking] Add logic for `isKnownNonZero(umax X, Y)`
Summary

(umax X, Y) != 0 -> X != 0 || Y != 0

Alive2 Link:

https://alive2.llvm.org/ce/z/_Z9AUT

Diff Detail

Event Timeline

goldstein.w.n created this revision.Apr 27 2023, 11:21 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 27 2023, 11:21 PM
Herald added a subscriber: hiraditya. · View Herald Transcript
goldstein.w.n requested review of this revision.Apr 27 2023, 11:21 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 27 2023, 11:21 PM
Herald added subscribers: llvm-commits, • pcwang-thead. · View Herald Transcript
Harbormaster completed remote builds in B228735: Diff 517799.Apr 27 2023, 11:21 PM
goldstein.w.n added a parent revision: D149414: [ValueTracking] Add logic for `isKnownNonZero(sadd.sat X, Y)`.Apr 27 2023, 11:26 PM
nikic accepted this revision.Apr 28 2023, 12:35 AM

LGTM

This revision is now accepted and ready to land.Apr 28 2023, 12:35 AM
goldstein.w.n added a child revision: D149416: [ValueTracking] Add logic for `isKnownNonZero(umin X, Y)`.Apr 28 2023, 2:33 PM
goldstein.w.n updated this revision to Diff 518179.Apr 29 2023, 9:14 AM

Rebase

Harbormaster completed remote builds in B229020: Diff 518179.Apr 29 2023, 10:44 AM
goldstein.w.n updated this revision to Diff 518210.Apr 29 2023, 11:42 AM

Rebase

Harbormaster completed remote builds in B229046: Diff 518210.Apr 29 2023, 1:29 PM
goldstein.w.n updated this revision to Diff 518248.Apr 29 2023, 3:09 PM

Rebase

Harbormaster completed remote builds in B229080: Diff 518248.Apr 29 2023, 4:41 PM
Closed by commit rG883daa7ac411: [ValueTracking] Add logic for `isKnownNonZero(umax X, Y)` (authored by goldstein.w.n). · Explain WhyApr 30 2023, 8:07 AM
This revision was automatically updated to reflect the committed changes.
goldstein.w.n added a commit: rG883daa7ac411: [ValueTracking] Add logic for `isKnownNonZero(umax X, Y)`.

Revision Contents

PathSize
llvm/
lib/
Analysis/
1 line
test/
Analysis/
ValueTracking/
5 lines
Transforms/
LoopVectorize/
4 lines

Diff 518324

llvm/lib/Analysis/ValueTracking.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,930 Lines • ▼ Show 20 Lines if (auto *II = dyn_cast<IntrinsicInst>(I)) {
break; break;
case Intrinsic::ssub_sat: case Intrinsic::ssub_sat:
return isNonZeroSub(DemandedElts, Depth, Q, BitWidth, return isNonZeroSub(DemandedElts, Depth, Q, BitWidth,
II->getArgOperand(0), II->getArgOperand(1)); II->getArgOperand(0), II->getArgOperand(1));
case Intrinsic::sadd_sat: case Intrinsic::sadd_sat:
return isNonZeroAdd(DemandedElts, Depth, Q, BitWidth, return isNonZeroAdd(DemandedElts, Depth, Q, BitWidth,
II->getArgOperand(0), II->getArgOperand(1), II->getArgOperand(0), II->getArgOperand(1),
/*NSW*/ true); /*NSW*/ true);
case Intrinsic::umax:
case Intrinsic::uadd_sat: case Intrinsic::uadd_sat:
if (isKnownNonZero(II->getArgOperand(0), DemandedElts, Depth, Q) || if (isKnownNonZero(II->getArgOperand(0), DemandedElts, Depth, Q) ||
isKnownNonZero(II->getArgOperand(1), DemandedElts, Depth, Q)) isKnownNonZero(II->getArgOperand(1), DemandedElts, Depth, Q))
return true; return true;
break; break;
case Intrinsic::cttz: case Intrinsic::cttz:
return computeKnownBits(II->getArgOperand(0), DemandedElts, Depth, Q) return computeKnownBits(II->getArgOperand(0), DemandedElts, Depth, Q)
.Zero[0]; .Zero[0];
▲ Show 20 Lines • Show All 5,759 Lines • Show Last 20 Lines

llvm/test/Analysis/ValueTracking/known-non-zero.ll

Show First 20 Lines • Show All 955 Lines • ▼ Show 20 Lines;
%r = icmp eq i8 %z, 0 %r = icmp eq i8 %z, 0
ret i1 %r ret i1 %r
} }
define i1 @umax_nonzero(i8 %xx, i8 %yy, i8 %ind) { define i1 @umax_nonzero(i8 %xx, i8 %yy, i8 %ind) {
; CHECK-LABEL: @umax_nonzero( ; CHECK-LABEL: @umax_nonzero(
; CHECK-NEXT: [[X_NZ:%.*]] = icmp ne i8 [[XX:%.*]], 0 ; CHECK-NEXT: [[X_NZ:%.*]] = icmp ne i8 [[XX:%.*]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[X_NZ]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[X_NZ]])
; CHECK-NEXT: [[X:%.*]] = call i8 @llvm.umax.i8(i8 [[XX]], i8 [[YY:%.*]]) ; CHECK-NEXT: ret i1 false
; CHECK-NEXT: [[Z:%.*]] = or i8 [[X]], [[IND:%.*]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[Z]], 0
; CHECK-NEXT: ret i1 [[R]]
; ;
%x_nz = icmp ne i8 %xx, 0 %x_nz = icmp ne i8 %xx, 0
call void @llvm.assume(i1 %x_nz) call void @llvm.assume(i1 %x_nz)
%x = call i8 @llvm.umax.i8(i8 %xx, i8 %yy) %x = call i8 @llvm.umax.i8(i8 %xx, i8 %yy)
%z = or i8 %x, %ind %z = or i8 %x, %ind
%r = icmp eq i8 %z, 0 %r = icmp eq i8 %z, 0
ret i1 %r ret i1 %r
} }
▲ Show 20 Lines • Show All 141 Lines • Show Last 20 Lines

llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll

Show First 20 Lines • Show All 477 Lines • ▼ Show 20 Lines
; B[i/2] = A[i] * 2; ; B[i/2] = A[i] * 2;
; } ; }
define void @even_load_dynamic_tc(ptr noalias nocapture readonly %A, ptr noalias nocapture %B, i64 %N) { define void @even_load_dynamic_tc(ptr noalias nocapture readonly %A, ptr noalias nocapture %B, i64 %N) {
; CHECK-LABEL: @even_load_dynamic_tc( ; CHECK-LABEL: @even_load_dynamic_tc(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N:%.*]], i64 2) ; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N:%.*]], i64 2)
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], -1 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 9
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph: ; CHECK: vector.ph:
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], -1
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 1 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 1
; CHECK-NEXT: [[TMP2:%.*]] = add nuw i64 [[TMP1]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = add nuw i64 [[TMP1]], 1
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP2]], 3 ; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i64 4, i64 [[N_MOD_VF]] ; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i64 4, i64 [[N_MOD_VF]]
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[TMP4]] ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[TMP4]]
; CHECK-NEXT: [[IND_END:%.*]] = shl i64 [[N_VEC]], 1 ; CHECK-NEXT: [[IND_END:%.*]] = shl i64 [[N_VEC]], 1
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
▲ Show 20 Lines • Show All 1,085 Lines • Show Last 20 Lines