[GlobalISel][InlineAsm][X86]Fallback on DAG ISel when lowering inline assembly

[mingmingl]

Summary

Currently inline assembly lowering reports error as shown in https://gcc.godbolt.org/z/Kdx7e3n9M

• This doesn't fix https://github.com/llvm/llvm-project/issues/62343 but gives a workaround by tuning 'global-isel-abort'.

[mingmingl]

undo the change in CodeGen/GlobalISel/IRTranslator.cpp as they are not relevant in this patch (the call to fallback ) in IRTranslator::translate will return false so translateInlineAsm won't be executed.

[arsenm]

I don't understand why this needs to be special cased. The regular fallback seems to work expected as-is.

[mingmingl]

https://gcc.godbolt.org/z/vq4nGG793 shows setting global-isel-abort to DisableWithDiag indeed works.

Thinking back what I have in mind when writing this patch, I misunderstood how I shall use fallBackToDAGISel (thought the fallback path would also call this method )-> in fact, when IRTranslator handles translation error, it sets properties on machine-function; and let codegen pass builder to decide whether to restore machine function and falls back to selection-dag-based ISel (decided by -global-isel-abort mode)

[arsenm]

In D149211#4297740, @mingmingl wrote:

https://gcc.godbolt.org/z/vq4nGG793 shows setting global-isel-abort to DisableWithDiag indeed works.

Thinking back what I have in mind when writing this patch, I misunderstood how I shall use fallBackToDAGISel (thought the fallback path would also call this method )-> in fact, when IRTranslator handles translation error, it sets properties on machine-function; and let codegen pass builder to decide whether to restore machine function and falls back to selection-dag-based ISel (decided by -global-isel-abort mode)

IIRC the only reason that exists was for a compile time hack for common cases that would fall back.

llvm/lib/Target/X86/X86ISelLowering.h

bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
                                  const SelectionDAG &DAG,
                                  const MachineMemOperand &MMO) const override;
 
     /// Intel processors have a unified instruction and data cache
     const char * getClearCacheBuiltinName() const override {
       return nullptr; // nothing to do, move along.
     }
 
+    bool fallBackToDAGISel(const Instruction& Inst) const override;
+
     Register getRegisterByName(const char* RegName, LLT VT,
                                const MachineFunction &MF) const override;
 
     /// If a physical register, this returns the register that receives the
     /// exception address on entry to an EH pad.
     Register
     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
 

llvm/lib/Target/X86/X86ISelLowering.cpp

assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
          "Invalid Frame Register!");
   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
   while (Depth--)
     FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
                             MachinePointerInfo());
   return FrameAddr;
 }
 
+bool X86TargetLowering::fallBackToDAGISel(const Instruction& Inst) const {
+  auto* CI = dyn_cast<CallInst>(&Inst);
+
+  return CI && CI->isInlineAsm();
+}
+
 // FIXME? Maybe this could be a TableGen attribute on some registers and
 // this table could be generated automatically from RegInfo.
 Register X86TargetLowering::getRegisterByName(const char* RegName, LLT VT,
                                               const MachineFunction &MF) const {
   const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
 
   Register Reg = StringSwitch<unsigned>(RegName)
                        .Case("esp", X86::ESP)

llvm/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll

 ; FALLBACK-WITH-REPORT-OUT-LABEL: ScaleObjectOverwrite_2:
 %struct.PointListStruct = type { ptr, ptr }
 declare void @ScaleObjectOverwrite_3(ptr %index, ptr byval(%struct.PointListStruct) %index2)
 define void @ScaleObjectOverwrite_2(ptr %index) {
 entry:
   call void @ScaleObjectOverwrite_3(ptr %index, ptr byval(%struct.PointListStruct) %index)
   ret void
 }
+
+; Check that inline assembly lowering falls back to instruction selection.
+; FALLBACK-WITH-REPORT-ERR: <unknown>:0:0: unable to translate instruction: call: '  %2 = tail call i32 asm "and $$3, ${0:k}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %0)' (in function: inline_asm_func)
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for inline_asm_func
+; FALLBACK-WITH-REPORT-OUT-LABEL: inline_asm_func:
+define i32 @inline_asm_func(i32 %0) {
+  %2 = tail call i32 asm "and $$3, ${0:k}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %0)
+  ret i32 %2
+}