[PowerPC] Rename fp/int conversion nodes

[qiucf]

Summary

PowerPC backend uses FCFID* and FCTI(D|W)* as custom ISD node name for in-place conversion between float and integers. But we do not always use these instructions.

Also, separate nodes from int to f32/f64/f128 are not needed, since we can differentiate them by node types.

[qiucf]

Migrated to https://github.com/llvm/llvm-project/pull/67303

llvm/lib/Target/PowerPC/PPCISelLowering.h

     /// FSEL - Traditional three-operand fsel node.
     ///
     FSEL,
 
     /// XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.
     XSMAXC,
     XSMINC,
 
-    /// FCFID - The FCFID instruction, taking an f64 operand and producing
-    /// and f64 value containing the FP representation of the integer that
-    /// was temporarily in the f64 operand.
-    FCFID,
-
-    /// Newer FCFID[US] integer-to-floating-point conversion instructions for
-    /// unsigned integers and single-precision outputs.
-    FCFIDU,
-    FCFIDS,
-    FCFIDUS,
-
-    /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
-    /// operand, producing an f64 value containing the integer representation
-    /// of that FP value.
-    FCTIDZ,
-    FCTIWZ,
-
-    /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
-    /// unsigned integers with round toward zero.
-    FCTIDUZ,
-    FCTIWUZ,
+    /// Inplace integer-to-float conversion.
+    SINT_TO_FP_INREG,
+    UINT_TO_FP_INREG,
+
+    /// Inplace float-to-integer conversion.
+    FP_TO_I64_INREG,
+    FP_TO_I32_INREG,
+    FP_TO_U64_INREG,
+    FP_TO_U32_INREG,
 
     /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
     /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
     VEXTS,
 
     /// Reciprocal estimate instructions (unary FP ops).
     FRE,
     FRSQRTE,

     /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same
     /// element type.
     EXTRACT_VSX_REG,
 
     /// XXMFACC = This corresponds to the xxmfacc instruction.
     XXMFACC,
 
     // Constrained conversion from floating point to int
-    STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE,
-    STRICT_FCTIWZ,
-    STRICT_FCTIDUZ,
-    STRICT_FCTIWUZ,
+    STRICT_FP_TO_I64_INREG = ISD::FIRST_TARGET_STRICTFP_OPCODE,
+    STRICT_FP_TO_I32_INREG,
+    STRICT_FP_TO_U64_INREG,
+    STRICT_FP_TO_U32_INREG,
 
     /// Constrained integer-to-floating-point conversion instructions.
-    STRICT_FCFID,
-    STRICT_FCFIDU,
-    STRICT_FCFIDS,
-    STRICT_FCFIDUS,
+    STRICT_SINT_TO_FP_INREG,
+    STRICT_UINT_TO_FP_INREG,
 
     /// Constrained floating point add in round-to-zero mode.
     STRICT_FADDRTZ,
 
     // NOTE: The nodes below may require PC-Rel specific patterns if the
     // address could be PC-Relative. When adding new nodes below, consider
     // whether or not the address can be PC-Relative and add the corresponding
     // PC-relative patterns and tests.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 }
 
 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((PPCISD::NodeType)Opcode) {
   case PPCISD::FIRST_NUMBER:    break;
   case PPCISD::FSEL:            return "PPCISD::FSEL";
   case PPCISD::XSMAXC:          return "PPCISD::XSMAXC";
   case PPCISD::XSMINC:          return "PPCISD::XSMINC";
-  case PPCISD::FCFID:           return "PPCISD::FCFID";
-  case PPCISD::FCFIDU:          return "PPCISD::FCFIDU";
-  case PPCISD::FCFIDS:          return "PPCISD::FCFIDS";
-  case PPCISD::FCFIDUS:         return "PPCISD::FCFIDUS";
-  case PPCISD::FCTIDZ:          return "PPCISD::FCTIDZ";
-  case PPCISD::FCTIWZ:          return "PPCISD::FCTIWZ";
-  case PPCISD::FCTIDUZ:         return "PPCISD::FCTIDUZ";
-  case PPCISD::FCTIWUZ:         return "PPCISD::FCTIWUZ";
+  case PPCISD::SINT_TO_FP_INREG:
+    return "PPCISD::SINT_TO_FP_INREG";
+  case PPCISD::UINT_TO_FP_INREG:
+    return "PPCISD::UINT_TO_FP_INREG";
+  case PPCISD::FP_TO_I64_INREG:
+    return "PPCISD::FP_TO_I64_INREG";
+  case PPCISD::FP_TO_I32_INREG:
+    return "PPCISD::FP_TO_I32_INREG";
+  case PPCISD::FP_TO_U64_INREG:
+    return "PPCISD::FP_TO_U64_INREG";
+  case PPCISD::FP_TO_U32_INREG:
+    return "PPCISD::FP_TO_U32_INREG";
   case PPCISD::FRE:             return "PPCISD::FRE";
   case PPCISD::FRSQRTE:         return "PPCISD::FRSQRTE";
   case PPCISD::FTSQRT:
     return "PPCISD::FTSQRT";
   case PPCISD::FSQRT:
     return "PPCISD::FSQRT";
   case PPCISD::STFIWX:          return "PPCISD::STFIWX";
   case PPCISD::VPERM:           return "PPCISD::VPERM";

   case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
   case PPCISD::XXMFACC:         return "PPCISD::XXMFACC";
   case PPCISD::LD_SPLAT:        return "PPCISD::LD_SPLAT";
   case PPCISD::ZEXT_LD_SPLAT:   return "PPCISD::ZEXT_LD_SPLAT";
   case PPCISD::SEXT_LD_SPLAT:   return "PPCISD::SEXT_LD_SPLAT";
   case PPCISD::FNMSUB:          return "PPCISD::FNMSUB";
   case PPCISD::STRICT_FADDRTZ:
     return "PPCISD::STRICT_FADDRTZ";
-  case PPCISD::STRICT_FCTIDZ:
-    return "PPCISD::STRICT_FCTIDZ";
-  case PPCISD::STRICT_FCTIWZ:
-    return "PPCISD::STRICT_FCTIWZ";
-  case PPCISD::STRICT_FCTIDUZ:
-    return "PPCISD::STRICT_FCTIDUZ";
-  case PPCISD::STRICT_FCTIWUZ:
-    return "PPCISD::STRICT_FCTIWUZ";
-  case PPCISD::STRICT_FCFID:
-    return "PPCISD::STRICT_FCFID";
-  case PPCISD::STRICT_FCFIDU:
-    return "PPCISD::STRICT_FCFIDU";
-  case PPCISD::STRICT_FCFIDS:
-    return "PPCISD::STRICT_FCFIDS";
-  case PPCISD::STRICT_FCFIDUS:
-    return "PPCISD::STRICT_FCFIDUS";
+  case PPCISD::STRICT_FP_TO_I64_INREG:
+    return "PPCISD::STRICT_FP_TO_I64_INREG";
+  case PPCISD::STRICT_FP_TO_I32_INREG:
+    return "PPCISD::STRICT_FP_TO_I32_INREG";
+  case PPCISD::STRICT_FP_TO_U64_INREG:
+    return "PPCISD::STRICT_FP_TO_U64_INREG";
+  case PPCISD::STRICT_FP_TO_U32_INREG:
+    return "PPCISD::STRICT_FP_TO_U32_INREG";
+  case PPCISD::STRICT_SINT_TO_FP_INREG:
+    return "PPCISD::STRICT_SINT_TO_FP_INREG";
+  case PPCISD::STRICT_UINT_TO_FP_INREG:
+    return "PPCISD::STRICT_UINT_TO_FP_INREG";
   case PPCISD::LXVRZX:          return "PPCISD::LXVRZX";
   case PPCISD::STORE_COND:
     return "PPCISD::STORE_COND";
   }
   return nullptr;
 }
 
 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,

   }
   return Op;
 }
 
 static unsigned getPPCStrictOpcode(unsigned Opc) {
   switch (Opc) {
   default:
     llvm_unreachable("No strict version of this opcode!");
-  case PPCISD::FCTIDZ:
-    return PPCISD::STRICT_FCTIDZ;
-  case PPCISD::FCTIWZ:
-    return PPCISD::STRICT_FCTIWZ;
-  case PPCISD::FCTIDUZ:
-    return PPCISD::STRICT_FCTIDUZ;
-  case PPCISD::FCTIWUZ:
-    return PPCISD::STRICT_FCTIWUZ;
-  case PPCISD::FCFID:
-    return PPCISD::STRICT_FCFID;
-  case PPCISD::FCFIDU:
-    return PPCISD::STRICT_FCFIDU;
-  case PPCISD::FCFIDS:
-    return PPCISD::STRICT_FCFIDS;
-  case PPCISD::FCFIDUS:
-    return PPCISD::STRICT_FCFIDUS;
+  case PPCISD::FP_TO_I64_INREG:
+    return PPCISD::STRICT_FP_TO_I64_INREG;
+  case PPCISD::FP_TO_I32_INREG:
+    return PPCISD::STRICT_FP_TO_I32_INREG;
+  case PPCISD::FP_TO_U64_INREG:
+    return PPCISD::STRICT_FP_TO_U64_INREG;
+  case PPCISD::FP_TO_U32_INREG:
+    return PPCISD::STRICT_FP_TO_U32_INREG;
+  case PPCISD::SINT_TO_FP_INREG:
+    return PPCISD::STRICT_SINT_TO_FP_INREG;
+  case PPCISD::UINT_TO_FP_INREG:
+    return PPCISD::STRICT_UINT_TO_FP_INREG;
   }
 }
 
 static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
                               const PPCSubtarget &Subtarget) {
   SDLoc dl(Op);
   bool IsStrict = Op->isStrictFPOpcode();
   bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT ||

       Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
   }
   if ((DestTy == MVT::i8 || DestTy == MVT::i16) && Subtarget.hasP9Vector())
     DestTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
   unsigned Opc = ISD::DELETED_NODE;
   switch (DestTy.SimpleTy) {
   default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
   case MVT::i32:
-    Opc = IsSigned ? PPCISD::FCTIWZ
-                   : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ);
+    Opc = IsSigned ? PPCISD::FP_TO_I32_INREG
+                   : (Subtarget.hasFPCVT() ? PPCISD::FP_TO_U32_INREG
+                                           : PPCISD::FP_TO_I64_INREG);
     break;
   case MVT::i64:
     assert((IsSigned || Subtarget.hasFPCVT()) &&
            "i64 FP_TO_UINT is supported only with FPCVT");
-    Opc = IsSigned ? PPCISD::FCTIDZ : PPCISD::FCTIDUZ;
+    Opc = IsSigned ? PPCISD::FP_TO_I64_INREG : PPCISD::FP_TO_U64_INREG;
   }
   EVT ConvTy = Src.getValueType() == MVT::f128 ? MVT::f128 : MVT::f64;
   SDValue Conv;
   if (IsStrict) {
     Opc = getPPCStrictOpcode(Opc);
     Conv = DAG.getNode(Opc, dl, DAG.getVTList(ConvTy, MVT::Other), {Chain, Src},
                        Flags);
   } else {

 
   // TODO: Any other flags to propagate?
   SDNodeFlags Flags;
   Flags.setNoFPExcept(Op->getFlags().hasNoFPExcept());
 
   // If we have FCFIDS, then use it when converting to single-precision.
   // Otherwise, convert to double-precision and then round.
   bool IsSingle = Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT();
-  unsigned ConvOpc = IsSingle ? (IsSigned ? PPCISD::FCFIDS : PPCISD::FCFIDUS)
-                              : (IsSigned ? PPCISD::FCFID : PPCISD::FCFIDU);
+  unsigned ConvOpc =
+      IsSigned ? PPCISD::SINT_TO_FP_INREG : PPCISD::UINT_TO_FP_INREG;
   EVT ConvTy = IsSingle ? MVT::f32 : MVT::f64;
   if (Op->isStrictFPOpcode()) {
     if (!Chain)
       Chain = Op.getOperand(0);
     return DAG.getNode(getPPCStrictOpcode(ConvOpc), dl,
                        DAG.getVTList(ConvTy, MVT::Other), {Chain, Src}, Flags);
   } else
     return DAG.getNode(ConvOpc, dl, ConvTy, Src);

 
   SDValue FirstInput = N->getOperand(0);
   assert(FirstInput.getOpcode() == PPCISD::MFVSR &&
          "The input operand must be an fp-to-int conversion.");
 
   // This combine happens after legalization so the fp_to_[su]i nodes are
   // already converted to PPCSISD nodes.
   unsigned FirstConversion = FirstInput.getOperand(0).getOpcode();
-  if (FirstConversion == PPCISD::FCTIDZ ||
-      FirstConversion == PPCISD::FCTIDUZ ||
-      FirstConversion == PPCISD::FCTIWZ ||
-      FirstConversion == PPCISD::FCTIWUZ) {
+  if (FirstConversion == PPCISD::FP_TO_I64_INREG ||
+      FirstConversion == PPCISD::FP_TO_U64_INREG ||
+      FirstConversion == PPCISD::FP_TO_I32_INREG ||
+      FirstConversion == PPCISD::FP_TO_U32_INREG) {
     bool IsSplat = true;
-    bool Is32Bit = FirstConversion == PPCISD::FCTIWZ ||
-      FirstConversion == PPCISD::FCTIWUZ;
+    bool Is32Bit = FirstConversion == PPCISD::FP_TO_I32_INREG ||
+                   FirstConversion == PPCISD::FP_TO_U32_INREG;
     EVT SrcVT = FirstInput.getOperand(0).getValueType();
     SmallVector<SDValue, 4> Ops;
     EVT TargetVT = N->getValueType(0);
     for (int i = 0, e = N->getNumOperands(); i < e; ++i) {
       SDValue NextOp = N->getOperand(i);
       if (NextOp.getOpcode() != PPCISD::MFVSR)
         return SDValue();
       unsigned NextConversion = NextOp.getOperand(0).getOpcode();

                           DAG.getIntPtrConstant(1, dl, /*isTarget=*/true));
           Ops.push_back(Trunc);
         }
       } else
         Ops.push_back(In.isUndef() ? DAG.getUNDEF(SrcVT) : In.getOperand(0));
     }
 
     unsigned Opcode;
-    if (FirstConversion == PPCISD::FCTIDZ ||
-        FirstConversion == PPCISD::FCTIWZ)
+    if (FirstConversion == PPCISD::FP_TO_I64_INREG ||
+        FirstConversion == PPCISD::FP_TO_I32_INREG)
       Opcode = ISD::FP_TO_SINT;
     else
       Opcode = ISD::FP_TO_UINT;
 
     EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32;
     SDValue BV = DAG.getBuildVector(NewVT, dl, Ops);
     return DAG.getNode(Opcode, dl, TargetVT, BV);
   }

 
   SDValue FirstOperand(Op.getOperand(0));
   bool SubWordLoad = FirstOperand.getOpcode() == ISD::LOAD &&
     (FirstOperand.getValueType() == MVT::i8 ||
      FirstOperand.getValueType() == MVT::i16);
   if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) {
     bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
     bool DstDouble = Op.getValueType() == MVT::f64;
-    unsigned ConvOp = Signed ?
-      (DstDouble ? PPCISD::FCFID  : PPCISD::FCFIDS) :
-      (DstDouble ? PPCISD::FCFIDU : PPCISD::FCFIDUS);
+    unsigned ConvOp =
+        Signed ? PPCISD::SINT_TO_FP_INREG : PPCISD::UINT_TO_FP_INREG;
     SDValue WidthConst =
       DAG.getIntPtrConstant(FirstOperand.getValueType() == MVT::i8 ? 1 : 2,
                             dl, false);
     LoadSDNode *LDN = cast<LoadSDNode>(FirstOperand.getNode());
     SDValue Ops[] = { LDN->getChain(), LDN->getBasePtr(), WidthConst };
     SDValue Ld = DAG.getMemIntrinsicNode(PPCISD::LXSIZX, dl,
                                          DAG.getVTList(MVT::f64, MVT::Other),
                                          Ops, MVT::i8, LDN->getMemOperand());

   if (Op.getOperand(0).getValueType() == MVT::i32)
     return SDValue();
 
   assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
          "UINT_TO_FP is supported only with FPCVT");
 
   // If we have FCFIDS, then use it when converting to single-precision.
   // Otherwise, convert to double-precision and then round.
-  unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
-                       ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
-                                                            : PPCISD::FCFIDS)
-                       : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
-                                                            : PPCISD::FCFID);
+  unsigned FCFOp = Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::UINT_TO_FP_INREG
+                                                     : PPCISD::SINT_TO_FP_INREG;
   MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
                   ? MVT::f32
                   : MVT::f64;
 
   // If we're converting from a float, to an int, and back to a float again,
   // then we don't need the store/load pair at all.
   if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
        Subtarget.hasFPCVT()) ||
       (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
     SDValue Src = Op.getOperand(0).getOperand(0);
     if (Src.getValueType() == MVT::f32) {
       Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
       DCI.AddToWorklist(Src.getNode());
     } else if (Src.getValueType() != MVT::f64) {
       // Make sure that we don't pick up a ppc_fp128 source value.
       return SDValue();
     }
 
-    unsigned FCTOp =
-      Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
-                                                        PPCISD::FCTIDUZ;
+    unsigned FCTOp = Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT
+                         ? PPCISD::FP_TO_I64_INREG
+                         : PPCISD::FP_TO_U64_INREG;
 
     SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
     SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
 
     if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
       FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
                        DAG.getIntPtrConstant(0, dl, /*isTarget=*/true));
       DCI.AddToWorklist(FP.getNode());

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 // Floating point instructions.
 //
 
 
 let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1,
     Uses = [RM] in {  // FPU Operations.
 defm FCFID  : XForm_26r<63, 846, (outs f8rc:$RST), (ins f8rc:$RB),
                         "fcfid", "$RST, $RB", IIC_FPGeneral,
-                        [(set f64:$RST, (PPCany_fcfid f64:$RB))]>, isPPC64;
+                        [(set f64:$RST, (PPCany_sint_to_fp f64:$RB))]>, isPPC64;
 defm FCTID  : XForm_26r<63, 814, (outs f8rc:$RST), (ins f8rc:$RB),
                         "fctid", "$RST, $RB", IIC_FPGeneral,
                         []>, isPPC64;
 defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$RST), (ins f8rc:$RB),
                         "fctidu", "$RST, $RB", IIC_FPGeneral,
                         []>, isPPC64;
 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$RST), (ins f8rc:$RB),
                         "fctidz", "$RST, $RB", IIC_FPGeneral,
-                        [(set f64:$RST, (PPCany_fctidz f64:$RB))]>, isPPC64;
+                        [(set f64:$RST, (PPCany_fp_to_i64 f64:$RB))]>, isPPC64;
 
 defm FCFIDU  : XForm_26r<63, 974, (outs f8rc:$RST), (ins f8rc:$RB),
                         "fcfidu", "$RST, $RB", IIC_FPGeneral,
-                        [(set f64:$RST, (PPCany_fcfidu f64:$RB))]>, isPPC64;
+                        [(set f64:$RST, (PPCany_uint_to_fp f64:$RB))]>, isPPC64;
 defm FCFIDS  : XForm_26r<59, 846, (outs f4rc:$RST), (ins f8rc:$RB),
                         "fcfids", "$RST, $RB", IIC_FPGeneral,
-                        [(set f32:$RST, (PPCany_fcfids f64:$RB))]>, isPPC64;
+                        [(set f32:$RST, (PPCany_sint_to_fp f64:$RB))]>, isPPC64;
 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$RST), (ins f8rc:$RB),
                         "fcfidus", "$RST, $RB", IIC_FPGeneral,
-                        [(set f32:$RST, (PPCany_fcfidus f64:$RB))]>, isPPC64;
+                        [(set f32:$RST, (PPCany_uint_to_fp f64:$RB))]>, isPPC64;
 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$RST), (ins f8rc:$RB),
                         "fctiduz", "$RST, $RB", IIC_FPGeneral,
-                        [(set f64:$RST, (PPCany_fctiduz f64:$RB))]>, isPPC64;
+                        [(set f64:$RST, (PPCany_fp_to_u64 f64:$RB))]>, isPPC64;
 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$RST), (ins f8rc:$RB),
                         "fctiwuz", "$RST, $RB", IIC_FPGeneral,
-                        [(set f64:$RST, (PPCany_fctiwuz f64:$RB))]>, isPPC64;
+                        [(set f64:$RST, (PPCany_fp_to_u32 f64:$RB))]>, isPPC64;
 }
 
 // These instructions store a hash computed from the value of the link register
 // and the value of the stack pointer.
 let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs),
                                 (ins g8rc:$RB, (memrihash $D, $RA):$addr),
                                 "hashst $RB, $addr", IIC_IntGeneral, []>;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 // PowerPC specific DAG Nodes.
 //
 
 def PPCfre    : SDNode<"PPCISD::FRE",     SDTFPUnaryOp, []>;
 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
 def PPCfsqrt  : SDNode<"PPCISD::FSQRT",   SDTFPUnaryOp, []>;
 def PPCftsqrt : SDNode<"PPCISD::FTSQRT",  SDT_PPCFtsqrt,[]>;
 
-def PPCfcfid  : SDNode<"PPCISD::FCFID",   SDTFPUnaryOp, []>;
-def PPCfcfidu : SDNode<"PPCISD::FCFIDU",  SDTFPUnaryOp, []>;
-def PPCfcfids : SDNode<"PPCISD::FCFIDS",  SDTFPRoundOp, []>;
-def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
-def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
-def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
-def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
-def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
-
-def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID",
-                             SDTFPUnaryOp, [SDNPHasChain]>;
-def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU",
-                              SDTFPUnaryOp, [SDNPHasChain]>;
-def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS",
-                             SDTFPRoundOp, [SDNPHasChain]>;
-def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS",
-                              SDTFPRoundOp, [SDNPHasChain]>;
-
-def PPCany_fcfid : PatFrags<(ops node:$op),
-                             [(PPCfcfid node:$op),
-                              (PPCstrict_fcfid node:$op)]>;
-def PPCany_fcfidu : PatFrags<(ops node:$op),
-                             [(PPCfcfidu node:$op),
-                              (PPCstrict_fcfidu node:$op)]>;
-def PPCany_fcfids : PatFrags<(ops node:$op),
-                              [(PPCfcfids node:$op),
-                               (PPCstrict_fcfids node:$op)]>;
-def PPCany_fcfidus : PatFrags<(ops node:$op),
-                              [(PPCfcfidus node:$op),
-                               (PPCstrict_fcfidus node:$op)]>;
+def SDTToFpInRegOp : SDTypeProfile<1, 1, [ SDTCisFP<0>, SDTCisVT<1, f64> ]>;
+def PPCsint_to_fp: SDNode<"PPCISD::SINT_TO_FP_INREG", SDTToFpInRegOp, []>;
+def PPCuint_to_fp: SDNode<"PPCISD::UINT_TO_FP_INREG", SDTToFpInRegOp, []>;
+def PPCfp_to_i64 : SDNode<"PPCISD::FP_TO_I64_INREG", SDTFPUnaryOp, []>;
+def PPCfp_to_i32 : SDNode<"PPCISD::FP_TO_I32_INREG", SDTFPUnaryOp, []>;
+def PPCfp_to_u64 : SDNode<"PPCISD::FP_TO_U64_INREG", SDTFPUnaryOp, []>;
+def PPCfp_to_u32 : SDNode<"PPCISD::FP_TO_U32_INREG", SDTFPUnaryOp, []>;
+
+def PPCstrict_sint_to_fp: SDNode<"PPCISD::STRICT_SINT_TO_FP_INREG",
+                                  SDTToFpInRegOp, [SDNPHasChain]>;
+def PPCstrict_uint_to_fp: SDNode<"PPCISD::STRICT_UINT_TO_FP_INREG",
+                                  SDTToFpInRegOp, [SDNPHasChain]>;
+
+def PPCany_sint_to_fp: PatFrags<(ops node:$op),
+                                [(PPCsint_to_fp node:$op),
+                                 (PPCstrict_sint_to_fp node:$op)]>;
+def PPCany_uint_to_fp: PatFrags<(ops node:$op),
+                                [(PPCuint_to_fp node:$op),
+                                 (PPCstrict_uint_to_fp node:$op)]>;
 
 def PPCstore_scal_int_from_vsr:
    SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr,
            [SDNPHasChain, SDNPMayStore]>;
 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
                        [SDNPHasChain, SDNPMayStore]>;
 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
                        [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;

 def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntShiftOp>;
 def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntShiftOp>;
 def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntShiftOp>;
 
 def PPCfnmsub     : SDNode<"PPCISD::FNMSUB"    , SDTFPTernaryOp>;
 
 def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>;
 
-def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ",
+def PPCstrict_fp_to_i64: SDNode<"PPCISD::STRICT_FP_TO_I64_INREG",
                                 SDTFPUnaryOp, [SDNPHasChain]>;
-def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ",
+def PPCstrict_fp_to_i32: SDNode<"PPCISD::STRICT_FP_TO_I32_INREG",
                                 SDTFPUnaryOp, [SDNPHasChain]>;
-def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ",
+def PPCstrict_fp_to_u64: SDNode<"PPCISD::STRICT_FP_TO_U64_INREG",
                                 SDTFPUnaryOp, [SDNPHasChain]>;
-def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ",
+def PPCstrict_fp_to_u32: SDNode<"PPCISD::STRICT_FP_TO_U32_INREG",
                                 SDTFPUnaryOp, [SDNPHasChain]>;
 
-def PPCany_fctidz : PatFrags<(ops node:$op),
-                             [(PPCstrict_fctidz node:$op),
-                              (PPCfctidz node:$op)]>;
-def PPCany_fctiwz : PatFrags<(ops node:$op),
-                             [(PPCstrict_fctiwz node:$op),
-                              (PPCfctiwz node:$op)]>;
-def PPCany_fctiduz : PatFrags<(ops node:$op),
-                              [(PPCstrict_fctiduz node:$op),
-                               (PPCfctiduz node:$op)]>;
-def PPCany_fctiwuz : PatFrags<(ops node:$op),
-                              [(PPCstrict_fctiwuz node:$op),
-                               (PPCfctiwuz node:$op)]>;
+def PPCany_fp_to_i64: PatFrags<(ops node:$op),
+                               [(PPCstrict_fp_to_i64 node:$op),
+                                (PPCfp_to_i64 node:$op)]>;
+def PPCany_fp_to_i32: PatFrags<(ops node:$op),
+                               [(PPCstrict_fp_to_i32 node:$op),
+                                (PPCfp_to_i32 node:$op)]>;
+def PPCany_fp_to_u64: PatFrags<(ops node:$op),
+                               [(PPCstrict_fp_to_u64 node:$op),
+                                (PPCfp_to_u64 node:$op)]>;
+def PPCany_fp_to_u32: PatFrags<(ops node:$op),
+                               [(PPCstrict_fp_to_u32 node:$op),
+                                (PPCfp_to_u32 node:$op)]>;
 
 // Move 2 i64 values into a VSX register
 def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128",
                            SDTypeProfile<1, 2,
                              [SDTCisFP<0>, SDTCisSameSizeAs<1,2>,
                               SDTCisSameAs<1,2>]>,
                            []>;
 

   defm FCTIW  : XForm_26r<63, 14, (outs f8rc:$RST), (ins f8rc:$RB),
                           "fctiw", "$RST, $RB", IIC_FPGeneral,
                           []>;
   defm FCTIWU  : XForm_26r<63, 142, (outs f8rc:$RST), (ins f8rc:$RB),
                           "fctiwu", "$RST, $RB", IIC_FPGeneral,
                           []>;
   defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$RST), (ins f8rc:$RB),
                           "fctiwz", "$RST, $RB", IIC_FPGeneral,
-                          [(set f64:$RST, (PPCany_fctiwz f64:$RB))]>;
+                          [(set f64:$RST, (PPCany_fp_to_i32 f64:$RB))]>;
 
   defm FRSP   : XForm_26r<63, 12, (outs f4rc:$RST), (ins f8rc:$RB),
                           "frsp", "$RST, $RB", IIC_FPGeneral,
                           [(set f32:$RST, (any_fpround f64:$RB))]>;
 
   defm FSQRT  : XForm_26r<63, 22, (outs f8rc:$RST), (ins f8rc:$RB),
                           "fsqrt", "$RST, $RB", IIC_FPSqrtD,
                           [(set f64:$RST, (any_fsqrt f64:$RB))]>;

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 
   // Conversion Instructions
   def XSCVDPSP : XX2Form<60, 265,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xscvdpsp $XT, $XB", IIC_VecFP, []>;
   def XSCVDPSXDS : XX2Form<60, 344,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xscvdpsxds $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (PPCany_fctidz f64:$XB))]>;
+                      [(set f64:$XT, (PPCany_fp_to_i64 f64:$XB))]>;
   let isCodeGenOnly = 1 in
   def XSCVDPSXDSs : XX2Form<60, 344,
                       (outs vssrc:$XT), (ins vssrc:$XB),
                       "xscvdpsxds $XT, $XB", IIC_VecFP,
-                      [(set f32:$XT, (PPCany_fctidz f32:$XB))]>;
+                      [(set f32:$XT, (PPCany_fp_to_i64 f32:$XB))]>;
   def XSCVDPSXWS : XX2Form<60, 88,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xscvdpsxws $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (PPCany_fctiwz f64:$XB))]>;
+                      [(set f64:$XT, (PPCany_fp_to_i32 f64:$XB))]>;
   let isCodeGenOnly = 1 in
   def XSCVDPSXWSs : XX2Form<60, 88,
                       (outs vssrc:$XT), (ins vssrc:$XB),
                       "xscvdpsxws $XT, $XB", IIC_VecFP,
-                      [(set f32:$XT, (PPCany_fctiwz f32:$XB))]>;
+                      [(set f32:$XT, (PPCany_fp_to_i32 f32:$XB))]>;
   def XSCVDPUXDS : XX2Form<60, 328,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xscvdpuxds $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (PPCany_fctiduz f64:$XB))]>;
+                      [(set f64:$XT, (PPCany_fp_to_u64 f64:$XB))]>;
   let isCodeGenOnly = 1 in
   def XSCVDPUXDSs : XX2Form<60, 328,
                       (outs vssrc:$XT), (ins vssrc:$XB),
                       "xscvdpuxds $XT, $XB", IIC_VecFP,
-                      [(set f32:$XT, (PPCany_fctiduz f32:$XB))]>;
+                      [(set f32:$XT, (PPCany_fp_to_u64 f32:$XB))]>;
   def XSCVDPUXWS : XX2Form<60, 72,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xscvdpuxws $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (PPCany_fctiwuz f64:$XB))]>;
+                      [(set f64:$XT, (PPCany_fp_to_u32 f64:$XB))]>;
   let isCodeGenOnly = 1 in
   def XSCVDPUXWSs : XX2Form<60, 72,
                       (outs vssrc:$XT), (ins vssrc:$XB),
                       "xscvdpuxws $XT, $XB", IIC_VecFP,
-                      [(set f32:$XT, (PPCany_fctiwuz f32:$XB))]>;
+                      [(set f32:$XT, (PPCany_fp_to_u32 f32:$XB))]>;
   def XSCVSPDP : XX2Form<60, 329,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xscvspdp $XT, $XB", IIC_VecFP, []>;
   def XSCVSXDDP : XX2Form<60, 376,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xscvsxddp $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (PPCany_fcfid f64:$XB))]>;
+                      [(set f64:$XT, (PPCany_sint_to_fp f64:$XB))]>;
   def XSCVUXDDP : XX2Form<60, 360,
                       (outs vsfrc:$XT), (ins vsfrc:$XB),
                       "xscvuxddp $XT, $XB", IIC_VecFP,
-                      [(set f64:$XT, (PPCany_fcfidu f64:$XB))]>;
+                      [(set f64:$XT, (PPCany_uint_to_fp f64:$XB))]>;
 
   def XVCVDPSP : XX2Form<60, 393,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvdpsp $XT, $XB", IIC_VecFP,
                       [(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>;
   def XVCVDPSXDS : XX2Form<60, 472,
                       (outs vsrc:$XT), (ins vsrc:$XB),
                       "xvcvdpsxds $XT, $XB", IIC_VecFP,

                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   // Single Precision Conversions (FP <-> INT)
   def XSCVSXDSP : XX2Form<60, 312,
                       (outs vssrc:$XT), (ins vsfrc:$XB),
                       "xscvsxdsp $XT, $XB", IIC_VecFP,
-                      [(set f32:$XT, (PPCany_fcfids f64:$XB))]>;
+                      [(set f32:$XT, (PPCany_sint_to_fp f64:$XB))]>;
   def XSCVUXDSP : XX2Form<60, 296,
                       (outs vssrc:$XT), (ins vsfrc:$XB),
                       "xscvuxdsp $XT, $XB", IIC_VecFP,
-                      [(set f32:$XT, (PPCany_fcfidus f64:$XB))]>;
+                      [(set f32:$XT, (PPCany_uint_to_fp f64:$XB))]>;
   } // mayRaiseFPException
 
   // Conversions between vector and scalar single precision
   def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB),
                           "xscvdpspn $XT, $XB", IIC_VecFP, []>;
   def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),
                           "xscvspdpn $XT, $XB", IIC_VecFP, []>;
 

                                           [(set f64:$RST,
                                           (int_ppc_truncf128_round_to_odd
                                           f128:$RB))]>;
   }
 
   // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
   let mayRaiseFPException = 1 in {
     def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz",
-        [(set f128:$RST, (PPCany_fctidz f128:$RB))]>;
+        [(set f128:$RST, (PPCany_fp_to_i64 f128:$RB))]>;
     def XSCVQPSWZ : X_VT5_XO5_VB5<63,  9, 836, "xscvqpswz",
-        [(set f128:$RST, (PPCany_fctiwz f128:$RB))]>;
+        [(set f128:$RST, (PPCany_fp_to_i32 f128:$RB))]>;
     def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz",
-        [(set f128:$RST, (PPCany_fctiduz f128:$RB))]>;
+        [(set f128:$RST, (PPCany_fp_to_u64 f128:$RB))]>;
     def XSCVQPUWZ : X_VT5_XO5_VB5<63,  1, 836, "xscvqpuwz",
-        [(set f128:$RST, (PPCany_fctiwuz f128:$RB))]>;
+        [(set f128:$RST, (PPCany_fp_to_u32 f128:$RB))]>;
   }
 
   // Convert (Un)Signed DWord -> QP.
   def XSCVSDQP  : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;
   def XSCVUDQP  : X_VT5_XO5_VB5_TyVB<63,  2, 836, "xscvudqp", vfrc, []>;
 
   // (Round &) Convert DP <-> HP
   // Note! xscvdphp's src and dest register both use the left 64 bits, so we use

   dag ZELi16i64 = (i64 (zextloadi16 ForceXForm:$src));
   dag SELi16 =    (i32 (sextloadi16 ForceXForm:$src));
   dag SELi16i64 = (i64 (sextloadi16 ForceXForm:$src));
 
   dag Li32 = (i32 (load ForceXForm:$src));
 }
 
 def DWToSPExtractConv {
-  dag El0US1 = (f32 (PPCfcfidus
+  dag El0US1 = (f32 (PPCuint_to_fp
                     (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0))))));
-  dag El1US1 = (f32 (PPCfcfidus
+  dag El1US1 = (f32 (PPCuint_to_fp
                     (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1))))));
-  dag El0US2 = (f32 (PPCfcfidus
+  dag El0US2 = (f32 (PPCuint_to_fp
                     (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0))))));
-  dag El1US2 = (f32 (PPCfcfidus
+  dag El1US2 = (f32 (PPCuint_to_fp
                     (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1))))));
-  dag El0SS1 = (f32 (PPCfcfids
+  dag El0SS1 = (f32 (PPCsint_to_fp
                     (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0))))));
-  dag El1SS1 = (f32 (PPCfcfids
+  dag El1SS1 = (f32 (PPCsint_to_fp
                     (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1))))));
-  dag El0SS2 = (f32 (PPCfcfids
+  dag El0SS2 = (f32 (PPCsint_to_fp
                     (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0))))));
-  dag El1SS2 = (f32 (PPCfcfids
+  dag El1SS2 = (f32 (PPCsint_to_fp
                     (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1))))));
   dag BVU = (v4f32 (build_vector El0US1, El1US1, El0US2, El1US2));
   dag BVS = (v4f32 (build_vector El0SS1, El1SS1, El0SS2, El1SS2));
 }
 
 def WToDPExtractConv {
-  dag El0S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 0))));
-  dag El1S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 1))));
-  dag El2S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 2))));
-  dag El3S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 3))));
-  dag El0U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 0))));
-  dag El1U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 1))));
-  dag El2U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 2))));
-  dag El3U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 3))));
+  dag El0S = (f64 (PPCsint_to_fp (PPCmtvsra (extractelt v4i32:$A, 0))));
+  dag El1S = (f64 (PPCsint_to_fp (PPCmtvsra (extractelt v4i32:$A, 1))));
+  dag El2S = (f64 (PPCsint_to_fp (PPCmtvsra (extractelt v4i32:$A, 2))));
+  dag El3S = (f64 (PPCsint_to_fp (PPCmtvsra (extractelt v4i32:$A, 3))));
+  dag El0U = (f64 (PPCuint_to_fp (PPCmtvsrz (extractelt v4i32:$A, 0))));
+  dag El1U = (f64 (PPCuint_to_fp (PPCmtvsrz (extractelt v4i32:$A, 1))));
+  dag El2U = (f64 (PPCuint_to_fp (PPCmtvsrz (extractelt v4i32:$A, 2))));
+  dag El3U = (f64 (PPCuint_to_fp (PPCmtvsrz (extractelt v4i32:$A, 3))));
   dag BV02S = (v2f64 (build_vector El0S, El2S));
   dag BV13S = (v2f64 (build_vector El1S, El3S));
   dag BV02U = (v2f64 (build_vector El0U, El2U));
   dag BV13U = (v2f64 (build_vector El1U, El3U));
 }
 
 /*  Direct moves of various widths from GPR's into VSR's. Each move lines
     the value up into element 0 (both BE and LE). Namely, entities smaller than

 def DblToFlt {
   dag A0 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 0))));
   dag A1 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 1))));
   dag B0 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 0))));
   dag B1 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 1))));
 }
 
 def ExtDbl {
-  dag A0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 0))))));
-  dag A1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 1))))));
-  dag B0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 0))))));
-  dag B1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 1))))));
-  dag A0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 0))))));
-  dag A1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 1))))));
-  dag B0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 0))))));
-  dag B1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 1))))));
+  dag A0S = (i32 (PPCmfvsr (f64 (PPCfp_to_i32 (f64 (extractelt v2f64:$A, 0))))));
+  dag A1S = (i32 (PPCmfvsr (f64 (PPCfp_to_i32 (f64 (extractelt v2f64:$A, 1))))));
+  dag B0S = (i32 (PPCmfvsr (f64 (PPCfp_to_i32 (f64 (extractelt v2f64:$B, 0))))));
+  dag B1S = (i32 (PPCmfvsr (f64 (PPCfp_to_i32 (f64 (extractelt v2f64:$B, 1))))));
+  dag A0U = (i32 (PPCmfvsr (f64 (PPCfp_to_u32 (f64 (extractelt v2f64:$A, 0))))));
+  dag A1U = (i32 (PPCmfvsr (f64 (PPCfp_to_u32 (f64 (extractelt v2f64:$A, 1))))));
+  dag B0U = (i32 (PPCmfvsr (f64 (PPCfp_to_u32 (f64 (extractelt v2f64:$B, 0))))));
+  dag B1U = (i32 (PPCmfvsr (f64 (PPCfp_to_u32 (f64 (extractelt v2f64:$B, 1))))));
 }
 
 def ByteToWord {
   dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 0)), i8));
   dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 4)), i8));
   dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 8)), i8));
   dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 12)), i8));
   dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 3)), i8));

 def WordToDWord {
   dag LE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 0))));
   dag LE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 2))));
   dag BE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 1))));
   dag BE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 3))));
 }
 
 def FltToIntLoad {
-  dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (extloadf32 ForceXForm:$A)))));
+  dag A = (i32 (PPCmfvsr (PPCfp_to_i32 (f64 (extloadf32 ForceXForm:$A)))));
 }
 def FltToUIntLoad {
-  dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (extloadf32 ForceXForm:$A)))));
+  dag A = (i32 (PPCmfvsr (PPCfp_to_u32 (f64 (extloadf32 ForceXForm:$A)))));
 }
 def FltToLongLoad {
-  dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 ForceXForm:$A)))));
+  dag A = (i64 (PPCmfvsr (PPCfp_to_i64 (f64 (extloadf32 ForceXForm:$A)))));
 }
 def FltToLongLoadP9 {
-  dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 DSForm:$A)))));
+  dag A = (i64 (PPCmfvsr (PPCfp_to_i64 (f64 (extloadf32 DSForm:$A)))));
 }
 def FltToULongLoad {
-  dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 ForceXForm:$A)))));
+  dag A = (i64 (PPCmfvsr (PPCfp_to_u64 (f64 (extloadf32 ForceXForm:$A)))));
 }
 def FltToULongLoadP9 {
-  dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 DSForm:$A)))));
+  dag A = (i64 (PPCmfvsr (PPCfp_to_u64 (f64 (extloadf32 DSForm:$A)))));
 }
 def FltToLong {
-  dag A = (i64 (PPCmfvsr (f64 (PPCfctidz (fpextend f32:$A)))));
+  dag A = (i64 (PPCmfvsr (f64 (PPCfp_to_i64 (fpextend f32:$A)))));
 }
 def FltToULong {
-  dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz (fpextend f32:$A)))));
+  dag A = (i64 (PPCmfvsr (f64 (PPCfp_to_u64 (fpextend f32:$A)))));
 }
 def DblToInt {
-  dag A = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$A))));
-  dag B = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$B))));
-  dag C = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$C))));
-  dag D = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$D))));
+  dag A = (i32 (PPCmfvsr (f64 (PPCfp_to_i32 f64:$A))));
+  dag B = (i32 (PPCmfvsr (f64 (PPCfp_to_i32 f64:$B))));
+  dag C = (i32 (PPCmfvsr (f64 (PPCfp_to_i32 f64:$C))));
+  dag D = (i32 (PPCmfvsr (f64 (PPCfp_to_i32 f64:$D))));
 }
 def DblToUInt {
-  dag A = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$A))));
-  dag B = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$B))));
-  dag C = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$C))));
-  dag D = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$D))));
+  dag A = (i32 (PPCmfvsr (f64 (PPCfp_to_u32 f64:$A))));
+  dag B = (i32 (PPCmfvsr (f64 (PPCfp_to_u32 f64:$B))));
+  dag C = (i32 (PPCmfvsr (f64 (PPCfp_to_u32 f64:$C))));
+  dag D = (i32 (PPCmfvsr (f64 (PPCfp_to_u32 f64:$D))));
 }
 def DblToLong {
-  dag A = (i64 (PPCmfvsr (f64 (PPCfctidz f64:$A))));
+  dag A = (i64 (PPCmfvsr (f64 (PPCfp_to_i64 f64:$A))));
 }
 def DblToULong {
-  dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz f64:$A))));
+  dag A = (i64 (PPCmfvsr (f64 (PPCfp_to_u64 f64:$A))));
 }
 def DblToIntLoad {
-  dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load ForceXForm:$A)))));
+  dag A = (i32 (PPCmfvsr (PPCfp_to_i32 (f64 (load ForceXForm:$A)))));
 }
 def DblToIntLoadP9 {
-  dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load DSForm:$A)))));
+  dag A = (i32 (PPCmfvsr (PPCfp_to_i32 (f64 (load DSForm:$A)))));
 }
 def DblToUIntLoad {
-  dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load ForceXForm:$A)))));
+  dag A = (i32 (PPCmfvsr (PPCfp_to_u32 (f64 (load ForceXForm:$A)))));
 }
 def DblToUIntLoadP9 {
-  dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load DSForm:$A)))));
+  dag A = (i32 (PPCmfvsr (PPCfp_to_u32 (f64 (load DSForm:$A)))));
 }
 def DblToLongLoad {
-  dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (load ForceXForm:$A)))));
+  dag A = (i64 (PPCmfvsr (PPCfp_to_i64 (f64 (load ForceXForm:$A)))));
 }
 def DblToULongLoad {
-  dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (load ForceXForm:$A)))));
+  dag A = (i64 (PPCmfvsr (PPCfp_to_u64 (f64 (load ForceXForm:$A)))));
 }
 
 // FP load dags (for f32 -> v4f32)
 def LoadFP {
   dag A = (f32 (load ForceXForm:$A));
   dag B = (f32 (load ForceXForm:$B));
   dag C = (f32 (load ForceXForm:$C));
   dag D = (f32 (load ForceXForm:$D));

 let Predicates = [HasVSX, IsBigEndian] in {
 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
           (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
 
 def : Pat<(f64 (extractelt v2f64:$S, 0)),
           (f64 (EXTRACT_SUBREG $S, sub_64))>;
 def : Pat<(f64 (extractelt v2f64:$S, 1)),
           (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
-def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
+def : Pat<(f64 (PPCsint_to_fp (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS $S, VSFRC)))>;
-def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
+def : Pat<(f64 (PPCsint_to_fp (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
-def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
+def : Pat<(f64 (PPCuint_to_fp (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
           (f64 (XSCVUXDDP (COPY_TO_REGCLASS $S, VSFRC)))>;
-def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
+def : Pat<(f64 (PPCuint_to_fp (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
           (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
 
 def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),
           (f64 VectorExtractions.BE_VARIABLE_DOUBLE)>;
 
 def : Pat<(v2f64 (build_vector f64:$A, f64:$B)),
           (v2f64 (XXPERMDI
                     (SUBREG_TO_REG (i64 1), $A, sub_64),

 def : Pat<(v2f64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
 def : Pat<(PPCst_vec_be v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
 def : Pat<(v4f32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
 def : Pat<(PPCst_vec_be v4f32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>;
 def : Pat<(v2i64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
 def : Pat<(PPCst_vec_be v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
 def : Pat<(v4i32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
 def : Pat<(PPCst_vec_be v4i32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>;
-def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
+def : Pat<(f64 (PPCsint_to_fp (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
-def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
+def : Pat<(f64 (PPCsint_to_fp (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
-def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
+def : Pat<(f64 (PPCuint_to_fp (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
           (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
-def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
+def : Pat<(f64 (PPCuint_to_fp (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
           (f64 (XSCVUXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
 
 def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)),
           (f64 VectorExtractions.LE_VARIABLE_DOUBLE)>;
 
 // Little endian, available on all targets with VSX
 def : Pat<(v2f64 (build_vector f64:$A, f64:$B)),
           (v2f64 (XXPERMDI

           (f32 (XSCVSPDPN $S))>;
 def : Pat<(f32 (vector_extract v4f32:$S, 1)),
           (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;
 def : Pat<(f32 (vector_extract v4f32:$S, 2)),
           (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;
 def : Pat<(f32 (vector_extract v4f32:$S, 3)),
           (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>;
 
-def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
+def : Pat<(f32 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
           (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>;
-def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
+def : Pat<(f32 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
           (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>;
-def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
+def : Pat<(f32 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
           (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>;
-def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
+def : Pat<(f32 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
           (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>;
-def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
+def : Pat<(f64 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
           (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>;
-def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
+def : Pat<(f64 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
           (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>;
-def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
+def : Pat<(f64 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
           (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>;
-def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
+def : Pat<(f64 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
           (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>;
 
 def : Pat<(f32 (vector_extract v4f32:$S, i32:$Idx)),
           (f32 VectorExtractions.BE_32B_VARIABLE_FLOAT)>;
 
 def : Pat<(f64 (vector_extract v2f64:$S, i32:$Idx)),
           (f64 VectorExtractions.BE_32B_VARIABLE_DOUBLE)>;
 

           (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;
 def : Pat<(f32 (vector_extract v4f32:$S, 2)),
           (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;
 def : Pat<(f32 (vector_extract v4f32:$S, 3)),
           (f32 (XSCVSPDPN $S))>;
 def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)),
           (f32 VectorExtractions.LE_VARIABLE_FLOAT)>;
 
-def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
+def : Pat<(f32 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
           (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>;
-def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
+def : Pat<(f32 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
           (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>;
-def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
+def : Pat<(f32 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
           (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>;
-def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
+def : Pat<(f32 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
           (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>;
-def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
+def : Pat<(f64 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))),
           (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>;
-def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
+def : Pat<(f64 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))),
           (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>;
-def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
+def : Pat<(f64 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))),
           (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>;
-def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
+def : Pat<(f64 (PPCsint_to_fp (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
           (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>;
 
 // LIWAX - This instruction is used for sign extending i32 -> i64.
 // LIWZX - This instruction will be emitted for i32, f32, and when
 //         zero-extending i32 to i64 (zext i32 -> i64).
 defm : ScalToVecWPermute<
   v2i64, (i64 (sextloadi32 ForceXForm:$src)),
   (XXPERMDIs (LIWAX ForceXForm:$src), 2),

   (VSPLTBs 7, (LXSIBZX ForceXForm:$src)),
   (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
 // Build vectors from i16 loads
 defm : ScalToVecWPermute<
   v8i16, ScalarLoads.Li16,
   (VSPLTHs 3, (LXSIHZX ForceXForm:$src)),
   (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;
 
-def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
+def : Pat<(f32 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>;
-def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
+def : Pat<(f32 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>;
-def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
+def : Pat<(f32 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>;
-def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
+def : Pat<(f32 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>;
-def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
+def : Pat<(f64 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
           (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>;
-def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
+def : Pat<(f64 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
           (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>;
-def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
+def : Pat<(f64 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
           (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>;
-def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
+def : Pat<(f64 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
           (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>;
 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
 def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)),
           (v4i32 (XXINSERTW v4i32:$A,
                             (SUBREG_TO_REG (i64 1),
                                            (XSCVDPSXWS f64:$B), sub_64),
                             0))>;

           (f128 (XSCVSDQP (EXTRACT_SUBREG
                             (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
                             sub_64)))>;
   // The SDAG adds the `and` since an `i16` is being extracted as an `i32`.
   def : Pat<(f128 (uint_to_fp
                     (and (i32 (vector_extract v8i16:$src, Idx)), 65535))),
             (f128 (XSCVUDQP (EXTRACT_SUBREG
                               (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
-  def : Pat<(f32 (PPCfcfidus
+  def : Pat<(f32 (PPCuint_to_fp
                    (f64 (PPCmtvsrz (and (i32 (vector_extract v8i16:$src, Idx)),
                                         65535))))),
             (f32 (XSCVUXDSP (EXTRACT_SUBREG
                               (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
-  def : Pat<(f32 (PPCfcfids
+  def : Pat<(f32 (PPCsint_to_fp
                    (f64 (PPCmtvsra
                           (i32 (sext_inreg (vector_extract v8i16:$src, Idx),
                                i16)))))),
           (f32 (XSCVSXDSP (EXTRACT_SUBREG
                             (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
                             sub_64)))>;
-  def : Pat<(f64 (PPCfcfidu
+  def : Pat<(f64 (PPCuint_to_fp
                    (f64 (PPCmtvsrz
                           (and (i32 (vector_extract v8i16:$src, Idx)),
                                65535))))),
             (f64 (XSCVUXDDP (EXTRACT_SUBREG
                               (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
-  def : Pat<(f64 (PPCfcfid
+  def : Pat<(f64 (PPCsint_to_fp
                    (f64 (PPCmtvsra
                           (i32 (sext_inreg (vector_extract v8i16:$src, Idx),
                                i16)))))),
           (f64 (XSCVSXDDP (EXTRACT_SUBREG
                             (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
                             sub_64)))>;
 }
 
 // (Un)Signed Byte vector extract -> QP
 foreach Idx = 0-15 in {
   def : Pat<(f128 (sint_to_fp
                     (i32 (sext_inreg (vector_extract v16i8:$src, Idx),
                                      i8)))),
             (f128 (XSCVSDQP (EXTRACT_SUBREG
                               (VEXTSB2D (VEXTRACTUB Idx, $src)), sub_64)))>;
   def : Pat<(f128 (uint_to_fp
                     (and (i32 (vector_extract v16i8:$src, Idx)), 255))),
             (f128 (XSCVUDQP
                     (EXTRACT_SUBREG (VEXTRACTUB Idx, $src), sub_64)))>;
 
-  def : Pat<(f32 (PPCfcfidus
+  def : Pat<(f32 (PPCuint_to_fp
                    (f64 (PPCmtvsrz
                           (and (i32 (vector_extract v16i8:$src, Idx)),
                                255))))),
             (f32 (XSCVUXDSP (EXTRACT_SUBREG
                               (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>;
-  def : Pat<(f32 (PPCfcfids
+  def : Pat<(f32 (PPCsint_to_fp
                    (f64 (PPCmtvsra
                           (i32 (sext_inreg (vector_extract v16i8:$src, Idx),
                                i8)))))),
           (f32 (XSCVSXDSP (EXTRACT_SUBREG
                             (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)),
                             sub_64)))>;
-  def : Pat<(f64 (PPCfcfidu
+  def : Pat<(f64 (PPCuint_to_fp
                    (f64 (PPCmtvsrz
                           (and (i32 (vector_extract v16i8:$src, Idx)),
                           255))))),
             (f64 (XSCVUXDDP (EXTRACT_SUBREG
                               (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>;
-  def : Pat<(f64 (PPCfcfid
+  def : Pat<(f64 (PPCsint_to_fp
                    (f64 (PPCmtvsra
                           (i32 (sext_inreg (vector_extract v16i8:$src, Idx),
                                i8)))))),
           (f64 (XSCVSXDDP (EXTRACT_SUBREG
                             (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)),
                             sub_64)))>;
 }
 
 // Unsiged int in vsx register -> QP
 def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),
           (f128 (XSCVUDQP
                   (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>;
 } // HasVSX, HasP9Vector, IsBigEndian, IsPPC64
 
 // Little endian Power9 subtarget.
 let Predicates = [HasVSX, HasP9Vector, IsLittleEndian] in {
-def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
+def : Pat<(f32 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>;
-def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
+def : Pat<(f32 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>;
-def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
+def : Pat<(f32 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>;
-def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
+def : Pat<(f32 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>;
-def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
+def : Pat<(f64 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
           (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>;
-def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
+def : Pat<(f64 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
           (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>;
-def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
+def : Pat<(f64 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
           (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>;
-def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
+def : Pat<(f64 (PPCuint_to_fp (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))),
           (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>;
 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;
 def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)),
           (v4i32 (XXINSERTW v4i32:$A,
                             (SUBREG_TO_REG (i64 1),
                                            (XSCVDPSXWS f64:$B), sub_64),
                             12))>;

                     (EXTRACT_SUBREG (VEXTSH2D
                                       (VEXTRACTUH !head(!tail(Idx)), $src)),
                                     sub_64)))>;
   def : Pat<(f128 (uint_to_fp
                     (and (i32 (vector_extract v8i16:$src, !head(Idx))),
                          65535))),
             (f128 (XSCVUDQP (EXTRACT_SUBREG
                               (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
-  def : Pat<(f32 (PPCfcfidus
+  def : Pat<(f32 (PPCuint_to_fp
                    (f64 (PPCmtvsrz
                           (and (i32 (vector_extract v8i16:$src, !head(Idx))),
                           65535))))),
             (f32 (XSCVUXDSP (EXTRACT_SUBREG
                               (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
-  def : Pat<(f32 (PPCfcfids
+  def : Pat<(f32 (PPCsint_to_fp
                    (f64 (PPCmtvsra
                           (i32 (sext_inreg (vector_extract v8i16:$src,
                                            !head(Idx)), i16)))))),
             (f32 (XSCVSXDSP
                     (EXTRACT_SUBREG
                      (VEXTSH2D (VEXTRACTUH !head(!tail(Idx)), $src)),
                      sub_64)))>;
-  def : Pat<(f64 (PPCfcfidu
+  def : Pat<(f64 (PPCuint_to_fp
                    (f64 (PPCmtvsrz
                           (and (i32 (vector_extract v8i16:$src, !head(Idx))),
                           65535))))),
             (f64 (XSCVUXDDP (EXTRACT_SUBREG
                               (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
-  def : Pat<(f64 (PPCfcfid
+  def : Pat<(f64 (PPCsint_to_fp
                    (f64 (PPCmtvsra
                         (i32 (sext_inreg
                             (vector_extract v8i16:$src, !head(Idx)), i16)))))),
             (f64 (XSCVSXDDP
                     (EXTRACT_SUBREG (VEXTSH2D
                                       (VEXTRACTUH !head(!tail(Idx)), $src)),
                                     sub_64)))>;
 }

                       sub_64)))>;
   def : Pat<(f128 (uint_to_fp
                     (and (i32 (vector_extract v16i8:$src, !head(Idx))),
                          255))),
             (f128 (XSCVUDQP
                     (EXTRACT_SUBREG
                       (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
 
-  def : Pat<(f32 (PPCfcfidus
+  def : Pat<(f32 (PPCuint_to_fp
                    (f64 (PPCmtvsrz
                           (and (i32 (vector_extract v16i8:$src, !head(Idx))),
                           255))))),
             (f32 (XSCVUXDSP (EXTRACT_SUBREG
                               (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
-  def : Pat<(f32 (PPCfcfids
+  def : Pat<(f32 (PPCsint_to_fp
                    (f64 (PPCmtvsra
                           (i32 (sext_inreg
                             (vector_extract v16i8:$src, !head(Idx)), i8)))))),
             (f32 (XSCVSXDSP
                     (EXTRACT_SUBREG (VEXTSH2D
                                       (VEXTRACTUB !head(!tail(Idx)), $src)),
                                     sub_64)))>;
-  def : Pat<(f64 (PPCfcfidu
+  def : Pat<(f64 (PPCuint_to_fp
                    (f64 (PPCmtvsrz
                           (and (i32
                             (vector_extract v16i8:$src, !head(Idx))), 255))))),
             (f64 (XSCVUXDDP (EXTRACT_SUBREG
                               (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
-  def : Pat<(f64 (PPCfcfidu
+  def : Pat<(f64 (PPCuint_to_fp
                    (f64 (PPCmtvsra
                         (i32 (sext_inreg
                             (vector_extract v16i8:$src, !head(Idx)), i8)))))),
             (f64 (XSCVSXDDP
                     (EXTRACT_SUBREG (VEXTSH2D
                                       (VEXTRACTUB !head(!tail(Idx)), $src)),
                                     sub_64)))>;
 
-  def : Pat<(f64 (PPCfcfid
+  def : Pat<(f64 (PPCsint_to_fp
                    (f64 (PPCmtvsra
                         (i32 (sext_inreg
                           (vector_extract v16i8:$src, !head(Idx)), i8)))))),
             (f64 (XSCVSXDDP
                     (EXTRACT_SUBREG (VEXTSH2D
                                       (VEXTRACTUH !head(!tail(Idx)), $src)),
                                     sub_64)))>;
 }