[AMDGPU] Don't S_MOV_B32 into $scc

[rovka]

Summary

The peephole optimizer tries to replace

%n:sgpr_32 = S_MOV_B32 x
$scc = COPY %n

with a S_MOV_B32 directly into $scc.

This crashes because S_MOV_B32 cannot take $scc as input.

We currently generate code like this from GlobalISel when lowering a
G_BRCOND with a constant condition. We should probably look into
removing this kind of branch altogether, but until then we should at
least not crash.

This patch fixes the issue by making sure we don't apply the peephole
optimization when trying to S_MOV_B32 into a physical register that
doesn't have the SReg_32 register class.

[arsenm]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

3093–3094

Can check if the virtual register's class doesn't contain the physical register, don't need to hardcode the opcode/ class

[rovka]

Addressed the comment. Thanks for the quick review!

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

if (Is16Bit) {
       UseMI.getOperand(0).setSubReg(0);
       if (DstReg.isPhysical()) {
         DstReg = RI.get32BitRegister(DstReg);
         UseMI.getOperand(0).setReg(DstReg);
       }
       assert(UseMI.getOperand(1).getReg().isVirtual());
     }
 
-    UseMI.setDesc(get(NewOpc));
+    const MCInstrDesc &NewMCID = get(NewOpc);
+    if (DstReg.isPhysical() &&
+        !RI.getRegClass(NewMCID.operands()[0].RegClass)->contains(DstReg))
+      return false;
+
+    UseMI.setDesc(NewMCID);
     UseMI.getOperand(1).ChangeToImmediate(Imm.getSExtValue());
     UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
     return true;
   }
 
   if (Opc == AMDGPU::V_MAD_F32_e64 || Opc == AMDGPU::V_MAC_F32_e64 ||
       Opc == AMDGPU::V_MAD_F16_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
       Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64 ||

llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass peephole-opt -o - %s | FileCheck -check-prefix=GCN %s
 
 ---
+name:            fold_simm_virtual
+body:             |
+  bb.0:
+
+    ; GCN-LABEL: name: fold_simm_virtual
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GCN-NEXT: SI_RETURN_TO_EPILOG
+    %0:sreg_32 = S_MOV_B32 0
+    %1:sreg_32 = COPY killed %0
+    SI_RETURN_TO_EPILOG
+
+...
+
+---
+name:            fold_simm_physical
+body:             |
+  bb.0:
+
+    ; GCN-LABEL: name: fold_simm_physical
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GCN-NEXT: $sgpr1 = S_MOV_B32 0
+    ; GCN-NEXT: SI_RETURN_TO_EPILOG
+    %0:sreg_32 = S_MOV_B32 0
+    $sgpr1 = COPY killed %0
+    SI_RETURN_TO_EPILOG
+
+...
+
+---
+name:            dont_fold_simm_scc
+body:             |
+  bb.0:
+
+    ; GCN-LABEL: name: dont_fold_simm_scc
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GCN-NEXT: $scc = COPY killed [[S_MOV_B32_]]
+    ; GCN-NEXT: SI_RETURN_TO_EPILOG
+    %0:sreg_32 = S_MOV_B32 0
+    $scc = COPY killed %0
+    SI_RETURN_TO_EPILOG
+
+...
+
+---
 name:            fold_simm_16_sub_to_lo
 body:             |
   bb.0:
 
     ; GCN-LABEL: name: fold_simm_16_sub_to_lo
     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
     ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_lo16 = COPY killed [[S_MOV_B32_]].lo16
     ; GCN-NEXT: SI_RETURN_TO_EPILOG [[COPY]]