[flang][openacc] Add missing piece to translate to LLVM IR dialect

[clementval]

Summary

Add missing pieces to translate handle OpenACC dialect in the translation.

Depends on D147825

[razvanlupusoru]

Looks good. I just have a few concerns about the UnrealizedConversionCastOp handling.

flang/lib/Optimizer/CodeGen/CodeGen.cpp

3654

Should you assert there is a single output?

3660–3666

This should possibly not be commented out.

[PeteSteinfeld]

I'm seeing errors when I try to build with this patch that are similar to the ones I saw when reviewing D147825.

[clementval]

Rebase

[clementval]

address review comments

[PeteSteinfeld]

All builds and tests correctly and looks good.

flang/lib/Optimizer/CodeGen/CMakeLists.txt

add_flang_library(FIRCodeGen
   FIRDialect
   FIRDialectSupport
   FIRSupport
   MLIRComplexToLLVM
   MLIRComplexToStandard
   MLIRMathToFuncs
   MLIRMathToLLVM
   MLIRMathToLibm
+  MLIROpenACCToLLVM
   MLIROpenMPToLLVM
   MLIRBuiltinToLLVMIRTranslation
   MLIRLLVMToLLVMIRTranslation
   MLIRTargetLLVMIRExport
 
   LINK_COMPONENTS
   AsmParser
   AsmPrinter
   Remarks
   TargetParser
 )

flang/lib/Optimizer/CodeGen/CodeGen.cpp

 #include "mlir/Conversion/ComplexToLLVM/ComplexToLLVM.h"
 #include "mlir/Conversion/ComplexToStandard/ComplexToStandard.h"
 #include "mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h"
 #include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h"
 #include "mlir/Conversion/LLVMCommon/Pattern.h"
 #include "mlir/Conversion/MathToFuncs/MathToFuncs.h"
 #include "mlir/Conversion/MathToLLVM/MathToLLVM.h"
 #include "mlir/Conversion/MathToLibm/MathToLibm.h"
+#include "mlir/Conversion/OpenACCToLLVM/ConvertOpenACCToLLVM.h"
 #include "mlir/Conversion/OpenMPToLLVM/ConvertOpenMPToLLVM.h"
+#include "mlir/Conversion/ReconcileUnrealizedCasts/ReconcileUnrealizedCasts.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "mlir/Dialect/OpenACC/OpenACC.h"
 #include "mlir/Dialect/OpenMP/OpenMPDialect.h"
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Matchers.h"
 #include "mlir/Pass/Pass.h"
 #include "mlir/Pass/PassManager.h"
 #include "mlir/Target/LLVMIR/ModuleTranslation.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/TypeSwitch.h"
matchAndRewrite(FromOp op, OpAdaptor adaptor,
                   mlir::ConversionPatternRewriter &rewriter) const final {
     if (!op->getUses().empty())
       return rewriter.notifyMatchFailure(op, "op must be dead");
     rewriter.eraseOp(op);
     return mlir::success();
   }
 };
 
+struct UnrealizedConversionCastOpConversion
+    : public FIROpConversion<mlir::UnrealizedConversionCastOp> {
+  using FIROpConversion::FIROpConversion;
+
+  mlir::LogicalResult
+  matchAndRewrite(mlir::UnrealizedConversionCastOp op, OpAdaptor adaptor,
+                  mlir::ConversionPatternRewriter &rewriter) const override {
+    assert(op.getOutputs().getTypes().size() == 1 && "expect a single type");
+    mlir::Type convertedType = convertType(op.getOutputs().getTypes()[0]);
+    if (convertedType == adaptor.getInputs().getTypes()[0]) {
+      rewriter.replaceOp(op, adaptor.getInputs());
+      return mlir::success();
+    }
+
+    convertedType = adaptor.getInputs().getTypes()[0];
+    if (convertedType == op.getOutputs().getType()[0]) {
+      rewriter.replaceOp(op, adaptor.getInputs());
+      return mlir::success();
+    }
+    return mlir::failure();
+  }
+};
+
 struct ShapeOpConversion : public MustBeDeadConversion<fir::ShapeOp> {
   using MustBeDeadConversion::MustBeDeadConversion;
 };
 
 struct ShapeShiftOpConversion : public MustBeDeadConversion<fir::ShapeShiftOp> {
   using MustBeDeadConversion::MustBeDeadConversion;
 };
 
pattern.insert<
         InsertValueOpConversion, IsPresentOpConversion,
         LenParamIndexOpConversion, LoadOpConversion, MulcOpConversion,
         NegcOpConversion, NoReassocOpConversion, SelectCaseOpConversion,
         SelectOpConversion, SelectRankOpConversion, SelectTypeOpConversion,
         ShapeOpConversion, ShapeShiftOpConversion, ShiftOpConversion,
         SliceOpConversion, StoreOpConversion, StringLitOpConversion,
         SubcOpConversion, TypeDescOpConversion, UnboxCharOpConversion,
         UnboxProcOpConversion, UndefOpConversion, UnreachableOpConversion,
-        XArrayCoorOpConversion, XEmboxOpConversion, XReboxOpConversion,
-        ZeroOpConversion>(typeConverter, options);
+        UnrealizedConversionCastOpConversion, XArrayCoorOpConversion,
+        XEmboxOpConversion, XReboxOpConversion, ZeroOpConversion>(typeConverter,
+                                                                  options);
     mlir::populateFuncToLLVMConversionPatterns(typeConverter, pattern);
+    mlir::populateOpenACCToLLVMConversionPatterns(typeConverter, pattern);
     mlir::populateOpenMPToLLVMConversionPatterns(typeConverter, pattern);
     mlir::arith::populateArithToLLVMConversionPatterns(typeConverter, pattern);
     mlir::cf::populateControlFlowToLLVMConversionPatterns(typeConverter,
                                                           pattern);
     // Math operations that have not been converted yet must be converted
     // to Libm.
     mlir::populateMathToLibmConversionPatterns(pattern);
     mlir::populateComplexToLLVMConversionPatterns(typeConverter, pattern);
     mlir::ConversionTarget target{*context};
     target.addLegalDialect<mlir::LLVM::LLVMDialect>();
     // The OpenMP dialect is legal for Operations without regions, for those
     // which contains regions it is legal if the region contains only the
     // LLVM dialect. Add OpenMP dialect as a legal dialect for conversion and
     // legalize conversion of OpenMP operations without regions.
     mlir::configureOpenMPToLLVMConversionLegality(target, typeConverter);
     target.addLegalDialect<mlir::omp::OpenMPDialect>();
+    target.addLegalDialect<mlir::acc::OpenACCDialect>();
 
     // required NOPs for applying a full conversion
     target.addLegalOp<mlir::ModuleOp>();
 
     // If we're on Windows, we might need to rename some libm calls.
     bool isMSVC = fir::getTargetTriple(mod).isOSMSVCRT();
     if (isMSVC) {
       pattern.insert<RenameMSVCLibmCallees, RenameMSVCLibmFuncs>(context);

flang/lib/Optimizer/Support/CMakeLists.txt

 get_property(dialect_libs GLOBAL PROPERTY MLIR_DIALECT_LIBS)
 
 add_flang_library(FIRSupport
   InitFIR.cpp
   InternalNames.cpp
 
   DEPENDS
   FIROpsIncGen
   HLFIROpsIncGen
   MLIRIR
   ${dialect_libs}
 
   LINK_LIBS
   ${dialect_libs}
   MLIRBuiltinToLLVMIRTranslation
+  MLIROpenACCToLLVMIRTranslation
   MLIROpenMPToLLVMIRTranslation
   MLIRLLVMToLLVMIRTranslation
   MLIRTargetLLVMIRExport
 
   LINK_COMPONENTS
   TargetParser
 )

flang/lib/Optimizer/Support/InitFIR.cpp

 //===-- Optimizer/Support/InitFIR.cpp -------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "flang/Optimizer/Support/InitFIR.h"
 #include "mlir/Target/LLVMIR/Dialect/Builtin/BuiltinToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.h"
+#include "mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h"
 #include "mlir/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.h"
 
 void fir::support::registerLLVMTranslation(mlir::MLIRContext &context) {
   mlir::DialectRegistry registry;
+  // Register OpenACC dialect interface here as well.
+  registerOpenACCDialectTranslation(registry);
   // Register OpenMP dialect interface here as well.
   registerOpenMPDialectTranslation(registry);
   // Register LLVM-IR dialect interface.
   registerLLVMDialectTranslation(registry);
   // Register builtin dialect interface.
   registerBuiltinDialectTranslation(registry);
   context.appendDialectRegistry(registry);
 }

flang/lib/Optimizer/Transforms/OpenACC/OpenACCDataOperandConversion.cpp

void OpenACCDataOperandConversion::runOnOperation() {
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::EnterDataOp>>(converter);
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::ExitDataOp>>(converter);
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::ParallelOp>>(converter);
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::UpdateOp>>(converter);
 
   ConversionTarget target(*context);
   target.addLegalDialect<fir::FIROpsDialect>();
   target.addLegalDialect<LLVM::LLVMDialect>();
-  target.addLegalOp<UnrealizedConversionCastOp>();
+  target.addLegalOp<mlir::UnrealizedConversionCastOp>();
 
   auto allDataOperandsAreConverted = [](ValueRange operands) {
     for (Value operand : operands) {
       if (!operand.getType().isa<LLVM::LLVMPointerType>())
         return false;
     }
     return true;
   };

flang/test/Transforms/OpenACC/convert-data-operands-to-llvmir.fir

 // RUN: fir-opt -fir-openacc-data-operand-conversion='use-opaque-pointers=1' -split-input-file %s | FileCheck %s
+// RUN: fir-opt -fir-openacc-data-operand-conversion='use-opaque-pointers=1' -split-input-file %s | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefix=LLVMIR
+
+fir.global internal @_QFEa : !fir.array<10xf32> {
+  %0 = fir.undefined !fir.array<10xf32>
+  fir.has_value %0 : !fir.array<10xf32>
+}
 
 func.func @_QQsub1() attributes {fir.bindc_name = "arr"} {
   %0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
   acc.data copy(%0 : !fir.ref<!fir.array<10xf32>>) {
     acc.terminator
   }
   return
 }
 
 // CHECK-LABEL: func.func @_QQsub1() attributes {fir.bindc_name = "arr"} {
 // CHECK: %[[ADDR:.*]] = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
 // CHECK: %[[CAST:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
 // CHECK: acc.data copy(%[[CAST]] : !llvm.ptr<array<10 x f32>>)
 
+// LLVMIR-LABEL: llvm.func @_QQsub1() attributes {fir.bindc_name = "arr"} {
+// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
+// LLVMIR: acc.data copy(%[[ADDR]] : !llvm.ptr<array<10 x f32>>) {
+
 // -----
 
+fir.global internal @_QFEa : !fir.array<10xf32> {
+  %0 = fir.undefined !fir.array<10xf32>
+  fir.has_value %0 : !fir.array<10xf32>
+}
+
 func.func @_QQsub_enter_exit() attributes {fir.bindc_name = "a"} {
   %0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
   acc.enter_data copyin(%0 : !fir.ref<!fir.array<10xf32>>)
   acc.exit_data copyout(%0 : !fir.ref<!fir.array<10xf32>>)
   return
 }
 
 // CHECK-LABEL: func.func @_QQsub_enter_exit() attributes {fir.bindc_name = "a"} {
 // CHECK: %[[ADDR:.*]] = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
 // CHECK: %[[CAST0:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
 // CHECK: acc.enter_data copyin(%[[CAST0]] : !llvm.ptr<array<10 x f32>>)
 // CHECK: %[[CAST1:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
 // CHECK: acc.exit_data copyout(%[[CAST1]] : !llvm.ptr<array<10 x f32>>)
 
+// LLVMIR-LABEL: llvm.func @_QQsub_enter_exit() attributes {fir.bindc_name = "a"} {
+// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
+// LLVMIR: acc.enter_data copyin(%[[ADDR]] : !llvm.ptr<array<10 x f32>>)
+// LLVMIR: acc.exit_data copyout(%[[ADDR]] : !llvm.ptr<array<10 x f32>>)
+
 // -----
 
+fir.global internal @_QFEa : !fir.array<10xf32> {
+  %0 = fir.undefined !fir.array<10xf32>
+  fir.has_value %0 : !fir.array<10xf32>
+}
+
 func.func @_QQsub_update() attributes {fir.bindc_name = "a"} {
   %0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
   acc.update device(%0 : !fir.ref<!fir.array<10xf32>>)
   return
 }
 
 // CHECK-LABEL: func.func @_QQsub_update() attributes {fir.bindc_name = "a"} {
 // CHECK: %[[ADDR:.*]] = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
 // CHECK: %[[CAST:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
 // CHECK: acc.update device(%[[CAST]] : !llvm.ptr<array<10 x f32>>)
 
+// LLVMIR-LABEL: llvm.func @_QQsub_update() attributes {fir.bindc_name = "a"} {
+// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
+// LLVMIR: acc.update device(%[[ADDR]] : !llvm.ptr<array<10 x f32>>)
+
 // -----
 
+fir.global internal @_QFEa : !fir.array<10xf32> {
+  %0 = fir.undefined !fir.array<10xf32>
+  fir.has_value %0 : !fir.array<10xf32>
+}
+
 func.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
   %0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
   %1 = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFEi"}
   acc.parallel copyin(%0: !fir.ref<!fir.array<10xf32>>) {
     acc.loop {
       %c1_i32 = arith.constant 1 : i32
       %2 = fir.convert %c1_i32 : (i32) -> index
       %c10_i32 = arith.constant 10 : i32
func.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
   }
   return
 }
 
 // CHECK-LABEL: func.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
 // CHECK: %[[ADDR:.*]] = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
 // CHECK: %[[CAST:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
 // CHECK: acc.parallel copyin(%[[CAST]]: !llvm.ptr<array<10 x f32>>) {
+
+// LLVMIR-LABEL: llvm.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
+// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
+// LLVMIR: acc.parallel copyin(%[[ADDR]]: !llvm.ptr<array<10 x f32>>) {