[RISCV][Tablegen] Make VLXSched and VSXSched classes aware of data and index lmul

[nitinjohnraj]

Summary

The LMUL for data and index are not guaranteed the same so we need different LMULs appended to the sched classes for them.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 ]>;
 
 class VSSSched<int n, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVSTS" #n #"_"#suffix),
   !cast<SchedReadWrite>("ReadVSTS" #n #"V_"#suffix),
   ReadVSTX, ReadVSTSX, ReadVMask
 ]>;
 
-class VLXSched<int n, string o, string suffix = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVLD" #o #"X" #n #"_" # suffix),
+class VLXSched<int n, string o,
+               string dataSuffix = "WorstCase",
+               string idxSuffix = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVLD" #o #"X" #n #"_" # dataSuffix),
   ReadVLDX,
-  !cast<SchedReadWrite>("ReadVLD" #o #"XV_" # suffix), ReadVMask
+  !cast<SchedReadWrite>("ReadVLD" #o #"XV_" # idxSuffix), ReadVMask
 ]>;
 
-class VSXSched<int n, string o, string suffix = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVST" #o #"X" #n #"_"#suffix),
-  !cast<SchedReadWrite>("ReadVST" #o #"X" #n #"_"#suffix),
-  ReadVSTX, !cast<SchedReadWrite>("ReadVST" #o #"XV_"#suffix), ReadVMask
+class VSXSched<int n, string o,
+               string dataSuffix = "WorstCase",
+               string idxSuffix = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVST" #o #"X" #n #"_"#dataSuffix),
+  !cast<SchedReadWrite>("ReadVST" #o #"X" #n #"_"#dataSuffix),
+  ReadVSTX, !cast<SchedReadWrite>("ReadVST" #o #"XV_"#idxSuffix), ReadVMask
 ]>;
 
 class VLFSched<string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLDFF_" # suffix),
   ReadVLDX, ReadVMask
 ]>;
 
 // Unit-Stride Segment Loads and Stores

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 multiclass VPseudoILoad<bit Ordered> {
   foreach eew = EEWList in {
     foreach sew = EEWList in {
       foreach lmul = MxSet<sew>.m in {
         defvar octuple_lmul = lmul.octuple;
         // Calculate emul = eew * lmul / sew
         defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2<sew>.val);
         if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
-          defvar LInfo = lmul.MX;
+          defvar DataLInfo = lmul.MX;
           defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
           defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = lmul.vrclass;
           defvar IdxVreg = idx_lmul.vrclass;
           defvar HasConstraint = !ne(sew, eew);
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = lmul.value in {
-            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo :
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo :
               VPseudoILoadNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
-              VLXSched<eew, Order, LInfo>;
-            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_TU":
+              VLXSched<eew, Order, DataLInfo, IdxLInfo>;
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo # "_TU":
               VPseudoILoadNoMaskTU<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
-              VLXSched<eew, Order, LInfo>;
-            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" :
+              VLXSched<eew, Order, DataLInfo, IdxLInfo>;
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
               VPseudoILoadMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
               RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
-              VLXSched<eew, Order, LInfo>;
+              VLXSched<eew, Order, DataLInfo, IdxLInfo>;
           }
         }
       }
     }
   }
 }
 
 multiclass VPseudoUSStore {

 multiclass VPseudoIStore<bit Ordered> {
   foreach eew = EEWList in {
     foreach sew = EEWList in {
       foreach lmul = MxSet<sew>.m in {
         defvar octuple_lmul = lmul.octuple;
         // Calculate emul = eew * lmul / sew
         defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2<sew>.val);
         if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
-          defvar LInfo = lmul.MX;
+          defvar DataLInfo = lmul.MX;
           defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
           defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = lmul.vrclass;
           defvar IdxVreg = idx_lmul.vrclass;
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = lmul.value in {
-            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo :
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo :
               VPseudoIStoreNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered>,
-              VSXSched<eew, Order, LInfo>;
-            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" :
+              VSXSched<eew, Order, DataLInfo, IdxLInfo>;
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
               VPseudoIStoreMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered>,
-              VSXSched<eew, Order, LInfo>;
+              VSXSched<eew, Order, DataLInfo, IdxLInfo>;
           }
         }
       }
     }
   }
 }
 
 multiclass VPseudoVPOP_M {