[RISCV][Tablegen] Remove LMUL from ReadVLDX, ReadVSTX, ReadVLDSX, ReadVSTSX scheduler classes

[nitinjohnraj]

Summary

This read is for a gpr pointer, and doesn't need to be LMUL aware.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 
 class VMVRSched<int n> : Sched<[
   !cast<SchedReadWrite>("WriteVMov" #n #"V"),
   !cast<SchedReadWrite>("ReadVMov" #n #"V")
 ]>;
 
 class VLESched<string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLDE_"#suffix),
-  !cast<SchedReadWrite>("ReadVLDX_"#suffix), ReadVMask
+  ReadVLDX, ReadVMask
 ]>;
 
 class VSESched<string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVSTE_" # suffix),
   !cast<SchedReadWrite>("ReadVSTEV_" # suffix),
-  !cast<SchedReadWrite>("ReadVSTX_" # suffix), ReadVMask
+  ReadVSTX, ReadVMask
 ]>;
 
 class VLSSched<int n, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLDS" #n #"_" # suffix),
-  !cast<SchedReadWrite>("ReadVLDX_" # suffix),
-  !cast<SchedReadWrite>("ReadVLDSX_" # suffix), ReadVMask
+  ReadVLDX, ReadVLDSX, ReadVMask
 ]>;
 
 class VSSSched<int n, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVSTS" #n #"_"#suffix),
   !cast<SchedReadWrite>("ReadVSTS" #n #"V_"#suffix),
-  !cast<SchedReadWrite>("ReadVSTX_"#suffix),
-  !cast<SchedReadWrite>("ReadVSTSX_"#suffix), ReadVMask
+  ReadVSTX, ReadVSTSX, ReadVMask
 ]>;
 
 class VLXSched<int n, string o, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLD" #o #"X" #n #"_" # suffix),
-  !cast<SchedReadWrite>("ReadVLDX_" # suffix),
+  ReadVLDX,
   !cast<SchedReadWrite>("ReadVLD" #o #"XV_" # suffix), ReadVMask
 ]>;
 
 class VSXSched<int n, string o, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVST" #o #"X" #n #"_"#suffix),
   !cast<SchedReadWrite>("ReadVST" #o #"X" #n #"_"#suffix),
-  !cast<SchedReadWrite>("ReadVSTX_"#suffix),
-  !cast<SchedReadWrite>("ReadVST" #o #"XV_"#suffix), ReadVMask
+  ReadVSTX, !cast<SchedReadWrite>("ReadVST" #o #"XV_"#suffix), ReadVMask
 ]>;
 
 class VLFSched<string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLDFF_" # suffix),
-  !cast<SchedReadWrite>("ReadVLDX_" # suffix), ReadVMask
+  ReadVLDX, ReadVMask
 ]>;
 
 // Unit-Stride Segment Loads and Stores
 class VLSEGSched<int nf, int eew, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLSEG" #nf #"e" #eew #"_"#suffix),
-  !cast<SchedReadWrite>("ReadVLDX_"#suffix), ReadVMask
+  ReadVLDX, ReadVMask
 ]>;
 class VSSEGSched<int nf, int eew, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVSSEG" #nf #"e" #eew #"_"#suffix),
   !cast<SchedReadWrite>("ReadVSTEV_"#suffix),
-  !cast<SchedReadWrite>("ReadVSTX_"#suffix), ReadVMask
+  ReadVSTX, ReadVMask
 ]>;
 class VLSEGFFSched<int nf, int eew, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLSEGFF" #nf #"e" #eew #"_"#suffix),
-  !cast<SchedReadWrite>("ReadVLDX_"#suffix), ReadVMask
+  ReadVLDX, ReadVMask
 ]>;
 // Strided Segment Loads and Stores
 class VLSSEGSched<int nf, int eew, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVLSSEG" #nf #"e" #eew #"_"#suffix),
-  !cast<SchedReadWrite>("ReadVLDX_"#suffix),
-  !cast<SchedReadWrite>("ReadVLDSX_"#suffix), ReadVMask
+  ReadVLDX, ReadVLDSX, ReadVMask
 ]>;
 class VSSSEGSched<int nf, int eew, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVSSSEG" #nf #"e" #eew #"_"#suffix),
   !cast<SchedReadWrite>("ReadVSTS" #eew #"V_"#suffix),
-  !cast<SchedReadWrite>("ReadVSTX_"#suffix),
-  !cast<SchedReadWrite>("ReadVSTSX_"#suffix), ReadVMask
+  ReadVSTX, ReadVSTSX, ReadVMask
 ]>;
 // Indexed Segment Loads and Stores
 class VLXSEGSched<int nf, int eew, string o, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVL" #o #"XSEG" #nf #"e" #eew #"_"#suffix),
-  !cast<SchedReadWrite>("ReadVLDX_"#suffix),
-  !cast<SchedReadWrite>("ReadVLD" #o #"XV" #"_"#suffix), ReadVMask
+  ReadVLDX, !cast<SchedReadWrite>("ReadVLD" #o #"XV" #"_"#suffix), ReadVMask
 ]>;
 class VSXSEGSched<int nf, int eew, string o, string suffix = "WorstCase"> : Sched<[
   !cast<SchedReadWrite>("WriteVS" #o #"XSEG" #nf #"e" #eew #"_"#suffix),
   !cast<SchedReadWrite>("ReadVST" #o #"X" #eew # "_"#suffix),
-  !cast<SchedReadWrite>("ReadVSTX_"#suffix),
-  !cast<SchedReadWrite>("ReadVST" #o #"XV" # "_"#suffix), ReadVMask
+  ReadVSTX, !cast<SchedReadWrite>("ReadVST" #o #"XV" # "_"#suffix), ReadVMask
 ]>;
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 // unit-stride load vd, (rs1), vm

 }
 
 multiclass VWholeLoadN<bits<3> nf, string opcodestr, RegisterClass VRC> {
   foreach l = [8, 16, 32] in {
     defvar w = !cast<RISCVWidth>("LSWidth" # l);
     defvar s = !cast<SchedWrite>("WriteVLD" # !add(nf, 1) # "R");
 
     def E # l # _V : VWholeLoad<nf, w, opcodestr # "e" # l # ".v", VRC>,
-                     Sched<[s, ReadVLDX_WorstCase]>;
+                     Sched<[s, ReadVLDX]>;
   }
 }
 multiclass VWholeLoadEEW64<bits<3> nf, string opcodestr, RegisterClass VRC, SchedReadWrite schedrw> {
   def E64_V : VWholeLoad<nf, LSWidth64, opcodestr # "e64.v", VRC>,
-              Sched<[schedrw, ReadVLDX_WorstCase]>;
+              Sched<[schedrw, ReadVLDX]>;
 }
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasVInstructions] in {
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
foreach eew = [8, 16, 32] in {
   def VSSE#eew#_V  : VStridedStore<w,  "vsse"#eew#".v">, VSSSched<eew>;
 }
 
 defm "" : VIndexLoadStore<[8, 16, 32]>;
 } // Predicates = [HasVInstructions]
 
 let Predicates = [HasVInstructions] in {
 def VLM_V : VUnitStrideLoadMask<"vlm.v">,
-             Sched<[WriteVLDM_WorstCase, ReadVLDX_WorstCase]>;
+             Sched<[WriteVLDM_WorstCase, ReadVLDX]>;
 def VSM_V : VUnitStrideStoreMask<"vsm.v">,
-             Sched<[WriteVSTM_WorstCase, ReadVSTM_WorstCase, ReadVSTX_WorstCase]>;
+             Sched<[WriteVSTM_WorstCase, ReadVSTM_WorstCase, ReadVSTX]>;
 def : InstAlias<"vle1.v $vd, (${rs1})",
                 (VLM_V VR:$vd, GPR:$rs1), 0>;
 def : InstAlias<"vse1.v $vs3, (${rs1})",
                 (VSM_V VR:$vs3, GPR:$rs1), 0>;
 
 defm VL1R : VWholeLoadN<0, "vl1r", VR>;
 defm VL2R : VWholeLoadN<1, "vl2r", VRM2>;
 defm VL4R : VWholeLoadN<3, "vl4r", VRM4>;
 defm VL8R : VWholeLoadN<7, "vl8r", VRM8>;
 
 def VS1R_V : VWholeStore<0, "vs1r.v", VR>,
-             Sched<[WriteVST1R, ReadVST1R, ReadVSTX_WorstCase]>;
+             Sched<[WriteVST1R, ReadVST1R, ReadVSTX]>;
 def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>,
-             Sched<[WriteVST2R, ReadVST2R, ReadVSTX_WorstCase]>;
+             Sched<[WriteVST2R, ReadVST2R, ReadVSTX]>;
 def VS4R_V : VWholeStore<3, "vs4r.v", VRM4>,
-             Sched<[WriteVST4R, ReadVST4R, ReadVSTX_WorstCase]>;
+             Sched<[WriteVST4R, ReadVST4R, ReadVSTX]>;
 def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>,
-             Sched<[WriteVST8R, ReadVST8R, ReadVSTX_WorstCase]>;
+             Sched<[WriteVST8R, ReadVST8R, ReadVSTX]>;
 
 def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>;
 def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>;
 def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>;
 def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>;
 } // Predicates = [HasVInstructions]
 
 let Predicates = [HasVInstructionsI64] in {

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

foreach eew = EEWList in {
     }
   }
 }
 
 multiclass VPseudoLoadMask {
   foreach mti = AllMasks in {
     defvar mx = mti.LMul.MX;
     defvar WriteVLDM_MX = !cast<SchedWrite>("WriteVLDM_" # mx);
-    defvar ReadVLDX_MX = !cast<SchedRead>("ReadVLDX_" # mx);
     let VLMul = mti.LMul.value in {
       def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, /*EEW*/1, /*DummyMask*/0>,
-        Sched<[WriteVLDM_MX, ReadVLDX_MX]>;
+        Sched<[WriteVLDM_MX, ReadVLDX]>;
     }
   }
 }
 
 multiclass VPseudoSLoad {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
foreach eew = EEWList in {
     }
   }
 }
 
 multiclass VPseudoStoreMask {
   foreach mti = AllMasks in {
     defvar mx = mti.LMul.MX;
     defvar WriteVSTM_MX = !cast<SchedWrite>("WriteVSTM_" # mx);
-    defvar ReadVSTX_MX = !cast<SchedRead>("ReadVSTX_" # mx);
     let VLMul = mti.LMul.value in {
       def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, /*EEW*/1, /*DummyMask*/0>,
-        Sched<[WriteVSTM_MX, ReadVSTX_MX]>;
+        Sched<[WriteVSTM_MX, ReadVSTX]>;
     }
   }
 }
 
 multiclass VPseudoSStore {
   foreach eew = EEWList in {
     foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;

llvm/lib/Target/RISCV/RISCVScheduleV.td

 //===----------------------------------------------------------------------===//
 /// Define scheduler resources associated with use operands.
 
 // 6. Configuration-Setting Instructions
 def ReadVSETVLI       : SchedRead;
 def ReadVSETVL        : SchedRead;
 
 // 7. Vector Loads and Stores
-defm "" : LMULSchedReads<"ReadVLDX">;
-defm "" : LMULSchedReads<"ReadVSTX">;
+def ReadVLDX : SchedRead;
+def ReadVSTX : SchedRead;
 // 7.4. Vector Unit-Stride Instructions
 defm "" : LMULSchedReads<"ReadVSTEV">;
 // 7.4.1. Vector Unit-Strided Mask
 defm "" : LMULSchedReads<"ReadVSTM">;
 // 7.5. Vector Strided Instructions
-defm "" : LMULSchedReads<"ReadVLDSX">;
-defm "" : LMULSchedReads<"ReadVSTSX">;
+def ReadVLDSX : SchedRead;
+def ReadVSTSX : SchedRead;
 defm "" : LMULSchedReads<"ReadVSTS8V">;
 defm "" : LMULSchedReads<"ReadVSTS16V">;
 defm "" : LMULSchedReads<"ReadVSTS32V">;
 defm "" : LMULSchedReads<"ReadVSTS64V">;
 // 7.6. Vector Indexed Instructions
 defm "" : LMULSchedReads<"ReadVLDUXV">;
 defm "" : LMULSchedReads<"ReadVLDOXV">;
 defm "" : LMULSchedReads<"ReadVSTUX8">;

 def : WriteRes<WriteVMov4V, []>;
 def : WriteRes<WriteVMov8V, []>;
 
 // 6. Configuration-Setting Instructions
 def : ReadAdvance<ReadVSETVLI, 0>;
 def : ReadAdvance<ReadVSETVL, 0>;
 
 // 7. Vector Loads and Stores
-defm "" : LMULReadAdvance<"ReadVLDX", 0>;
-defm "" : LMULReadAdvance<"ReadVSTX", 0>;
+def : ReadAdvance<ReadVLDX, 0>;
+def : ReadAdvance<ReadVSTX, 0>;
 defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
 defm "" : LMULReadAdvance<"ReadVSTM", 0>;
-defm "" : LMULReadAdvance<"ReadVLDSX", 0>;
-defm "" : LMULReadAdvance<"ReadVSTSX", 0>;
+def : ReadAdvance<ReadVLDSX, 0>;
+def : ReadAdvance<ReadVSTSX, 0>;
 defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
 defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
 defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
 defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
 defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
 defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
 defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
 defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;