[mlir][llvm] Add missing bit manipulation intrs

[Dinistro]

Summary

This commit adds three missing bit manipulation intrinsics.
LangRef: https://llvm.org/docs/LangRef.html#bit-manipulation-intrinsics

[gysit]

LGTM!

[nikic]

mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td

132

This is a byte swap, not a bit swap.

[Dinistro]

mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td

132

Thanks for pointing this out, fixed in https://reviews.llvm.org/rG3f4d16018d51

mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td

 class LLVM_BinarySameArgsIntrOpF<string func, list<Trait> traits = []> :
     LLVM_BinarySameArgsIntrOpBase<func, LLVM_AnyFloat, traits,
                                   /*requiresFastmath=*/1> {
   dag fmfArg = (
     ins DefaultValuedAttr<LLVM_FastmathFlagsAttr, "{}">:$fastmathFlags);
   let arguments = !con(commonArgs, fmfArg);
 }
 
-class LLVM_TernarySameArgsIntrOpF<string func, list<Trait> traits = []> :
+class LLVM_TernarySameArgsIntrOpBase<string func, Type element,
+              list<Trait> traits = [], bit requiresFastmath = 0> :
     LLVM_OneResultIntrOp<func, [], [0],
            !listconcat([Pure, SameOperandsAndResultType], traits),
-           /*requiresFastmath=*/1> {
-  let arguments = (ins LLVM_ScalarOrVectorOf<AnyFloat>:$a,
-                       LLVM_ScalarOrVectorOf<AnyFloat>:$b,
-                       LLVM_ScalarOrVectorOf<AnyFloat>:$c,
-                       DefaultValuedAttr<LLVM_FastmathFlagsAttr,
-                                         "{}">:$fastmathFlags);
+           requiresFastmath> {
+  dag commonArgs = (ins LLVM_ScalarOrVectorOf<element>:$a,
+                       LLVM_ScalarOrVectorOf<element>:$b,
+                       LLVM_ScalarOrVectorOf<element>:$c);
   let assemblyFormat = "`(` operands `)` custom<LLVMOpAttrs>(attr-dict) `:` "
       "functional-type(operands, results)";
 }
 
+class LLVM_TernarySameArgsIntrOpI<string func, list<Trait> traits = []> :
+    LLVM_TernarySameArgsIntrOpBase<func, AnySignlessInteger, traits> {
+  let arguments = commonArgs;
+}
+
+class LLVM_TernarySameArgsIntrOpF<string func, list<Trait> traits = []> :
+    LLVM_TernarySameArgsIntrOpBase<func, LLVM_AnyFloat, traits,
+                                  /*requiresFastmath=*/1> {
+  dag fmfArg = (
+    ins DefaultValuedAttr<LLVM_FastmathFlagsAttr, "{}">:$fastmathFlags);
+  let arguments = !con(commonArgs, fmfArg);
+}
+
 class LLVM_CountZerosIntrOp<string func, list<Trait> traits = []> :
     LLVM_OneResultIntrOp<func, [], [0],
            !listconcat([Pure], traits)> {
   let arguments = (ins LLVM_ScalarOrVectorOf<AnySignlessInteger>:$in,
                    I1:$zero_undefined);
 }
 
 def LLVM_AbsOp : LLVM_OneResultIntrOp<"abs", [], [0], [Pure]> {
def LLVM_PowIOp : LLVM_OneResultIntrOp<"powi", [], [0,1],
   let arguments =
       (ins LLVM_ScalarOrVectorOf<LLVM_AnyFloat>:$val,
            AnySignlessInteger:$power,
            DefaultValuedAttr<LLVM_FastmathFlagsAttr, "{}">:$fastmathFlags);
   let assemblyFormat = "`(` operands `)` custom<LLVMOpAttrs>(attr-dict) `:` "
       "functional-type(operands, results)";
 }
 def LLVM_BitReverseOp : LLVM_UnaryIntrOpI<"bitreverse">;
+def LLVM_BitSwapOp : LLVM_UnaryIntrOpI<"bswap">;
 def LLVM_CountLeadingZerosOp : LLVM_CountZerosIntrOp<"ctlz">;
 def LLVM_CountTrailingZerosOp : LLVM_CountZerosIntrOp<"cttz">;
 def LLVM_CtPopOp : LLVM_UnaryIntrOpI<"ctpop">;
+def LLVM_FshlOp : LLVM_TernarySameArgsIntrOpI<"fshl">;
+def LLVM_FshrOp : LLVM_TernarySameArgsIntrOpI<"fshr">;
 def LLVM_MaxNumOp : LLVM_BinarySameArgsIntrOpF<"maxnum">;
 def LLVM_MinNumOp : LLVM_BinarySameArgsIntrOpF<"minnum">;
 def LLVM_MaximumOp : LLVM_BinarySameArgsIntrOpF<"maximum">;
 def LLVM_MinimumOp : LLVM_BinarySameArgsIntrOpF<"minimum">;
 def LLVM_SMaxOp : LLVM_BinarySameArgsIntrOpI<"smax">;
 def LLVM_SMinOp : LLVM_BinarySameArgsIntrOpI<"smin">;
 def LLVM_UMaxOp : LLVM_BinarySameArgsIntrOpI<"umax">;
 def LLVM_UMinOp : LLVM_BinarySameArgsIntrOpI<"umin">;

mlir/test/Target/LLVMIR/Import/intrinsic.ll

 ; CHECK-LABEL:  llvm.func @bitreverse_test
 define void @bitreverse_test(i32 %0, <8 x i32> %1) {
   ; CHECK:   llvm.intr.bitreverse(%{{.*}}) : (i32) -> i32
   %3 = call i32 @llvm.bitreverse.i32(i32 %0)
   ; CHECK:   llvm.intr.bitreverse(%{{.*}}) : (vector<8xi32>) -> vector<8xi32>
   %4 = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %1)
   ret void
 }
+; CHECK-LABEL:  llvm.func @bitswap_test
+define void @bitswap_test(i32 %0, <8 x i32> %1) {
+  ; CHECK:   llvm.intr.bswap(%{{.*}}) : (i32) -> i32
+  %3 = call i32 @llvm.bswap.i32(i32 %0)
+  ; CHECK:   llvm.intr.bswap(%{{.*}}) : (vector<8xi32>) -> vector<8xi32>
+  %4 = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %1)
+  ret void
+}
 ; CHECK-LABEL:  llvm.func @ctlz_test
 define void @ctlz_test(i32 %0, <8 x i32> %1) {
   ; CHECK:   %[[FALSE:.+]] = llvm.mlir.constant(false) : i1
   ; CHECK:   "llvm.intr.ctlz"(%{{.*}}, %[[FALSE]]) : (i32, i1) -> i32
   %3 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
   ; CHECK:   "llvm.intr.ctlz"(%{{.*}}, %[[FALSE]]) : (vector<8xi32>, i1) -> vector<8xi32>
   %4 = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %1, i1 false)
   ret void

 define void @ctpop_test(i32 %0, <8 x i32> %1) {
   ; CHECK:   llvm.intr.ctpop(%{{.*}}) : (i32) -> i32
   %3 = call i32 @llvm.ctpop.i32(i32 %0)
   ; CHECK:   llvm.intr.ctpop(%{{.*}}) : (vector<8xi32>) -> vector<8xi32>
   %4 = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %1)
   ret void
 }
 
+; CHECK-LABEL:  llvm.func @fshl_test
+define void @fshl_test(i32 %0, i32 %1, i32 %2, <8 x i32> %3, <8 x i32> %4, <8 x i32> %5) {
+  ; CHECK:   llvm.intr.fshl(%{{.*}}, %{{.*}}, %{{.*}}) : (i32, i32, i32) -> i32
+  %7 = call i32 @llvm.fshl.i32(i32 %0, i32 %1, i32 %2)
+  ; CHECK:   llvm.intr.fshl(%{{.*}}, %{{.*}}, %{{.*}}) : (vector<8xi32>, vector<8xi32>, vector<8xi32>) -> vector<8xi32>
+  %8 = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %3, <8 x i32> %4, <8 x i32> %5)
+  ret void
+}
+
+; CHECK-LABEL:  llvm.func @fshr_test
+define void @fshr_test(i32 %0, i32 %1, i32 %2, <8 x i32> %3, <8 x i32> %4, <8 x i32> %5) {
+  ; CHECK:   llvm.intr.fshr(%{{.*}}, %{{.*}}, %{{.*}}) : (i32, i32, i32) -> i32
+  %7 = call i32 @llvm.fshr.i32(i32 %0, i32 %1, i32 %2)
+  ; CHECK:   llvm.intr.fshr(%{{.*}}, %{{.*}}, %{{.*}}) : (vector<8xi32>, vector<8xi32>, vector<8xi32>) -> vector<8xi32>
+  %8 = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %3, <8 x i32> %4, <8 x i32> %5)
+  ret void
+}
+
 ; CHECK-LABEL:  llvm.func @maximum_test
 define void @maximum_test(float %0, float %1, <8 x float> %2, <8 x float> %3) {
   ; CHECK:   llvm.intr.maximum(%{{.*}}, %{{.*}}) : (f32, f32) -> f32
   %5 = call float @llvm.maximum.f32(float %0, float %1)
   ; CHECK:   llvm.intr.maximum(%{{.*}}, %{{.*}}) : (vector<8xf32>, vector<8xf32>) -> vector<8xf32>
   %6 = call <8 x float> @llvm.maximum.v8f32(<8 x float> %2, <8 x float> %3)
   ret void
 }

 declare float @llvm.cos.f32(float)
 declare <8 x float> @llvm.cos.v8f32(<8 x float>)
 declare float @llvm.copysign.f32(float, float)
 declare <8 x float> @llvm.copysign.v8f32(<8 x float>, <8 x float>)
 declare float @llvm.pow.f32(float, float)
 declare <8 x float> @llvm.pow.v8f32(<8 x float>, <8 x float>)
 declare i32 @llvm.bitreverse.i32(i32)
 declare <8 x i32> @llvm.bitreverse.v8i32(<8 x i32>)
+declare i32 @llvm.bswap.i32(i32)
+declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
 declare i32 @llvm.ctlz.i32(i32, i1 immarg)
 declare <8 x i32> @llvm.ctlz.v8i32(<8 x i32>, i1 immarg)
 declare i32 @llvm.cttz.i32(i32, i1 immarg)
 declare <8 x i32> @llvm.cttz.v8i32(<8 x i32>, i1 immarg)
 declare i32 @llvm.ctpop.i32(i32)
 declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>)
+declare i32 @llvm.fshl.i32(i32, i32, i32)
+declare <8 x i32> @llvm.fshl.v8i32(<8 x i32>, <8 x i32>, <8 x i32>)
+declare i32 @llvm.fshr.i32(i32, i32, i32)
+declare <8 x i32> @llvm.fshr.v8i32(<8 x i32>, <8 x i32>, <8 x i32>)
 declare float @llvm.maximum.f32(float, float)
 declare <8 x float> @llvm.maximum.v8f32(<8 x float>, <8 x float>)
 declare float @llvm.minimum.f32(float, float)
 declare <8 x float> @llvm.minimum.v8f32(<8 x float>, <8 x float>)
 declare float @llvm.maxnum.f32(float, float)
 declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>)
 declare float @llvm.minnum.f32(float, float)
 declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>)

mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir

 llvm.func @bitreverse_test(%arg0: i32, %arg1: vector<8xi32>) {
   // CHECK: call i32 @llvm.bitreverse.i32
   "llvm.intr.bitreverse"(%arg0) : (i32) -> i32
   // CHECK: call <8 x i32> @llvm.bitreverse.v8i32
   "llvm.intr.bitreverse"(%arg1) : (vector<8xi32>) -> vector<8xi32>
   llvm.return
 }
 
+// CHECK-LABEL: @bitswap_test
+llvm.func @bitswap_test(%arg0: i32, %arg1: vector<8xi32>) {
+  // CHECK: call i32 @llvm.bswap.i32
+  "llvm.intr.bswap"(%arg0) : (i32) -> i32
+  // CHECK: call <8 x i32> @llvm.bswap.v8i32
+  "llvm.intr.bswap"(%arg1) : (vector<8xi32>) -> vector<8xi32>
+  llvm.return
+}
+
 // CHECK-LABEL: @ctlz_test
 llvm.func @ctlz_test(%arg0: i32, %arg1: vector<8xi32>) {
   %i1 = llvm.mlir.constant(false) : i1
   // CHECK: call i32 @llvm.ctlz.i32
   "llvm.intr.ctlz"(%arg0, %i1) : (i32, i1) -> i32
   // CHECK: call <8 x i32> @llvm.ctlz.v8i32
   "llvm.intr.ctlz"(%arg1, %i1) : (vector<8xi32>, i1) -> vector<8xi32>
   llvm.return

 llvm.func @ctpop_test(%arg0: i32, %arg1: vector<8xi32>) {
   // CHECK: call i32 @llvm.ctpop.i32
   "llvm.intr.ctpop"(%arg0) : (i32) -> i32
   // CHECK: call <8 x i32> @llvm.ctpop.v8i32
   "llvm.intr.ctpop"(%arg1) : (vector<8xi32>) -> vector<8xi32>
   llvm.return
 }
 
+// CHECK-LABEL: @fshl_test
+llvm.func @fshl_test(%arg0: i32, %arg1: i32, %arg2: i32, %arg3: vector<8xi32>, %arg4: vector<8xi32>, %arg5: vector<8xi32>) {
+  // CHECK: call i32 @llvm.fshl.i32
+  "llvm.intr.fshl"(%arg0, %arg1, %arg2) : (i32, i32, i32) -> i32
+  // CHECK: call <8 x i32> @llvm.fshl.v8i32
+  "llvm.intr.fshl"(%arg3, %arg4, %arg5) : (vector<8xi32>, vector<8xi32>, vector<8xi32>) -> vector<8xi32>
+  llvm.return
+}
+
+// CHECK-LABEL: @fshr_test
+llvm.func @fshr_test(%arg0: i32, %arg1: i32, %arg2: i32, %arg3: vector<8xi32>, %arg4: vector<8xi32>, %arg5: vector<8xi32>) {
+  // CHECK: call i32 @llvm.fshr.i32
+  "llvm.intr.fshr"(%arg0, %arg1, %arg2) : (i32, i32, i32) -> i32
+  // CHECK: call <8 x i32> @llvm.fshr.v8i32
+  "llvm.intr.fshr"(%arg3, %arg4, %arg5) : (vector<8xi32>, vector<8xi32>, vector<8xi32>) -> vector<8xi32>
+  llvm.return
+}
+
 // CHECK-LABEL: @maximum_test
 llvm.func @maximum_test(%arg0: f32, %arg1: f32, %arg2: vector<8xf32>, %arg3: vector<8xf32>) {
   // CHECK: call float @llvm.maximum.f32
   "llvm.intr.maximum"(%arg0, %arg1) : (f32, f32) -> f32
   // CHECK: call <8 x float> @llvm.maximum.v8f32
   "llvm.intr.maximum"(%arg2, %arg3) : (vector<8xf32>, vector<8xf32>) -> vector<8xf32>
   llvm.return
 }

mlir/test/Target/LLVMIR/llvmir-invalid.mlir

llvm.func @binary_int_intr_wrong_type(%arg0 : i32, %arg1 : f32) -> f32 {
   // expected-error @below{{op operand #1 must be signless integer or LLVM dialect-compatible vector of signless integer}}
   %0 = "llvm.intr.smax"(%arg0, %arg1) : (i32, f32) -> f32
   llvm.return %0 : f32
 }
 
 // -----
 
 llvm.func @ternary_float_intr_wrong_type(%arg0 : f32, %arg1 : f32, %arg2 : i32) -> f32 {
-  // expected-error @below{{op operand #2 must be floating-point or LLVM dialect-compatible vector of floating-point}}
+  // expected-error @below{{op operand #2 must be floating point LLVM type or LLVM dialect-compatible vector of floating point LLVM type}}
   %0 = "llvm.intr.fma"(%arg0, %arg1, %arg2) : (f32, f32, i32) -> f32
   llvm.return %0 : f32
 }
 
 // -----
 
 llvm.func @powi_intr_wrong_type(%arg0 : f32, %arg1 : f32) -> f32 {
   // expected-error @below{{op operand #1 must be signless integer, but got 'f32'}}