[ARM] Fix VMOVSR pattern requirements

[miyuki]

Summary

The required target features for VMOVSR instruction (integer -> MVE
FP register copy) are HasFPRegs and UseVMOVSR (see
https://reviews.llvm.org/D60694).

The instruction selection pattern must use the same set of
requirements (i.e., HasFPRegs instead of HasVFP2). The discrepancy
can cause instruction selection failure when compiling code for
execute-only position-independence mode.

[dmgreen]

It looks like there is only one place where the VMOVSR is created, with execute-only. Can you use this as a test case: https://godbolt.org/z/zbhqr38xP.

[miyuki]

Sorry, I didn't realize that we have execute-only in upstream LLVM.

[dmgreen]

Thanks. LGTM

llvm/lib/Target/ARM/ARMInstrVFP.td

def VMOVSR : AVConv4I<0b11100000, 0b1010,
   let Inst{6-5}   = 0b00;
   let Inst{3-0}   = 0b0000;
 
   // Some single precision VFP instructions may be executed on both NEON and VFP
   // pipelines.
   let D = VFPNeonDomain;
 }
 } // isMoveReg
-def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasVFP2, UseVMOVSR]>;
+def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasFPRegs, UseVMOVSR]>;
 
 let hasSideEffects = 0 in {
 def VMOVRRD  : AVConv3I<0b11000101, 0b1011,
                         (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
                         IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
                  [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>,
                Requires<[HasFPRegs]>,
                Sched<[WriteFPMOV]> {