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Differential D147484

[AArch64][GlobalISel] Move the localizer to run before the legalizer, and always localize globals.
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Authored by aemerson on Apr 3 2023, 4:24 PM.

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paquette
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rG1e2f87868f6f: [AArch64][GlobalISel] Move the localizer to run before the legalizer, and…
Summary

Our strategy for localizing globals in the entry block breaks down when we have
large functions with high register pressure, using lots of globals. When this
happens, our heuristics say that globals with many uses should not be localized,
leading us to cause excessive spills and stack usage. These situations are also
exacerbated by LTO which tends to generate large functions.

For now, moving to a strategy that's simpler and more akin to SelectionDAG
fixes these issues and makes our codegen more similar. This has an overall
neutral effect on size on CTMark, while showing slight improvements with -Os -flto
on benchmarks. For low level firmware software though we see big improvements.

The reason this is neutral, and not an improvement, is because we give up the
gains from CSE'ing globals in cases where we low register pressure. I think
this can be addressed in future with some better heuristics.

Diff Detail

Event Timeline

aemerson created this revision.Apr 3 2023, 4:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 3 2023, 4:24 PM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
aemerson requested review of this revision.Apr 3 2023, 4:24 PM
paquette accepted this revision.Apr 3 2023, 4:36 PM

LGTM

This revision is now accepted and ready to land.Apr 3 2023, 4:36 PM
Harbormaster completed remote builds in B223461: Diff 510640.Apr 3 2023, 5:12 PM
Closed by commit rG1e2f87868f6f: [AArch64][GlobalISel] Move the localizer to run before the legalizer, and… (authored by aemerson). · Explain WhyApr 3 2023, 8:42 PM
This revision was automatically updated to reflect the committed changes.
aemerson added a commit: rG1e2f87868f6f: [AArch64][GlobalISel] Move the localizer to run before the legalizer, and….

Revision Contents

Diff 510678

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 23,240 Lines • ▼ Show 20 Linesbool AArch64TargetLowering::shouldLocalize(
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case TargetOpcode::G_GLOBAL_VALUE: { case TargetOpcode::G_GLOBAL_VALUE: {
// On Darwin, TLS global vars get selected into function calls, which // On Darwin, TLS global vars get selected into function calls, which
// we don't want localized, as they can get moved into the middle of a // we don't want localized, as they can get moved into the middle of a
// another call sequence. // another call sequence.
const GlobalValue &GV = *MI.getOperand(1).getGlobal(); const GlobalValue &GV = *MI.getOperand(1).getGlobal();
if (GV.isThreadLocal() && Subtarget->isTargetMachO()) if (GV.isThreadLocal() && Subtarget->isTargetMachO())
return false; return false;
break; return true; // Always localize G_GLOBAL_VALUE to avoid high reg pressure.
} }
case TargetOpcode::G_CONSTANT: { case TargetOpcode::G_CONSTANT: {
auto *CI = MI.getOperand(1).getCImm(); auto *CI = MI.getOperand(1).getCImm();
APInt Imm = CI->getValue(); APInt Imm = CI->getValue();
InstructionCost Cost = TTI->getIntImmCost( InstructionCost Cost = TTI->getIntImmCost(
Imm, CI->getType(), TargetTransformInfo::TCK_CodeSize); Imm, CI->getType(), TargetTransformInfo::TCK_CodeSize);
assert(Cost.isValid() && "Expected a valid imm cost"); assert(Cost.isValid() && "Expected a valid imm cost");
unsigned RematCost = *Cost.getValue(); unsigned RematCost = *Cost.getValue();
Register Reg = MI.getOperand(0).getReg(); Register Reg = MI.getOperand(0).getReg();
unsigned MaxUses = maxUses(RematCost); unsigned MaxUses = maxUses(RematCost);
// Don't pass UINT_MAX sentinal value to hasAtMostUserInstrs(). // Don't pass UINT_MAX sentinal value to hasAtMostUserInstrs().
if (MaxUses == std::numeric_limits<unsigned>::max()) if (MaxUses == std::numeric_limits<unsigned>::max())
--MaxUses; --MaxUses;
return MRI.hasAtMostUserInstrs(Reg, MaxUses); return MRI.hasAtMostUserInstrs(Reg, MaxUses);
} }
// If we legalized G_GLOBAL_VALUE into ADRP + G_ADD_LOW, mark both as being // If we legalized G_GLOBAL_VALUE into ADRP + G_ADD_LOW, mark both as being
// localizable. // localizable.
case AArch64::ADRP: case AArch64::ADRP:
case AArch64::G_ADD_LOW: case AArch64::G_ADD_LOW:
// Need to localize G_PTR_ADD so that G_GLOBAL_VALUE can be localized too.
case TargetOpcode::G_PTR_ADD:
return true; return true;
default: default:
break; break;
} }
return TargetLoweringBase::shouldLocalize(MI, TTI); return TargetLoweringBase::shouldLocalize(MI, TTI);
} }
bool AArch64TargetLowering::fallBackToDAGISel(const Instruction &Inst) const { bool AArch64TargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
▲ Show 20 Lines • Show All 1,269 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

Show First 20 Lines • Show All 504 Lines • ▼ Show 20 Linespublic:
bool addPreISel() override; bool addPreISel() override;
void addCodeGenPrepare() override; void addCodeGenPrepare() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addIRTranslator() override; bool addIRTranslator() override;
void addPreLegalizeMachineIR() override; void addPreLegalizeMachineIR() override;
bool addLegalizeMachineIR() override; bool addLegalizeMachineIR() override;
void addPreRegBankSelect() override; void addPreRegBankSelect() override;
bool addRegBankSelect() override; bool addRegBankSelect() override;
void addPreGlobalInstructionSelect() override;
bool addGlobalInstructionSelect() override; bool addGlobalInstructionSelect() override;
void addMachineSSAOptimization() override; void addMachineSSAOptimization() override;
bool addILPOpts() override; bool addILPOpts() override;
void addPreRegAlloc() override; void addPreRegAlloc() override;
void addPostRegAlloc() override; void addPostRegAlloc() override;
void addPreSched2() override; void addPreSched2() override;
void addPreEmitPass() override; void addPreEmitPass() override;
void addPreEmitPass2() override; void addPreEmitPass2() override;
▲ Show 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
} }
bool AArch64PassConfig::addIRTranslator() { bool AArch64PassConfig::addIRTranslator() {
addPass(new IRTranslator(getOptLevel())); addPass(new IRTranslator(getOptLevel()));
return false; return false;
} }
void AArch64PassConfig::addPreLegalizeMachineIR() { void AArch64PassConfig::addPreLegalizeMachineIR() {
if (getOptLevel() == CodeGenOpt::None) if (getOptLevel() == CodeGenOpt::None) {
addPass(createAArch64O0PreLegalizerCombiner()); addPass(createAArch64O0PreLegalizerCombiner());
else { addPass(new Localizer());
} else {
addPass(createAArch64PreLegalizerCombiner()); addPass(createAArch64PreLegalizerCombiner());
addPass(new Localizer());
if (EnableGISelLoadStoreOptPreLegal) if (EnableGISelLoadStoreOptPreLegal)
addPass(new LoadStoreOpt()); addPass(new LoadStoreOpt());
} }
} }
bool AArch64PassConfig::addLegalizeMachineIR() { bool AArch64PassConfig::addLegalizeMachineIR() {
addPass(new Legalizer()); addPass(new Legalizer());
return false; return false;
Show All 9 Linesvoid AArch64PassConfig::addPreRegBankSelect() {
addPass(createAArch64PostLegalizerLowering()); addPass(createAArch64PostLegalizerLowering());
} }
bool AArch64PassConfig::addRegBankSelect() { bool AArch64PassConfig::addRegBankSelect() {
addPass(new RegBankSelect()); addPass(new RegBankSelect());
return false; return false;
} }
void AArch64PassConfig::addPreGlobalInstructionSelect() {
addPass(new Localizer());
}
bool AArch64PassConfig::addGlobalInstructionSelect() { bool AArch64PassConfig::addGlobalInstructionSelect() {
addPass(new InstructionSelect(getOptLevel())); addPass(new InstructionSelect(getOptLevel()));
if (getOptLevel() != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
addPass(createAArch64PostSelectOptimize()); addPass(createAArch64PostSelectOptimize());
return false; return false;
} }
void AArch64PassConfig::addMachineSSAOptimization() { void AArch64PassConfig::addMachineSSAOptimization() {
▲ Show 20 Lines • Show All 148 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll

Show First 20 Lines • Show All 2,723 Lines • ▼ Show 20 Lines; CHECK-LSE-O0-NEXT: ret
%res = atomicrmw umax ptr %ptr, i16 %rhs monotonic %res = atomicrmw umax ptr %ptr, i16 %rhs monotonic
ret i16 %res ret i16 %res
} }
define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) { define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-NOLSE-O1-LABEL: cmpxchg_i8: ; CHECK-NOLSE-O1-LABEL: cmpxchg_i8:
; CHECK-NOLSE-O1: ; %bb.0: ; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: mov x8, x0 ; CHECK-NOLSE-O1-NEXT: mov x8, x0
; CHECK-NOLSE-O1-NEXT: mov w9, w1
; CHECK-NOLSE-O1-NEXT: mov w1, wzr
; CHECK-NOLSE-O1-NEXT: ; kill: def $w2 killed $w2 def $x2 ; CHECK-NOLSE-O1-NEXT: ; kill: def $w2 killed $w2 def $x2
; CHECK-NOLSE-O1-NEXT: LBB47_1: ; %cmpxchg.start ; CHECK-NOLSE-O1-NEXT: LBB47_1: ; %cmpxchg.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldxrb w0, [x8] ; CHECK-NOLSE-O1-NEXT: ldxrb w0, [x8]
; CHECK-NOLSE-O1-NEXT: and w9, w0, #0xff ; CHECK-NOLSE-O1-NEXT: and w10, w0, #0xff
; CHECK-NOLSE-O1-NEXT: cmp w9, w1, uxtb ; CHECK-NOLSE-O1-NEXT: cmp w10, w9, uxtb
; CHECK-NOLSE-O1-NEXT: b.ne LBB47_4 ; CHECK-NOLSE-O1-NEXT: b.ne LBB47_4
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %cmpxchg.trystore ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %cmpxchg.trystore
; CHECK-NOLSE-O1-NEXT: ; in Loop: Header=BB47_1 Depth=1 ; CHECK-NOLSE-O1-NEXT: ; in Loop: Header=BB47_1 Depth=1
; CHECK-NOLSE-O1-NEXT: stxrb w9, w2, [x8] ; CHECK-NOLSE-O1-NEXT: stxrb w10, w2, [x8]
; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB47_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB47_1
; CHECK-NOLSE-O1-NEXT: ; %bb.3: ; CHECK-NOLSE-O1-NEXT: ; %bb.3:
; CHECK-NOLSE-O1-NEXT: mov w1, #1 ; CHECK-NOLSE-O1-NEXT: mov w1, #1
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0 ; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; CHECK-NOLSE-O1-NEXT: LBB47_4: ; %cmpxchg.nostore ; CHECK-NOLSE-O1-NEXT: LBB47_4: ; %cmpxchg.nostore
; CHECK-NOLSE-O1-NEXT: mov w1, wzr
; CHECK-NOLSE-O1-NEXT: clrex ; CHECK-NOLSE-O1-NEXT: clrex
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0 ; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: cmpxchg_i8: ; CHECK-NOLSE-O0-LABEL: cmpxchg_i8:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: mov x9, x0 ; CHECK-NOLSE-O0-NEXT: mov x9, x0
; CHECK-NOLSE-O0-NEXT: LBB47_1: ; =>This Inner Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: LBB47_1: ; =>This Inner Loop Header: Depth=1
Show All 33 Lines; CHECK-LSE-O0-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %desired, i8 %new monotonic monotonic %res = cmpxchg ptr %ptr, i8 %desired, i8 %new monotonic monotonic
ret { i8, i1 } %res ret { i8, i1 } %res
} }
define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) { define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-NOLSE-O1-LABEL: cmpxchg_i16: ; CHECK-NOLSE-O1-LABEL: cmpxchg_i16:
; CHECK-NOLSE-O1: ; %bb.0: ; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: mov x8, x0 ; CHECK-NOLSE-O1-NEXT: mov x8, x0
; CHECK-NOLSE-O1-NEXT: mov w9, w1
; CHECK-NOLSE-O1-NEXT: mov w1, wzr
; CHECK-NOLSE-O1-NEXT: ; kill: def $w2 killed $w2 def $x2 ; CHECK-NOLSE-O1-NEXT: ; kill: def $w2 killed $w2 def $x2
; CHECK-NOLSE-O1-NEXT: LBB48_1: ; %cmpxchg.start ; CHECK-NOLSE-O1-NEXT: LBB48_1: ; %cmpxchg.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldxrh w0, [x8] ; CHECK-NOLSE-O1-NEXT: ldxrh w0, [x8]
; CHECK-NOLSE-O1-NEXT: and w9, w0, #0xffff ; CHECK-NOLSE-O1-NEXT: and w10, w0, #0xffff
; CHECK-NOLSE-O1-NEXT: cmp w9, w1, uxth ; CHECK-NOLSE-O1-NEXT: cmp w10, w9, uxth
; CHECK-NOLSE-O1-NEXT: b.ne LBB48_4 ; CHECK-NOLSE-O1-NEXT: b.ne LBB48_4
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %cmpxchg.trystore ; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %cmpxchg.trystore
; CHECK-NOLSE-O1-NEXT: ; in Loop: Header=BB48_1 Depth=1 ; CHECK-NOLSE-O1-NEXT: ; in Loop: Header=BB48_1 Depth=1
; CHECK-NOLSE-O1-NEXT: stxrh w9, w2, [x8] ; CHECK-NOLSE-O1-NEXT: stxrh w10, w2, [x8]
; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB48_1 ; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB48_1
; CHECK-NOLSE-O1-NEXT: ; %bb.3: ; CHECK-NOLSE-O1-NEXT: ; %bb.3:
; CHECK-NOLSE-O1-NEXT: mov w1, #1 ; CHECK-NOLSE-O1-NEXT: mov w1, #1
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0 ; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; CHECK-NOLSE-O1-NEXT: LBB48_4: ; %cmpxchg.nostore ; CHECK-NOLSE-O1-NEXT: LBB48_4: ; %cmpxchg.nostore
; CHECK-NOLSE-O1-NEXT: mov w1, wzr
; CHECK-NOLSE-O1-NEXT: clrex ; CHECK-NOLSE-O1-NEXT: clrex
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0 ; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NOLSE-O1-NEXT: ret ; CHECK-NOLSE-O1-NEXT: ret
; ;
; CHECK-NOLSE-O0-LABEL: cmpxchg_i16: ; CHECK-NOLSE-O0-LABEL: cmpxchg_i16:
; CHECK-NOLSE-O0: ; %bb.0: ; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: mov x9, x0 ; CHECK-NOLSE-O0-NEXT: mov x9, x0
; CHECK-NOLSE-O0-NEXT: LBB48_1: ; =>This Inner Loop Header: Depth=1 ; CHECK-NOLSE-O0-NEXT: LBB48_1: ; =>This Inner Loop Header: Depth=1
▲ Show 20 Lines • Show All 149 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll

Show First 20 Lines • Show All 1,242 Lines • ▼ Show 20 Lines
define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) { define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
; CHECK-LABEL: name: cmpxchg_i8 ; CHECK-LABEL: name: cmpxchg_i8
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $w1, $w2, $x0 ; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0 ; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
; CHECK-NEXT: $w9 = ORRWrs $wzr, $w1, 0
; CHECK-NEXT: renamable $w2 = KILL $w2, implicit-def $x2 ; CHECK-NEXT: renamable $w2 = KILL $w2, implicit-def $x2
; CHECK-NEXT: $w1 = ORRWrs $wzr, $wzr, 0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.cmpxchg.start: ; CHECK-NEXT: bb.1.cmpxchg.start:
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000) ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
; CHECK-NEXT: liveins: $w1, $x2, $x8 ; CHECK-NEXT: liveins: $w1, $w9, $x2, $x8
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s8) from %ir.ptr) ; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s8) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 7, pcsections !0 ; CHECK-NEXT: renamable $w10 = ANDWri renamable $w0, 7, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 0, implicit-def $nzcv, pcsections !0 ; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.4, implicit killed $nzcv, pcsections !0 ; CHECK-NEXT: Bcc 1, %bb.4, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore: ; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000) ; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000)
; CHECK-NEXT: liveins: $w1, $x0, $x2, $x8 ; CHECK-NEXT: liveins: $w1, $w9, $x0, $x2, $x8
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s8) into %ir.ptr) ; CHECK-NEXT: early-clobber renamable $w10 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1 ; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3: ; CHECK-NEXT: bb.3:
; CHECK-NEXT: liveins: $x0 ; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w1 = MOVZWi 1, 0 ; CHECK-NEXT: renamable $w1 = MOVZWi 1, 0
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0 ; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1 ; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.cmpxchg.nostore: ; CHECK-NEXT: bb.4.cmpxchg.nostore:
; CHECK-NEXT: liveins: $x0 ; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $w1 = ORRWrs $wzr, $wzr, 0
; CHECK-NEXT: CLREX 15, pcsections !0 ; CHECK-NEXT: CLREX 15, pcsections !0
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0 ; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1 ; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1
%res = cmpxchg ptr %ptr, i8 %desired, i8 %new monotonic monotonic, !pcsections !0 %res = cmpxchg ptr %ptr, i8 %desired, i8 %new monotonic monotonic, !pcsections !0
ret { i8, i1 } %res ret { i8, i1 } %res
} }
define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) { define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
; CHECK-LABEL: name: cmpxchg_i16 ; CHECK-LABEL: name: cmpxchg_i16
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $w1, $w2, $x0 ; CHECK-NEXT: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0 ; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
; CHECK-NEXT: $w9 = ORRWrs $wzr, $w1, 0
; CHECK-NEXT: renamable $w2 = KILL $w2, implicit-def $x2 ; CHECK-NEXT: renamable $w2 = KILL $w2, implicit-def $x2
; CHECK-NEXT: $w1 = ORRWrs $wzr, $wzr, 0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.cmpxchg.start: ; CHECK-NEXT: bb.1.cmpxchg.start:
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000) ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
; CHECK-NEXT: liveins: $w1, $x2, $x8 ; CHECK-NEXT: liveins: $w1, $w9, $x2, $x8
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s16) from %ir.ptr) ; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s16) from %ir.ptr)
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 15, pcsections !0 ; CHECK-NEXT: renamable $w10 = ANDWri renamable $w0, 15, pcsections !0
; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w9, renamable $w1, 8, implicit-def $nzcv, pcsections !0 ; CHECK-NEXT: dead $wzr = SUBSWrx killed renamable $w10, renamable $w9, 8, implicit-def $nzcv, pcsections !0
; CHECK-NEXT: Bcc 1, %bb.4, implicit killed $nzcv, pcsections !0 ; CHECK-NEXT: Bcc 1, %bb.4, implicit killed $nzcv, pcsections !0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cmpxchg.trystore: ; CHECK-NEXT: bb.2.cmpxchg.trystore:
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000) ; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000)
; CHECK-NEXT: liveins: $w1, $x0, $x2, $x8 ; CHECK-NEXT: liveins: $w1, $w9, $x0, $x2, $x8
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s16) into %ir.ptr) ; CHECK-NEXT: early-clobber renamable $w10 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1 ; CHECK-NEXT: CBNZW killed renamable $w10, %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3: ; CHECK-NEXT: bb.3:
; CHECK-NEXT: liveins: $x0 ; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w1 = MOVZWi 1, 0 ; CHECK-NEXT: renamable $w1 = MOVZWi 1, 0
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0 ; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1 ; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.cmpxchg.nostore: ; CHECK-NEXT: bb.4.cmpxchg.nostore:
; CHECK-NEXT: liveins: $x0 ; CHECK-NEXT: liveins: $w1, $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $w1 = ORRWrs $wzr, $wzr, 0
; CHECK-NEXT: CLREX 15, pcsections !0 ; CHECK-NEXT: CLREX 15, pcsections !0
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0 ; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1 ; CHECK-NEXT: RET undef $lr, implicit $w0, implicit $w1
%res = cmpxchg ptr %ptr, i16 %desired, i16 %new monotonic monotonic, !pcsections !0 %res = cmpxchg ptr %ptr, i16 %desired, i16 %new monotonic monotonic, !pcsections !0
ret { i16, i1 } %res ret { i16, i1 } %res
} }
!0 = !{!"foo"} !0 = !{!"foo"}

llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; ENABLED-O1: Basic Alias Analysis (stateless AA impl) ; ENABLED-O1: Basic Alias Analysis (stateless AA impl)
; ENABLED-O1-NEXT: Function Alias Analysis Results ; ENABLED-O1-NEXT: Function Alias Analysis Results
; ENABLED: IRTranslator ; ENABLED: IRTranslator
; VERIFY-NEXT: Verify generated machine code ; VERIFY-NEXT: Verify generated machine code
; ENABLED-NEXT: Analysis for ComputingKnownBits ; ENABLED-NEXT: Analysis for ComputingKnownBits
; ENABLED-O1-NEXT: MachineDominator Tree Construction ; ENABLED-O1-NEXT: MachineDominator Tree Construction
; ENABLED-O1-NEXT: Analysis containing CSE Info ; ENABLED-O1-NEXT: Analysis containing CSE Info
; ENABLED-O1-NEXT: PreLegalizerCombiner ; ENABLED-O1-NEXT: PreLegalizerCombiner
; ENABLED-O1-NEXT: Localizer
; VERIFY-O0-NEXT: AArch64O0PreLegalizerCombiner ; VERIFY-O0-NEXT: AArch64O0PreLegalizerCombiner
; VERIFY-NEXT: Verify generated machine code ; VERIFY-NEXT: Verify generated machine code
; ENABLED-O1-NEXT: LoadStoreOpt ; ENABLED-O1-NEXT: LoadStoreOpt
; VERIFY-O0-NEXT: Analysis containing CSE Info ; ENABLED-O1-NEXT: Analysis containing CSE Info
; ENABLED-NEXT: Legalizer ; ENABLED: Legalizer
; VERIFY-NEXT: Verify generated machine code ; VERIFY-NEXT: Verify generated machine code
; ENABLED: RegBankSelect ; ENABLED: RegBankSelect
; VERIFY-NEXT: Verify generated machine code ; VERIFY-NEXT: Verify generated machine code
; ENABLED-NEXT: Localizer
; VERIFY-O0-NEXT: Verify generated machine code
; ENABLED-NEXT: Analysis for ComputingKnownBits ; ENABLED-NEXT: Analysis for ComputingKnownBits
; ENABLED-O1-NEXT: Lazy Branch Probability Analysis ; ENABLED-O1-NEXT: Lazy Branch Probability Analysis
; ENABLED-O1-NEXT: Lazy Block Frequency Analysis ; ENABLED-O1-NEXT: Lazy Block Frequency Analysis
; ENABLED-NEXT: InstructionSelect ; ENABLED-NEXT: InstructionSelect
; ENABLED-O1-NEXT: AArch64 Post Select Optimizer ; ENABLED-O1-NEXT: AArch64 Post Select Optimizer
; VERIFY-NEXT: Verify generated machine code ; VERIFY-NEXT: Verify generated machine code
; ENABLED-NEXT: ResetMachineFunction ; ENABLED-NEXT: ResetMachineFunction
Show All 11 Lines

llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=legalizer %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=legalizer %s -o - | FileCheck %s
@global_var = external global i32 @global_var = external global i32
declare i32 @__gxx_personality_v0(...) declare i32 @__gxx_personality_v0(...)
declare void @may_throw() declare void @may_throw()
; This test checks that the widened G_CONSTANT operand to the phi in "continue" bb ; This test checks that the widened G_CONSTANT operand to the phi in "continue" bb
; is placed before the potentially throwing call in the entry block. ; is placed before the potentially throwing call in the entry block.
define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0 { define i1 @test_lpad_phi_widen_into_pred() personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: name: test_lpad_phi_widen_into_pred ; CHECK-LABEL: name: test_lpad_phi_widen_into_pred
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: G_STORE [[C]](s32), [[GV]](p0) :: (store (s32) into @global_var) ; CHECK-NEXT: G_STORE [[C1]](s32), [[GV]](p0) :: (store (s32) into @global_var)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK-NEXT: G_INVOKE_REGION_START ; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol > ; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @may_throw, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp ; CHECK-NEXT: BL @may_throw, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: EH_LABEL <mcsymbol > ; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_BR %bb.3 ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.lpad (landing-pad): ; CHECK-NEXT: bb.2.lpad (landing-pad):
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1 ; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol > ; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV]](p0) :: (store (s32) into @global_var) ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV1]](p0) :: (store (s32) into @global_var)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK-NEXT: G_BR %bb.3 ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue: ; CHECK-NEXT: bb.3.continue:
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[C2]](s16), %bb.1, [[C3]](s16), %bb.2 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[C2]](s16), %bb.1, [[C3]](s16), %bb.2
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16) ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
Show All 18 Lines
; Same test but with extensions. ; Same test but with extensions.
define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_personality_v0 { define i1 @test_lpad_phi_widen_into_pred_ext(ptr %ptr) personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: name: test_lpad_phi_widen_into_pred_ext ; CHECK-LABEL: name: test_lpad_phi_widen_into_pred_ext
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $x0 ; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: G_STORE [[C]](s32), [[GV]](p0) :: (store (s32) into @global_var) ; CHECK-NEXT: G_STORE [[C1]](s32), [[GV]](p0) :: (store (s32) into @global_var)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.ptr) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.ptr)
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1 ; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[ASSERT_ZEXT]](s8) ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[ASSERT_ZEXT]](s8)
; CHECK-NEXT: G_INVOKE_REGION_START ; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol > ; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @may_throw, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp ; CHECK-NEXT: BL @may_throw, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: EH_LABEL <mcsymbol > ; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_BR %bb.3 ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.lpad (landing-pad): ; CHECK-NEXT: bb.2.lpad (landing-pad):
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1 ; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.1
; CHECK-NEXT: EH_LABEL <mcsymbol > ; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV]](p0) :: (store (s32) into @global_var) ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @global_var
; CHECK-NEXT: G_STORE [[PHI]](s32), [[GV1]](p0) :: (store (s32) into @global_var)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK-NEXT: G_BR %bb.3 ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue: ; CHECK-NEXT: bb.3.continue:
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[ANYEXT]](s16), %bb.1, [[C2]](s16), %bb.2 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[ANYEXT]](s16), %bb.1, [[C2]](s16), %bb.2
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16) ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
Show All 18 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -O0 -mtriple=aarch64-apple-ios -verify-machineinstrs -global-isel -stop-after=legalizer %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=aarch64-apple-ios -verify-machineinstrs -global-isel -stop-after=legalizer %s -o - | FileCheck %s
@_ZTIi = external global ptr @_ZTIi = external global ptr
declare i32 @foo(i32) declare i32 @foo(i32)
declare i32 @__gxx_personality_v0(...) declare i32 @__gxx_personality_v0(...)
declare i32 @llvm.eh.typeid.for(ptr) declare i32 @llvm.eh.typeid.for(ptr)
declare void @_Unwind_Resume(ptr) declare void @_Unwind_Resume(ptr)
define void @bar() personality ptr @__gxx_personality_v0 { define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: name: bar ; CHECK-LABEL: name: bar
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ehselector.slot
; CHECK-NEXT: G_INVOKE_REGION_START ; CHECK-NEXT: G_INVOKE_REGION_START
; CHECK-NEXT: EH_LABEL <mcsymbol > ; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: $w0 = COPY [[C]](s32) ; CHECK-NEXT: $w0 = COPY [[C]](s32)
; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0 ; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: EH_LABEL <mcsymbol > ; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_BR %bb.3 ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.cleanup (landing-pad): ; CHECK-NEXT: bb.2.cleanup (landing-pad):
; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: liveins: $x0, $x1 ; CHECK-NEXT: liveins: $x0, $x1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: EH_LABEL <mcsymbol > ; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0) ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64) ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[PTRTOINT]](s64)
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
; CHECK-NEXT: G_STORE [[COPY]](p0), [[FRAME_INDEX]](p0) :: (store (p0) into %ir.exn.slot) ; CHECK-NEXT: G_STORE [[COPY]](p0), [[FRAME_INDEX]](p0) :: (store (p0) into %ir.exn.slot)
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.ehselector.slot
; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.ehselector.slot) ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.ehselector.slot)
; CHECK-NEXT: G_BR %bb.4 ; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.continue: ; CHECK-NEXT: bb.3.continue:
; CHECK-NEXT: RET_ReallyLR ; CHECK-NEXT: RET_ReallyLR
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.eh.resume: ; CHECK-NEXT: bb.4.eh.resume:
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (p0) from %ir.exn.slot) ; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.exn.slot
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.exn.slot)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[LOAD]](p0) ; CHECK-NEXT: $x0 = COPY [[LOAD]](p0)
; CHECK-NEXT: BL @_Unwind_Resume, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0 ; CHECK-NEXT: BL @_Unwind_Resume, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap) ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
%exn.slot = alloca ptr %exn.slot = alloca ptr
%ehselector.slot = alloca i32 %ehselector.slot = alloca i32
%1 = invoke i32 @foo(i32 42) to label %continue unwind label %cleanup %1 = invoke i32 @foo(i32 42) to label %continue unwind label %cleanup
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llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll

Show All 13 Lines
; Some of the instructions in entry block are dead after this pass so don't ; Some of the instructions in entry block are dead after this pass so don't
; strictly need to be checked for. ; strictly need to be checked for.
define i32 @foo() { define i32 @foo() {
; CHECK-LABEL: name: foo ; CHECK-LABEL: name: foo
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3 ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @var1) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]] ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
; CHECK-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ICMP]], [[C3]] ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.3
; CHECK-NEXT: G_BR %bb.2 ; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then: ; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2 ; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: G_STORE [[C4]](s32), [[GV3]](p0) :: (store (s32) into @var2) ; CHECK-NEXT: G_STORE [[C4]](s32), [[GV3]](p0) :: (store (s32) into @var2)
; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: G_STORE [[C5]](s32), [[GV]](p0) :: (store (s32) into @var1) ; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
; CHECK-NEXT: [[GV4:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3 ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV4]](p0) :: (store (s32) into @var1)
; CHECK-NEXT: G_STORE [[C4]](s32), [[GV4]](p0) :: (store (s32) into @var3) ; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
; CHECK-NEXT: G_STORE [[C5]](s32), [[GV]](p0) :: (store (s32) into @var1) ; CHECK-NEXT: G_STORE [[C4]](s32), [[GV5]](p0) :: (store (s32) into @var3)
; CHECK-NEXT: G_STORE [[C5]](s32), [[GV4]](p0) :: (store (s32) into @var1)
; CHECK-NEXT: G_BR %bb.3 ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end: ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: $w0 = COPY [[C6]](s32) ; CHECK-NEXT: $w0 = COPY [[C6]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0 ; CHECK-NEXT: RET_ReallyLR implicit $w0
entry: entry:
%0 = load i32, ptr @var1, align 4 %0 = load i32, ptr @var1, align 4
%cmp = icmp eq i32 %0, 1 %cmp = icmp eq i32 %0, 1
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
Show All 14 Lines
; below a physreg write, clobbering it (TLS accesses on Darwin need a function call). ; below a physreg write, clobbering it (TLS accesses on Darwin need a function call).
; For now, we check we don't localize at all. We could in theory make sure that ; For now, we check we don't localize at all. We could in theory make sure that
; we don't localize into the middle of a call sequence instead. ; we don't localize into the middle of a call sequence instead.
define i32 @darwin_tls() { define i32 @darwin_tls() {
; CHECK-LABEL: name: darwin_tls ; CHECK-LABEL: name: darwin_tls
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @tls_gv ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @tls_gv
; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2 ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1 ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C1]] ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C1]]
; CHECK-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ICMP]], [[C1]] ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.3
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.3
; CHECK-NEXT: G_BR %bb.2 ; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then: ; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:gpr(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @tls_gv) ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load (s32) from @tls_gv)
; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2 ; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: G_STORE [[LOAD1]](s32), [[GV3]](p0) :: (store (s32) into @var2) ; CHECK-NEXT: G_STORE [[LOAD1]](s32), [[GV3]](p0) :: (store (s32) into @var2)
; CHECK-NEXT: G_BR %bb.3 ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end: ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: $w0 = COPY [[C2]](s32) ; CHECK-NEXT: $w0 = COPY [[C2]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0 ; CHECK-NEXT: RET_ReallyLR implicit $w0
entry: entry:
%0 = load i32, ptr @var1, align 4 %0 = load i32, ptr @var1, align 4
%cmp = icmp eq i32 %0, 1 %cmp = icmp eq i32 %0, 1
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
%tls = load i32, ptr @tls_gv, align 4 %tls = load i32, ptr @tls_gv, align 4
store i32 %tls, ptr @var2, align 4 store i32 %tls, ptr @var2, align 4
br label %if.end br label %if.end
if.end: if.end:
ret i32 0 ret i32 0
} }
define i32 @imm_cost_too_large_cost_of_2() { define i32 @imm_cost_too_large_cost_of_2() {
; CHECK-LABEL: name: imm_cost_too_large_cost_of_2 ; CHECK-LABEL: name: imm_cost_too_large_cost_of_2
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 -2228259 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2228259
; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3 ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1 ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s32) from @var1)
; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]] ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]
; CHECK-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ICMP]], [[C2]] ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.4
; CHECK-NEXT: G_BR %bb.2 ; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then: ; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2 ; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2
; CHECK-NEXT: G_STORE [[C]](s32), [[GV3]](p0) :: (store (s32) into @var2) ; CHECK-NEXT: G_STORE [[C]](s32), [[GV3]](p0) :: (store (s32) into @var2)
; CHECK-NEXT: G_BR %bb.3 ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2: ; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1 ; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1
; CHECK-NEXT: G_STORE [[C]](s32), [[GV4]](p0) :: (store (s32) into @var1) ; CHECK-NEXT: G_STORE [[C]](s32), [[GV4]](p0) :: (store (s32) into @var1)
; CHECK-NEXT: G_BR %bb.4 ; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end: ; CHECK-NEXT: bb.4.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3 ; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3
; CHECK-NEXT: G_STORE [[C]](s32), [[GV5]](p0) :: (store (s32) into @var3) ; CHECK-NEXT: G_STORE [[C]](s32), [[GV5]](p0) :: (store (s32) into @var3)
; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: $w0 = COPY [[C3]](s32) ; CHECK-NEXT: $w0 = COPY [[C3]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0 ; CHECK-NEXT: RET_ReallyLR implicit $w0
entry: entry:
%0 = load i32, ptr @var1, align 4 %0 = load i32, ptr @var1, align 4
%cst1 = bitcast i32 -2228259 to i32 %cst1 = bitcast i32 -2228259 to i32
%cmp = icmp eq i32 %0, 1 %cmp = icmp eq i32 %0, 1
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
Show All 10 Linesif.end:
ret i32 0 ret i32 0
} }
define i64 @imm_cost_too_large_cost_of_4() { define i64 @imm_cost_too_large_cost_of_4() {
; CHECK-LABEL: name: imm_cost_too_large_cost_of_4 ; CHECK-LABEL: name: imm_cost_too_large_cost_of_4
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 -2228259 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2228259
; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2_64 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3_64 ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1_64 ; CHECK-NEXT: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s64) from @var1_64, align 4) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV2]](p0) :: (dereferenceable load (s64) from @var1_64, align 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[LOAD]](s64), [[C2]] ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s64), [[C2]]
; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
; CHECK-NEXT: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[ICMP]], [[C3]]
; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.4
; CHECK-NEXT: G_BR %bb.2 ; CHECK-NEXT: G_BR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.then: ; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2_64 ; CHECK-NEXT: [[GV3:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2_64
; CHECK-NEXT: G_STORE [[C]](s64), [[GV3]](p0) :: (store (s64) into @var2_64) ; CHECK-NEXT: G_STORE [[C]](s64), [[GV3]](p0) :: (store (s64) into @var2_64)
; CHECK-NEXT: G_BR %bb.3 ; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.then2: ; CHECK-NEXT: bb.3.if.then2:
; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV4:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1_64 ; CHECK-NEXT: [[GV4:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1_64
; CHECK-NEXT: G_STORE [[C]](s64), [[GV4]](p0) :: (store (s64) into @var1_64) ; CHECK-NEXT: G_STORE [[C]](s64), [[GV4]](p0) :: (store (s64) into @var1_64)
; CHECK-NEXT: G_BR %bb.4 ; CHECK-NEXT: G_BR %bb.4
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.if.end: ; CHECK-NEXT: bb.4.if.end:
; CHECK-NEXT: [[GV5:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3_64 ; CHECK-NEXT: [[GV5:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var3_64
; CHECK-NEXT: G_STORE [[C]](s64), [[GV5]](p0) :: (store (s64) into @var3_64) ; CHECK-NEXT: G_STORE [[C]](s64), [[GV5]](p0) :: (store (s64) into @var3_64)
; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: $x0 = COPY [[C4]](s64) ; CHECK-NEXT: $x0 = COPY [[C3]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0 ; CHECK-NEXT: RET_ReallyLR implicit $x0
entry: entry:
%0 = load i64, ptr @var1_64, align 4 %0 = load i64, ptr @var1_64, align 4
%cst1 = bitcast i64 -2228259 to i64 %cst1 = bitcast i64 -2228259 to i64
%cmp = icmp eq i64 %0, 1 %cmp = icmp eq i64 %0, 1
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
Show All 15 Lines

llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir

  • This file was deleted.
# RUN: llc -O0 -mtriple aarch64-apple-ios %s -global-isel -start-after regbankselect \
# RUN: -stop-before instruction-select -o - | FileCheck --check-prefix=CHECK --check-prefix=OPTNONE %s
# RUN: llc -mtriple aarch64-apple-ios %s -global-isel -start-after regbankselect \
# RUN: -stop-before instruction-select -o - | FileCheck --check-prefix=CHECK --check-prefix=OPT %s
#
# Check that we are only running the localizer at O0 and that it runs
# between the regbankselect pass and the instruction-select.
# Moreover, check that it does what we expect.
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-apple-ios"
define float @foo(float %arg, i1 %cond) {
br i1 %cond, label %true, label %false
true: ; preds = %0
br label %end
false: ; preds = %0
br label %end
end: ; preds = %false, %true
%val = phi float [ 1.000000e+00, %true ], [ 2.000000e+00, %false ]
%res = fadd float %arg, %val
ret float %res
}
...
---
# CHECK-LABEL: name: foo
name: foo
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 5, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 6, class: gpr, preferred-register: '' }
# The localizer will create two new values to materialize the constants.
# OPTNONE-NEXT: - { id: 7, class: fpr, preferred-register: '' }
# OPTNONE-NEXT: - { id: 8, class: fpr, preferred-register: '' }
- { id: 0, class: fpr }
- { id: 1, class: gpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
- { id: 5, class: fpr }
- { id: 6, class: gpr }
# First block remains untouched
# CHECK: body
# CHECK: %4:fpr(s32) = G_FCONSTANT float 1.000000e+00
# CHECK: %5:fpr(s32) = G_FCONSTANT float 2.000000e+00
# Second block will get the constant 1.0 when the localizer is enabled.
# CHECK: bb.1.{{[a-zA-Z0-9]+}}:
# OPT: [[FONE:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
# OPTNONE: [[FONE:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
# CHECK: G_BR %bb.3
# Thrid block will get the constant 2.0 when the localizer is enabled.
# CHECK: bb.2.{{[a-zA-Z0-9]+}}:
# OPT: [[FTWO:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00
# OPTNONE: [[FTWO:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00
# CHECK: bb.3.end
# OPTNONE: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1, [[FTWO]](s32), %bb.2
# OPT: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1, [[FTWO]](s32), %bb.2
# CHECK-NEXT: G_FADD %0, %2
body: |
bb.0 (%ir-block.0):
liveins: $s0, $w0
%0(s32) = COPY $s0
%6(s32) = COPY $w0
%1(s1) = G_TRUNC %6
%4(s32) = G_FCONSTANT float 1.000000e+00
%5(s32) = G_FCONSTANT float 2.000000e+00
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
bb.1.true:
G_BR %bb.3
bb.2.false:
bb.3.end:
%2(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2
%3(s32) = G_FADD %0, %2
$s0 = COPY %3(s32)
RET_ReallyLR implicit $s0
...

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir

Show All 15 Lines
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; LOWER-LABEL: name: swap_sextinreg_lhs ; LOWER-LABEL: name: swap_sextinreg_lhs
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %reg:_(s64) = COPY $x0 ; LOWER-NEXT: {{ $}}
; LOWER: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8 ; LOWER-NEXT: %reg:_(s64) = COPY $x0
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_sextinreg_lhs ; SELECT-LABEL: name: swap_sextinreg_lhs
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %reg:gpr64all = COPY $x0 ; SELECT-NEXT: {{ $}}
; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32 ; SELECT-NEXT: %reg:gpr64all = COPY $x0
; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32
; SELECT: %cmp_rhs:gpr64sp = COPY $x1 ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0 %reg:_(s64) = COPY $x0
%cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8 %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: dont_swap_more_than_one_use name: dont_swap_more_than_one_use
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; The LHS of the compare is used in an add, and a second compare. Don't ; The LHS of the compare is used in an add, and a second compare. Don't
; swap, since we don't gain any folding opportunities here. ; swap, since we don't gain any folding opportunities here.
; LOWER-LABEL: name: dont_swap_more_than_one_use ; LOWER-LABEL: name: dont_swap_more_than_one_use
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %reg0:_(s64) = COPY $x0 ; LOWER-NEXT: {{ $}}
; LOWER: %cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8 ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
; LOWER: %add:_(s64) = G_ADD %cmp_lhs, %reg0 ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8
; LOWER: %cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add ; LOWER-NEXT: %add:_(s64) = G_ADD %cmp_lhs, %reg0
; LOWER: $w0 = COPY %cmp2(s32) ; LOWER-NEXT: %cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp2(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_more_than_one_use ; SELECT-LABEL: name: dont_swap_more_than_one_use
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %reg0:gpr64 = COPY $x0 ; SELECT-NEXT: {{ $}}
; SELECT: %cmp_lhs:gpr64 = SBFMXri %reg0, 0, 7 ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
; SELECT: %add:gpr64 = ADDXrr %cmp_lhs, %reg0 ; SELECT-NEXT: %cmp_lhs:gpr64 = SBFMXri %reg0, 0, 7
; SELECT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %add, implicit-def $nzcv ; SELECT-NEXT: %add:gpr64 = ADDXrr %cmp_lhs, %reg0
; SELECT: %cmp2:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %add, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp2 ; SELECT-NEXT: %cmp2:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp2
; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg0:_(s64) = COPY $x0 %reg0:_(s64) = COPY $x0
%cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8 %cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8
%reg1:_(s64) = COPY $x1 %reg1:_(s64) = COPY $x1
%cmp1:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %reg1 %cmp1:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %reg1
%add:_(s64) = G_ADD %cmp_lhs(s64), %reg0 %add:_(s64) = G_ADD %cmp_lhs(s64), %reg0
%cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add %cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add
$w0 = COPY %cmp2(s32) $w0 = COPY %cmp2(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: dont_swap_legal_arith_immed_on_rhs name: dont_swap_legal_arith_immed_on_rhs
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; Arithmetic immediates can be folded into compares. If we have one, then ; Arithmetic immediates can be folded into compares. If we have one, then
; don't bother changing anything. ; don't bother changing anything.
; LOWER-LABEL: name: dont_swap_legal_arith_immed_on_rhs ; LOWER-LABEL: name: dont_swap_legal_arith_immed_on_rhs
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %reg:_(s64) = COPY $x0 ; LOWER-NEXT: {{ $}}
; LOWER: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8 ; LOWER-NEXT: %reg:_(s64) = COPY $x0
; LOWER: %cmp_rhs:_(s64) = G_CONSTANT i64 12 ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
; LOWER: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: %cmp_rhs:_(s64) = G_CONSTANT i64 12
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_legal_arith_immed_on_rhs ; SELECT-LABEL: name: dont_swap_legal_arith_immed_on_rhs
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %reg:gpr64 = COPY $x0 ; SELECT-NEXT: {{ $}}
; SELECT: %cmp_lhs:gpr64common = SBFMXri %reg, 0, 7 ; SELECT-NEXT: %reg:gpr64 = COPY $x0
; SELECT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %cmp_lhs, 12, 0, implicit-def $nzcv ; SELECT-NEXT: %cmp_lhs:gpr64common = SBFMXri %reg, 0, 7
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv ; SELECT-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %cmp_lhs, 12, 0, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0 %reg:_(s64) = COPY $x0
%cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8 %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
%cmp_rhs:_(s64) = G_CONSTANT i64 12 %cmp_rhs:_(s64) = G_CONSTANT i64 12
%cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: swap_non_arith_immed_on_rhs name: swap_non_arith_immed_on_rhs
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; If we have a non-arithmetic immediate on the rhs, then we can swap to get ; If we have a non-arithmetic immediate on the rhs, then we can swap to get
; a guaranteed folding opportunity. ; a guaranteed folding opportunity.
; LOWER-LABEL: name: swap_non_arith_immed_on_rhs ; LOWER-LABEL: name: swap_non_arith_immed_on_rhs
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %reg:_(s64) = COPY $x0 ; LOWER-NEXT: {{ $}}
; LOWER: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8 ; LOWER-NEXT: %reg:_(s64) = COPY $x0
; LOWER: %cmp_rhs:_(s64) = G_CONSTANT i64 1234567 ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: %cmp_rhs:_(s64) = G_CONSTANT i64 1234567
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_non_arith_immed_on_rhs ; SELECT-LABEL: name: swap_non_arith_immed_on_rhs
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %reg:gpr64all = COPY $x0 ; SELECT-NEXT: {{ $}}
; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32 ; SELECT-NEXT: %reg:gpr64all = COPY $x0
; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32
; SELECT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234567 ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
; SELECT: %cmp_rhs:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 ; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234567
; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv ; SELECT-NEXT: %cmp_rhs:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg:_(s64) = COPY $x0 %reg:_(s64) = COPY $x0
%cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8 %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
%cmp_rhs:_(s64) = G_CONSTANT i64 1234567 %cmp_rhs:_(s64) = G_CONSTANT i64 1234567
%cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: swap_and_lhs_0xFF name: swap_and_lhs_0xFF
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; LOWER-LABEL: name: swap_and_lhs_0xFF ; LOWER-LABEL: name: swap_and_lhs_0xFF
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: {{ $}}
; LOWER: %and_lhs:_(s64) = COPY $x0 ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: %cst:_(s64) = G_CONSTANT i64 255 ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
; LOWER: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 255
; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_and_lhs_0xFF ; SELECT-LABEL: name: swap_and_lhs_0xFF
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %cmp_rhs:gpr64sp = COPY $x1 ; SELECT-NEXT: {{ $}}
; SELECT: %and_lhs:gpr64all = COPY $x0 ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32 ; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 0, implicit-def $nzcv ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 0, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%and_lhs:_(s64) = COPY $x0 %and_lhs:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 255 %cst:_(s64) = G_CONSTANT i64 255
%cmp_lhs:_(s64) = G_AND %and_lhs, %cst(s64) %cmp_lhs:_(s64) = G_AND %and_lhs, %cst(s64)
%cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: swap_and_lhs_0xFFFF name: swap_and_lhs_0xFFFF
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; LOWER-LABEL: name: swap_and_lhs_0xFFFF ; LOWER-LABEL: name: swap_and_lhs_0xFFFF
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: {{ $}}
; LOWER: %cst:_(s64) = G_CONSTANT i64 65535 ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: %and_lhs:_(s64) = COPY $x0 ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 65535
; LOWER: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_and_lhs_0xFFFF ; SELECT-LABEL: name: swap_and_lhs_0xFFFF
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %cmp_rhs:gpr64sp = COPY $x1 ; SELECT-NEXT: {{ $}}
; SELECT: %and_lhs:gpr64all = COPY $x0 ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32 ; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 8, implicit-def $nzcv ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 8, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%cst:_(s64) = G_CONSTANT i64 65535 %cst:_(s64) = G_CONSTANT i64 65535
%and_lhs:_(s64) = COPY $x0 %and_lhs:_(s64) = COPY $x0
%cmp_lhs:_(s64) = G_AND %and_lhs, %cst(s64) %cmp_lhs:_(s64) = G_AND %and_lhs, %cst(s64)
%cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: swap_and_lhs_0xFFFFFFFF name: swap_and_lhs_0xFFFFFFFF
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; LOWER-LABEL: name: swap_and_lhs_0xFFFFFFFF ; LOWER-LABEL: name: swap_and_lhs_0xFFFFFFFF
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: {{ $}}
; LOWER: %and_lhs:_(s64) = COPY $x0 ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: %cst:_(s64) = G_CONSTANT i64 4294967295 ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
; LOWER: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 4294967295
; LOWER: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_and_lhs_0xFFFFFFFF ; SELECT-LABEL: name: swap_and_lhs_0xFFFFFFFF
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %cmp_rhs:gpr64sp = COPY $x1 ; SELECT-NEXT: {{ $}}
; SELECT: %and_lhs:gpr64all = COPY $x0 ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32 ; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 16, implicit-def $nzcv ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 16, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%and_lhs:_(s64) = COPY $x0 %and_lhs:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 4294967295 %cst:_(s64) = G_CONSTANT i64 4294967295
%cmp_lhs:_(s64) = G_AND %and_lhs, %cst(s64) %cmp_lhs:_(s64) = G_AND %and_lhs, %cst(s64)
%cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: dont_swap_and_lhs_wrong_mask name: dont_swap_and_lhs_wrong_mask
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; 7 isn't an extend mask for G_AND, so there's no folding opportunities ; 7 isn't an extend mask for G_AND, so there's no folding opportunities
; here. ; here.
; ;
; LOWER-LABEL: name: dont_swap_and_lhs_wrong_mask ; LOWER-LABEL: name: dont_swap_and_lhs_wrong_mask
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: {{ $}}
; LOWER: %and_lhs:_(s64) = COPY $x0 ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: %not_an_extend_mask:_(s64) = G_CONSTANT i64 7 ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
; LOWER: %cmp_lhs:_(s64) = G_AND %and_lhs, %not_an_extend_mask ; LOWER-NEXT: %not_an_extend_mask:_(s64) = G_CONSTANT i64 7
; LOWER: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %not_an_extend_mask
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_and_lhs_wrong_mask ; SELECT-LABEL: name: dont_swap_and_lhs_wrong_mask
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %cmp_rhs:gpr64 = COPY $x1 ; SELECT-NEXT: {{ $}}
; SELECT: %and_lhs:gpr64 = COPY $x0 ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
; SELECT: %cmp_lhs:gpr64common = ANDXri %and_lhs, 4098 ; SELECT-NEXT: %and_lhs:gpr64 = COPY $x0
; SELECT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv ; SELECT-NEXT: %cmp_lhs:gpr64common = ANDXri %and_lhs, 4098
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%and_lhs:_(s64) = COPY $x0 %and_lhs:_(s64) = COPY $x0
%not_an_extend_mask:_(s64) = G_CONSTANT i64 7 %not_an_extend_mask:_(s64) = G_CONSTANT i64 7
%cmp_lhs:_(s64) = G_AND %and_lhs, %not_an_extend_mask(s64) %cmp_lhs:_(s64) = G_AND %and_lhs, %not_an_extend_mask(s64)
%cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: swap_shl_lhs name: swap_shl_lhs
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; LOWER-LABEL: name: swap_shl_lhs ; LOWER-LABEL: name: swap_shl_lhs
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: {{ $}}
; LOWER: %shl_lhs:_(s64) = COPY $x0 ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: %cst:_(s64) = G_CONSTANT i64 1 ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
; LOWER: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %cst(s64) ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
; LOWER: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_shl_lhs ; SELECT-LABEL: name: swap_shl_lhs
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %cmp_rhs:gpr64 = COPY $x1 ; SELECT-NEXT: {{ $}}
; SELECT: %shl_lhs:gpr64 = COPY $x0 ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
; SELECT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %shl_lhs, 1, implicit-def $nzcv ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %shl_lhs, 1, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%shl_lhs:_(s64) = COPY $x0 %shl_lhs:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 1 %cst:_(s64) = G_CONSTANT i64 1
%cmp_lhs:_(s64) = G_SHL %shl_lhs, %cst(s64) %cmp_lhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
%cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: swap_ashr_lhs name: swap_ashr_lhs
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; LOWER-LABEL: name: swap_ashr_lhs ; LOWER-LABEL: name: swap_ashr_lhs
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: {{ $}}
; LOWER: %ashr_lhs:_(s64) = COPY $x0 ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: %cst:_(s64) = G_CONSTANT i64 1 ; LOWER-NEXT: %ashr_lhs:_(s64) = COPY $x0
; LOWER: %cmp_lhs:_(s64) = G_ASHR %ashr_lhs, %cst(s64) ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
; LOWER: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: %cmp_lhs:_(s64) = G_ASHR %ashr_lhs, %cst(s64)
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_ashr_lhs ; SELECT-LABEL: name: swap_ashr_lhs
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %cmp_rhs:gpr64 = COPY $x1 ; SELECT-NEXT: {{ $}}
; SELECT: %ashr_lhs:gpr64 = COPY $x0 ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
; SELECT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %ashr_lhs, 129, implicit-def $nzcv ; SELECT-NEXT: %ashr_lhs:gpr64 = COPY $x0
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %ashr_lhs, 129, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%ashr_lhs:_(s64) = COPY $x0 %ashr_lhs:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 1 %cst:_(s64) = G_CONSTANT i64 1
%cmp_lhs:_(s64) = G_ASHR %ashr_lhs, %cst(s64) %cmp_lhs:_(s64) = G_ASHR %ashr_lhs, %cst(s64)
%cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: swap_lshr_lhs name: swap_lshr_lhs
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; LOWER-LABEL: name: swap_lshr_lhs ; LOWER-LABEL: name: swap_lshr_lhs
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: {{ $}}
; LOWER: %lshr_lhs:_(s64) = COPY $x0 ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: %cst:_(s64) = G_CONSTANT i64 1 ; LOWER-NEXT: %lshr_lhs:_(s64) = COPY $x0
; LOWER: %cmp_lhs:_(s64) = G_LSHR %lshr_lhs, %cst(s64) ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
; LOWER: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: %cmp_lhs:_(s64) = G_LSHR %lshr_lhs, %cst(s64)
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_lshr_lhs ; SELECT-LABEL: name: swap_lshr_lhs
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %cmp_rhs:gpr64 = COPY $x1 ; SELECT-NEXT: {{ $}}
; SELECT: %lshr_lhs:gpr64 = COPY $x0 ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
; SELECT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %lshr_lhs, 65, implicit-def $nzcv ; SELECT-NEXT: %lshr_lhs:gpr64 = COPY $x0
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %lshr_lhs, 65, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%lshr_lhs:_(s64) = COPY $x0 %lshr_lhs:_(s64) = COPY $x0
%cst:_(s64) = G_CONSTANT i64 1 %cst:_(s64) = G_CONSTANT i64 1
%cmp_lhs:_(s64) = G_LSHR %lshr_lhs, %cst(s64) %cmp_lhs:_(s64) = G_LSHR %lshr_lhs, %cst(s64)
%cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: dont_swap_shift_s64_cst_too_large name: dont_swap_shift_s64_cst_too_large
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; Constant for the shift must be <= 63. ; Constant for the shift must be <= 63.
; LOWER-LABEL: name: dont_swap_shift_s64_cst_too_large ; LOWER-LABEL: name: dont_swap_shift_s64_cst_too_large
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: {{ $}}
; LOWER: %shl_lhs:_(s64) = COPY $x0 ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: %too_large:_(s64) = G_CONSTANT i64 64 ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
; LOWER: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %too_large(s64) ; LOWER-NEXT: %too_large:_(s64) = G_CONSTANT i64 64
; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %too_large(s64)
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_shift_s64_cst_too_large ; SELECT-LABEL: name: dont_swap_shift_s64_cst_too_large
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %cmp_rhs:gpr64 = COPY $x1 ; SELECT-NEXT: {{ $}}
; SELECT: %shl_lhs:gpr64 = COPY $x0 ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
; SELECT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 64 ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0
; SELECT: %too_large:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 ; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 64
; SELECT: %cmp_lhs:gpr64 = LSLVXr %shl_lhs, %too_large ; SELECT-NEXT: %too_large:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; SELECT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv ; SELECT-NEXT: %cmp_lhs:gpr64 = LSLVXr %shl_lhs, %too_large
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%shl_lhs:_(s64) = COPY $x0 %shl_lhs:_(s64) = COPY $x0
%too_large:_(s64) = G_CONSTANT i64 64 %too_large:_(s64) = G_CONSTANT i64 64
%cmp_lhs:_(s64) = G_SHL %shl_lhs, %too_large(s64) %cmp_lhs:_(s64) = G_SHL %shl_lhs, %too_large(s64)
%cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
name: dont_swap_shift_s32_cst_too_large name: dont_swap_shift_s32_cst_too_large
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $w0, $w1 liveins: $w0, $w1
; Constant for the shift must be <= 32. ; Constant for the shift must be <= 32.
; LOWER-LABEL: name: dont_swap_shift_s32_cst_too_large ; LOWER-LABEL: name: dont_swap_shift_s32_cst_too_large
; LOWER: liveins: $w0, $w1 ; LOWER: liveins: $w0, $w1
; LOWER: %cmp_rhs:_(s32) = COPY $w1 ; LOWER-NEXT: {{ $}}
; LOWER: %shl_lhs:_(s32) = COPY $w0 ; LOWER-NEXT: %cmp_rhs:_(s32) = COPY $w1
; LOWER: %cst:_(s32) = G_CONSTANT i32 32 ; LOWER-NEXT: %shl_lhs:_(s32) = COPY $w0
; LOWER: %cmp_lhs:_(s32) = G_SHL %shl_lhs, %cst(s32) ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 32
; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s32), %cmp_rhs ; LOWER-NEXT: %cmp_lhs:_(s32) = G_SHL %shl_lhs, %cst(s32)
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s32), %cmp_rhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_shift_s32_cst_too_large ; SELECT-LABEL: name: dont_swap_shift_s32_cst_too_large
; SELECT: liveins: $w0, $w1 ; SELECT: liveins: $w0, $w1
; SELECT: %cmp_rhs:gpr32 = COPY $w1 ; SELECT-NEXT: {{ $}}
; SELECT: %shl_lhs:gpr32 = COPY $w0 ; SELECT-NEXT: %cmp_rhs:gpr32 = COPY $w1
; SELECT: %cst:gpr32 = MOVi32imm 32 ; SELECT-NEXT: %shl_lhs:gpr32 = COPY $w0
; SELECT: %cmp_lhs:gpr32 = LSLVWr %shl_lhs, %cst ; SELECT-NEXT: %cst:gpr32 = MOVi32imm 32
; SELECT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv ; SELECT-NEXT: %cmp_lhs:gpr32 = LSLVWr %shl_lhs, %cst
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; SELECT-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s32) = COPY $w1 %cmp_rhs:_(s32) = COPY $w1
%shl_lhs:_(s32) = COPY $w0 %shl_lhs:_(s32) = COPY $w0
%cst:_(s32) = G_CONSTANT i32 32 %cst:_(s32) = G_CONSTANT i32 32
%cmp_lhs:_(s32) = G_SHL %shl_lhs, %cst(s32) %cmp_lhs:_(s32) = G_SHL %shl_lhs, %cst(s32)
%cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s32), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s32), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
Show All 9 Lines bb.0.entry:
liveins: $x0, $x1 liveins: $x0, $x1
; No reason to swap a CMN on the LHS when it won't introduce a constant ; No reason to swap a CMN on the LHS when it won't introduce a constant
; folding opportunity. We can recognise CMNs on the LHS and RHS, so there's ; folding opportunity. We can recognise CMNs on the LHS and RHS, so there's
; nothing to gain here. ; nothing to gain here.
; LOWER-LABEL: name: dont_swap_cmn_lhs_no_folding_opportunities ; LOWER-LABEL: name: dont_swap_cmn_lhs_no_folding_opportunities
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: {{ $}}
; LOWER: %sub_rhs:_(s64) = COPY $x0 ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: %zero:_(s64) = G_CONSTANT i64 0 ; LOWER-NEXT: %sub_rhs:_(s64) = COPY $x0
; LOWER: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; LOWER: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_cmn_lhs_no_folding_opportunities ; SELECT-LABEL: name: dont_swap_cmn_lhs_no_folding_opportunities
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %cmp_rhs:gpr64 = COPY $x1 ; SELECT-NEXT: {{ $}}
; SELECT: %sub_rhs:gpr64 = COPY $x0 ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
; SELECT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %sub_rhs, %cmp_rhs, implicit-def $nzcv ; SELECT-NEXT: %sub_rhs:gpr64 = COPY $x0
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv ; SELECT-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %sub_rhs, %cmp_rhs, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%sub_rhs:_(s64) = COPY $x0 %sub_rhs:_(s64) = COPY $x0
%zero:_(s64) = G_CONSTANT i64 0 %zero:_(s64) = G_CONSTANT i64 0
%cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
%cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
Show All 9 Lines bb.0.entry:
liveins: $x0, $x1 liveins: $x0, $x1
; Swap when we can see a constant folding opportunity through the sub on ; Swap when we can see a constant folding opportunity through the sub on
; the LHS. ; the LHS.
; LOWER-LABEL: name: swap_cmn_lhs ; LOWER-LABEL: name: swap_cmn_lhs
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %cmp_rhs:_(s64) = COPY $x1 ; LOWER-NEXT: {{ $}}
; LOWER: %shl_lhs:_(s64) = COPY $x0 ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
; LOWER: %zero:_(s64) = G_CONSTANT i64 0 ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
; LOWER: %cst:_(s64) = G_CONSTANT i64 63 ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; LOWER: %sub_rhs:_(s64) = G_SHL %shl_lhs, %cst(s64) ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 63
; LOWER: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs ; LOWER-NEXT: %sub_rhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
; LOWER: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_rhs(s64), %cmp_lhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_cmn_lhs ; SELECT-LABEL: name: swap_cmn_lhs
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %cmp_rhs:gpr64 = COPY $x1 ; SELECT-NEXT: {{ $}}
; SELECT: %shl_lhs:gpr64 = COPY $x0 ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
; SELECT: [[ADDSXrs:%[0-9]+]]:gpr64 = ADDSXrs %cmp_rhs, %shl_lhs, 63, implicit-def $nzcv ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv ; SELECT-NEXT: [[ADDSXrs:%[0-9]+]]:gpr64 = ADDSXrs %cmp_rhs, %shl_lhs, 63, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%cmp_rhs:_(s64) = COPY $x1 %cmp_rhs:_(s64) = COPY $x1
%shl_lhs:_(s64) = COPY $x0 %shl_lhs:_(s64) = COPY $x0
%zero:_(s64) = G_CONSTANT i64 0 %zero:_(s64) = G_CONSTANT i64 0
%cst:_(s64) = G_CONSTANT i64 63 %cst:_(s64) = G_CONSTANT i64 63
%sub_rhs:_(s64) = G_SHL %shl_lhs, %cst(s64) %sub_rhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
%cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
Show All 13 Lines bb.0.entry:
; Don't swap when the RHS's subtract offers a better constant folding ; Don't swap when the RHS's subtract offers a better constant folding
; opportunity than the LHS's subtract. ; opportunity than the LHS's subtract.
; ;
; In this case, the RHS has a supported extend, plus a shift with a constant ; In this case, the RHS has a supported extend, plus a shift with a constant
; <= 4. ; <= 4.
; LOWER-LABEL: name: dont_swap_cmn_lhs_when_rhs_more_profitable ; LOWER-LABEL: name: dont_swap_cmn_lhs_when_rhs_more_profitable
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %zero:_(s64) = G_CONSTANT i64 0 ; LOWER-NEXT: {{ $}}
; LOWER: %reg0:_(s64) = COPY $x0 ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
; LOWER: %shl_cst:_(s64) = G_CONSTANT i64 63 ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
; LOWER: %shl:_(s64) = G_SHL %reg0, %shl_cst(s64) ; LOWER-NEXT: %shl_cst:_(s64) = G_CONSTANT i64 63
; LOWER: %cmp_lhs:_(s64) = G_SUB %zero, %shl ; LOWER-NEXT: %shl:_(s64) = G_SHL %reg0, %shl_cst(s64)
; LOWER: %reg1:_(s64) = COPY $x1 ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %shl
; LOWER: %sext_in_reg:_(s64) = G_SEXT_INREG %reg1, 1 ; LOWER-NEXT: %reg1:_(s64) = COPY $x1
; LOWER: %ashr_cst:_(s64) = G_CONSTANT i64 3 ; LOWER-NEXT: %sext_in_reg:_(s64) = G_SEXT_INREG %reg1, 1
; LOWER: %ashr:_(s64) = G_ASHR %sext_in_reg, %ashr_cst(s64) ; LOWER-NEXT: %ashr_cst:_(s64) = G_CONSTANT i64 3
; LOWER: %cmp_rhs:_(s64) = G_SUB %zero, %ashr ; LOWER-NEXT: %ashr:_(s64) = G_ASHR %sext_in_reg, %ashr_cst(s64)
; LOWER: %cmp:_(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: %cmp_rhs:_(s64) = G_SUB %zero, %ashr
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_cmn_lhs_when_rhs_more_profitable ; SELECT-LABEL: name: dont_swap_cmn_lhs_when_rhs_more_profitable
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %reg0:gpr64 = COPY $x0 ; SELECT-NEXT: {{ $}}
; SELECT: %shl:gpr64 = UBFMXri %reg0, 1, 0 ; SELECT-NEXT: %zero:gpr64 = COPY $xzr
; SELECT: %zero:gpr64 = COPY $xzr ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
; SELECT: %reg1:gpr64 = COPY $x1 ; SELECT-NEXT: %shl:gpr64 = UBFMXri %reg0, 1, 0
; SELECT: %sext_in_reg:gpr64 = SBFMXri %reg1, 0, 0 ; SELECT-NEXT: %reg1:gpr64 = COPY $x1
; SELECT: %cmp_rhs:gpr64 = SUBSXrs %zero, %sext_in_reg, 131, implicit-def $nzcv ; SELECT-NEXT: %sext_in_reg:gpr64 = SBFMXri %reg1, 0, 0
; SELECT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %shl, %cmp_rhs, implicit-def $nzcv ; SELECT-NEXT: %cmp_rhs:gpr64 = SUBSXrs %zero, %sext_in_reg, 131, implicit-def $nzcv
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; SELECT-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %shl, %cmp_rhs, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%zero:_(s64) = G_CONSTANT i64 0 %zero:_(s64) = G_CONSTANT i64 0
%reg0:_(s64) = COPY $x0 %reg0:_(s64) = COPY $x0
%shl_cst:_(s64) = G_CONSTANT i64 63 %shl_cst:_(s64) = G_CONSTANT i64 63
%shl:_(s64) = G_SHL %reg0, %shl_cst(s64) %shl:_(s64) = G_SHL %reg0, %shl_cst(s64)
%cmp_lhs:_(s64) = G_SUB %zero, %shl %cmp_lhs:_(s64) = G_SUB %zero, %shl
%reg1:_(s64) = COPY $x1 %reg1:_(s64) = COPY $x1
Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; The RHS offers more constant folding opportunities than the LHS. ; The RHS offers more constant folding opportunities than the LHS.
; LOWER-LABEL: name: dont_swap_rhs_with_supported_extend ; LOWER-LABEL: name: dont_swap_rhs_with_supported_extend
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %reg0:_(s64) = COPY $x0 ; LOWER-NEXT: {{ $}}
; LOWER: %lhs_cst:_(s64) = G_CONSTANT i64 1 ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
; LOWER: %cmp_lhs:_(s64) = G_SHL %reg0, %lhs_cst(s64) ; LOWER-NEXT: %lhs_cst:_(s64) = G_CONSTANT i64 1
; LOWER: %reg1:_(s64) = COPY $x1 ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %reg0, %lhs_cst(s64)
; LOWER: %and_mask:_(s64) = G_CONSTANT i64 255 ; LOWER-NEXT: %reg1:_(s64) = COPY $x1
; LOWER: %and:_(s64) = G_AND %reg1, %and_mask ; LOWER-NEXT: %and_mask:_(s64) = G_CONSTANT i64 255
; LOWER: %rhs_cst:_(s64) = G_CONSTANT i64 1 ; LOWER-NEXT: %and:_(s64) = G_AND %reg1, %and_mask
; LOWER: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64) ; LOWER-NEXT: %rhs_cst:_(s64) = G_CONSTANT i64 1
; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs ; LOWER-NEXT: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: dont_swap_rhs_with_supported_extend ; SELECT-LABEL: name: dont_swap_rhs_with_supported_extend
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %reg0:gpr64 = COPY $x0 ; SELECT-NEXT: {{ $}}
; SELECT: %cmp_lhs:gpr64 = UBFMXri %reg0, 63, 62 ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
; SELECT: %reg1:gpr64 = COPY $x1 ; SELECT-NEXT: %cmp_lhs:gpr64 = UBFMXri %reg0, 63, 62
; SELECT: %and:gpr64common = ANDXri %reg1, 4103 ; SELECT-NEXT: %reg1:gpr64 = COPY $x1
; SELECT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_lhs, %and, 129, implicit-def $nzcv ; SELECT-NEXT: %and:gpr64common = ANDXri %reg1, 4103
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_lhs, %and, 129, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg0:_(s64) = COPY $x0 %reg0:_(s64) = COPY $x0
%lhs_cst:_(s64) = G_CONSTANT i64 1 %lhs_cst:_(s64) = G_CONSTANT i64 1
%cmp_lhs:_(s64) = G_SHL %reg0, %lhs_cst(s64) %cmp_lhs:_(s64) = G_SHL %reg0, %lhs_cst(s64)
%reg1:_(s64) = COPY $x1 %reg1:_(s64) = COPY $x1
%and_mask:_(s64) = G_CONSTANT i64 255 %and_mask:_(s64) = G_CONSTANT i64 255
%and:_(s64) = G_AND %reg1, %and_mask(s64) %and:_(s64) = G_AND %reg1, %and_mask(s64)
%rhs_cst:_(s64) = G_CONSTANT i64 1 %rhs_cst:_(s64) = G_CONSTANT i64 1
Show All 14 Lines bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; In this case, both the LHS and RHS are fed by a supported extend. However, ; In this case, both the LHS and RHS are fed by a supported extend. However,
; the LHS' shift has a constant <= 4. This makes it more profitable, so ; the LHS' shift has a constant <= 4. This makes it more profitable, so
; we should swap the operands. ; we should swap the operands.
; LOWER-LABEL: name: swap_rhs_with_supported_extend ; LOWER-LABEL: name: swap_rhs_with_supported_extend
; LOWER: liveins: $x0, $x1 ; LOWER: liveins: $x0, $x1
; LOWER: %reg0:_(s64) = COPY $x0 ; LOWER-NEXT: {{ $}}
; LOWER: %and_mask:_(s64) = G_CONSTANT i64 255 ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
; LOWER: %and:_(s64) = G_AND %reg0, %and_mask ; LOWER-NEXT: %and_mask:_(s64) = G_CONSTANT i64 255
; LOWER: %lhs_cst:_(s64) = G_CONSTANT i64 1 ; LOWER-NEXT: %and:_(s64) = G_AND %reg0, %and_mask
; LOWER: %cmp_lhs:_(s64) = G_SHL %and, %lhs_cst(s64) ; LOWER-NEXT: %lhs_cst:_(s64) = G_CONSTANT i64 1
; LOWER: %rhs_cst:_(s64) = G_CONSTANT i64 5 ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %and, %lhs_cst(s64)
; LOWER: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64) ; LOWER-NEXT: %rhs_cst:_(s64) = G_CONSTANT i64 5
; LOWER: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_rhs(s64), %cmp_lhs ; LOWER-NEXT: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
; LOWER: $w0 = COPY %cmp(s32) ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_rhs(s64), %cmp_lhs
; LOWER: RET_ReallyLR implicit $w0 ; LOWER-NEXT: $w0 = COPY %cmp(s32)
; LOWER-NEXT: RET_ReallyLR implicit $w0
; SELECT-LABEL: name: swap_rhs_with_supported_extend ; SELECT-LABEL: name: swap_rhs_with_supported_extend
; SELECT: liveins: $x0, $x1 ; SELECT: liveins: $x0, $x1
; SELECT: %reg0:gpr64 = COPY $x0 ; SELECT-NEXT: {{ $}}
; SELECT: %and:gpr64common = ANDXri %reg0, 4103 ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
; SELECT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg0.sub_32 ; SELECT-NEXT: %and:gpr64common = ANDXri %reg0, 4103
; SELECT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg0.sub_32
; SELECT: %cmp_rhs:gpr64common = SBFMXri %and, 5, 63 ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
; SELECT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 1, implicit-def $nzcv ; SELECT-NEXT: %cmp_rhs:gpr64common = SBFMXri %and, 5, 63
; SELECT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 1, implicit-def $nzcv
; SELECT: $w0 = COPY %cmp ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT: RET_ReallyLR implicit $w0 ; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
%reg0:_(s64) = COPY $x0 %reg0:_(s64) = COPY $x0
%and_mask:_(s64) = G_CONSTANT i64 255 %and_mask:_(s64) = G_CONSTANT i64 255
%and:_(s64) = G_AND %reg0, %and_mask(s64) %and:_(s64) = G_AND %reg0, %and_mask(s64)
%lhs_cst:_(s64) = G_CONSTANT i64 1 %lhs_cst:_(s64) = G_CONSTANT i64 1
%cmp_lhs:_(s64) = G_SHL %and, %lhs_cst(s64) %cmp_lhs:_(s64) = G_SHL %and, %lhs_cst(s64)
%rhs_cst:_(s64) = G_CONSTANT i64 5 %rhs_cst:_(s64) = G_CONSTANT i64 5
%cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64) %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
%cmp:_(s32) = G_ICMP intpred(sgt), %cmp_lhs(s64), %cmp_rhs %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_lhs(s64), %cmp_rhs
$w0 = COPY %cmp(s32) $w0 = COPY %cmp(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0

llvm/test/CodeGen/AArch64/O0-pipeline.ll

Show All 33 Lines
; CHECK-NEXT: Prepare callbr ; CHECK-NEXT: Prepare callbr
; CHECK-NEXT: Safe Stack instrumentation pass ; CHECK-NEXT: Safe Stack instrumentation pass
; CHECK-NEXT: Insert stack protectors ; CHECK-NEXT: Insert stack protectors
; CHECK-NEXT: Module Verifier ; CHECK-NEXT: Module Verifier
; CHECK-NEXT: Analysis containing CSE Info ; CHECK-NEXT: Analysis containing CSE Info
; CHECK-NEXT: IRTranslator ; CHECK-NEXT: IRTranslator
; CHECK-NEXT: Analysis for ComputingKnownBits ; CHECK-NEXT: Analysis for ComputingKnownBits
; CHECK-NEXT: AArch64O0PreLegalizerCombiner ; CHECK-NEXT: AArch64O0PreLegalizerCombiner
; CHECK-NEXT: Localizer
; CHECK-NEXT: Analysis containing CSE Info ; CHECK-NEXT: Analysis containing CSE Info
; CHECK-NEXT: Analysis for ComputingKnownBits
; CHECK-NEXT: Legalizer ; CHECK-NEXT: Legalizer
; CHECK-NEXT: AArch64PostLegalizerLowering ; CHECK-NEXT: AArch64PostLegalizerLowering
; CHECK-NEXT: RegBankSelect ; CHECK-NEXT: RegBankSelect
; CHECK-NEXT: Localizer
; CHECK-NEXT: Analysis for ComputingKnownBits ; CHECK-NEXT: Analysis for ComputingKnownBits
; CHECK-NEXT: InstructionSelect ; CHECK-NEXT: InstructionSelect
; CHECK-NEXT: ResetMachineFunction ; CHECK-NEXT: ResetMachineFunction
; CHECK-NEXT: Assignment Tracking Analysis ; CHECK-NEXT: Assignment Tracking Analysis
; CHECK-NEXT: AArch64 Instruction Selection ; CHECK-NEXT: AArch64 Instruction Selection
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: Local Stack Slot Allocation
; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Eliminate PHI nodes for register allocation
Show All 37 Lines

llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll

Show All 32 Lines
entry: entry:
%r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 0, i64 0) %r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 0, i64 0)
ret ptr %r ret ptr %r
} }
define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) { define ptr @memset_tagged_1_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_1_zeroval: ; GISel-O0-LABEL: memset_tagged_1_zeroval:
; GISel-O0: // %bb.0: // %entry ; GISel-O0: // %bb.0: // %entry
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: mov w8, #1 ; GISel-O0-NEXT: mov w8, #1
; GISel-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9 ; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9 ; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9 ; GISel-O0-NEXT: setge [x0]!, x8!, x9
; GISel-O0-NEXT: ret ; GISel-O0-NEXT: ret
; ;
; GISel-LABEL: memset_tagged_1_zeroval: ; GISel-LABEL: memset_tagged_1_zeroval:
; GISel: // %bb.0: // %entry ; GISel: // %bb.0: // %entry
; GISel-NEXT: mov w8, #1 ; GISel-NEXT: mov w8, #1
Show All 12 Lines
entry: entry:
%r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 0, i64 1) %r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 0, i64 1)
ret ptr %r ret ptr %r
} }
define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) { define ptr @memset_tagged_10_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_10_zeroval: ; GISel-O0-LABEL: memset_tagged_10_zeroval:
; GISel-O0: // %bb.0: // %entry ; GISel-O0: // %bb.0: // %entry
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: mov w8, #10 ; GISel-O0-NEXT: mov w8, #10
; GISel-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9 ; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9 ; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9 ; GISel-O0-NEXT: setge [x0]!, x8!, x9
; GISel-O0-NEXT: ret ; GISel-O0-NEXT: ret
; ;
; GISel-LABEL: memset_tagged_10_zeroval: ; GISel-LABEL: memset_tagged_10_zeroval:
; GISel: // %bb.0: // %entry ; GISel: // %bb.0: // %entry
; GISel-NEXT: mov w8, #10 ; GISel-NEXT: mov w8, #10
Show All 12 Lines
entry: entry:
%r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 0, i64 10) %r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 0, i64 10)
ret ptr %r ret ptr %r
} }
define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) { define ptr @memset_tagged_10000_zeroval(ptr %dst, i64 %size) {
; GISel-O0-LABEL: memset_tagged_10000_zeroval: ; GISel-O0-LABEL: memset_tagged_10000_zeroval:
; GISel-O0: // %bb.0: // %entry ; GISel-O0: // %bb.0: // %entry
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: mov w8, #10000 ; GISel-O0-NEXT: mov w8, #10000
; GISel-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: mov x9, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9 ; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9 ; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9 ; GISel-O0-NEXT: setge [x0]!, x8!, x9
; GISel-O0-NEXT: ret ; GISel-O0-NEXT: ret
; ;
; GISel-LABEL: memset_tagged_10000_zeroval: ; GISel-LABEL: memset_tagged_10000_zeroval:
; GISel: // %bb.0: // %entry ; GISel: // %bb.0: // %entry
; GISel-NEXT: mov w8, #10000 ; GISel-NEXT: mov w8, #10000
Show All 39 Lines
entry: entry:
%r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 0, i64 %size) %r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 0, i64 %size)
ret ptr %r ret ptr %r
} }
define ptr @memset_tagged_0(ptr %dst, i64 %size, i32 %value) { define ptr @memset_tagged_0(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_0: ; GISel-O0-LABEL: memset_tagged_0:
; GISel-O0: // %bb.0: // %entry ; GISel-O0: // %bb.0: // %entry
; GISel-O0-NEXT: mov x8, xzr
; GISel-O0-NEXT: // implicit-def: $x9 ; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2 ; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: mov x8, xzr
; GISel-O0-NEXT: setgp [x0]!, x8!, x9 ; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9 ; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9 ; GISel-O0-NEXT: setge [x0]!, x8!, x9
; GISel-O0-NEXT: ret ; GISel-O0-NEXT: ret
; ;
; GISel-LABEL: memset_tagged_0: ; GISel-LABEL: memset_tagged_0:
; GISel: // %bb.0: // %entry ; GISel: // %bb.0: // %entry
; GISel-NEXT: mov x8, xzr ; GISel-NEXT: mov x8, xzr
Show All 15 Linesentry:
%value_trunc = trunc i32 %value to i8 %value_trunc = trunc i32 %value to i8
%r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 %value_trunc, i64 0) %r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 %value_trunc, i64 0)
ret ptr %r ret ptr %r
} }
define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) { define ptr @memset_tagged_1(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_1: ; GISel-O0-LABEL: memset_tagged_1:
; GISel-O0: // %bb.0: // %entry ; GISel-O0: // %bb.0: // %entry
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: mov w8, #1 ; GISel-O0-NEXT: mov w8, #1
; GISel-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: setgp [x0]!, x8!, x9 ; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9 ; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9 ; GISel-O0-NEXT: setge [x0]!, x8!, x9
; GISel-O0-NEXT: ret ; GISel-O0-NEXT: ret
; ;
; GISel-LABEL: memset_tagged_1: ; GISel-LABEL: memset_tagged_1:
; GISel: // %bb.0: // %entry ; GISel: // %bb.0: // %entry
; GISel-NEXT: mov w8, #1 ; GISel-NEXT: mov w8, #1
Show All 15 Linesentry:
%value_trunc = trunc i32 %value to i8 %value_trunc = trunc i32 %value to i8
%r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 %value_trunc, i64 1) %r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 %value_trunc, i64 1)
ret ptr %r ret ptr %r
} }
define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) { define ptr @memset_tagged_10(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_10: ; GISel-O0-LABEL: memset_tagged_10:
; GISel-O0: // %bb.0: // %entry ; GISel-O0: // %bb.0: // %entry
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: mov w8, #10 ; GISel-O0-NEXT: mov w8, #10
; GISel-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: setgp [x0]!, x8!, x9 ; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9 ; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9 ; GISel-O0-NEXT: setge [x0]!, x8!, x9
; GISel-O0-NEXT: ret ; GISel-O0-NEXT: ret
; ;
; GISel-LABEL: memset_tagged_10: ; GISel-LABEL: memset_tagged_10:
; GISel: // %bb.0: // %entry ; GISel: // %bb.0: // %entry
; GISel-NEXT: mov w8, #10 ; GISel-NEXT: mov w8, #10
Show All 15 Linesentry:
%value_trunc = trunc i32 %value to i8 %value_trunc = trunc i32 %value to i8
%r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 %value_trunc, i64 10) %r = tail call ptr @llvm.aarch64.mops.memset.tag(ptr %dst, i8 %value_trunc, i64 10)
ret ptr %r ret ptr %r
} }
define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) { define ptr @memset_tagged_10000(ptr %dst, i64 %size, i32 %value) {
; GISel-O0-LABEL: memset_tagged_10000: ; GISel-O0-LABEL: memset_tagged_10000:
; GISel-O0: // %bb.0: // %entry ; GISel-O0: // %bb.0: // %entry
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: mov w8, #10000 ; GISel-O0-NEXT: mov w8, #10000
; GISel-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-O0-NEXT: // kill: def $x8 killed $w8
; GISel-O0-NEXT: // implicit-def: $x9
; GISel-O0-NEXT: mov w9, w2
; GISel-O0-NEXT: setgp [x0]!, x8!, x9 ; GISel-O0-NEXT: setgp [x0]!, x8!, x9
; GISel-O0-NEXT: setgm [x0]!, x8!, x9 ; GISel-O0-NEXT: setgm [x0]!, x8!, x9
; GISel-O0-NEXT: setge [x0]!, x8!, x9 ; GISel-O0-NEXT: setge [x0]!, x8!, x9
; GISel-O0-NEXT: ret ; GISel-O0-NEXT: ret
; ;
; GISel-LABEL: memset_tagged_10000: ; GISel-LABEL: memset_tagged_10000:
; GISel: // %bb.0: // %entry ; GISel: // %bb.0: // %entry
; GISel-NEXT: mov w8, #10000 ; GISel-NEXT: mov w8, #10000
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/aarch64-mops.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
} }
define void @memset_10_zeroval_volatile(ptr %dst) { define void @memset_10_zeroval_volatile(ptr %dst) {
; GISel-WITHOUT-MOPS-O0-LABEL: memset_10_zeroval_volatile: ; GISel-WITHOUT-MOPS-O0-LABEL: memset_10_zeroval_volatile:
; GISel-WITHOUT-MOPS-O0: // %bb.0: // %entry ; GISel-WITHOUT-MOPS-O0: // %bb.0: // %entry
; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 16 ; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 16
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16 ; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16
; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: mov w8, #10 ; GISel-WITHOUT-MOPS-O0-NEXT: mov w8, #10
; GISel-WITHOUT-MOPS-O0-NEXT: mov w2, w8 ; GISel-WITHOUT-MOPS-O0-NEXT: mov w2, w8
; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: bl memset ; GISel-WITHOUT-MOPS-O0-NEXT: bl memset
; GISel-WITHOUT-MOPS-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; GISel-WITHOUT-MOPS-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O0-NEXT: ret ; GISel-WITHOUT-MOPS-O0-NEXT: ret
; ;
; GISel-WITHOUT-MOPS-O3-LABEL: memset_10_zeroval_volatile: ; GISel-WITHOUT-MOPS-O3-LABEL: memset_10_zeroval_volatile:
; GISel-WITHOUT-MOPS-O3: // %bb.0: // %entry ; GISel-WITHOUT-MOPS-O3: // %bb.0: // %entry
; GISel-WITHOUT-MOPS-O3-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; GISel-WITHOUT-MOPS-O3-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_def_cfa_offset 16 ; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_def_cfa_offset 16
; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16 ; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16
; GISel-WITHOUT-MOPS-O3-NEXT: mov w1, wzr ; GISel-WITHOUT-MOPS-O3-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10 ; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10
; GISel-WITHOUT-MOPS-O3-NEXT: bl memset ; GISel-WITHOUT-MOPS-O3-NEXT: bl memset
; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O3-NEXT: ret ; GISel-WITHOUT-MOPS-O3-NEXT: ret
; ;
; GISel-MOPS-O0-LABEL: memset_10_zeroval_volatile: ; GISel-MOPS-O0-LABEL: memset_10_zeroval_volatile:
; GISel-MOPS-O0: // %bb.0: // %entry ; GISel-MOPS-O0: // %bb.0: // %entry
; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: mov w8, #10 ; GISel-MOPS-O0-NEXT: mov w8, #10
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: ret ; GISel-MOPS-O0-NEXT: ret
; ;
; GISel-MOPS-O3-LABEL: memset_10_zeroval_volatile: ; GISel-MOPS-O3-LABEL: memset_10_zeroval_volatile:
; GISel-MOPS-O3: // %bb.0: // %entry ; GISel-MOPS-O3: // %bb.0: // %entry
; GISel-MOPS-O3-NEXT: mov w8, #10 ; GISel-MOPS-O3-NEXT: mov w8, #10
Show All 19 Lines
} }
define void @memset_10000_zeroval(ptr %dst) { define void @memset_10000_zeroval(ptr %dst) {
; GISel-WITHOUT-MOPS-O0-LABEL: memset_10000_zeroval: ; GISel-WITHOUT-MOPS-O0-LABEL: memset_10000_zeroval:
; GISel-WITHOUT-MOPS-O0: // %bb.0: // %entry ; GISel-WITHOUT-MOPS-O0: // %bb.0: // %entry
; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 16 ; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 16
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16 ; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16
; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: mov w8, #10000 ; GISel-WITHOUT-MOPS-O0-NEXT: mov w8, #10000
; GISel-WITHOUT-MOPS-O0-NEXT: mov w2, w8 ; GISel-WITHOUT-MOPS-O0-NEXT: mov w2, w8
; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: bl memset ; GISel-WITHOUT-MOPS-O0-NEXT: bl memset
; GISel-WITHOUT-MOPS-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; GISel-WITHOUT-MOPS-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O0-NEXT: ret ; GISel-WITHOUT-MOPS-O0-NEXT: ret
; ;
; GISel-WITHOUT-MOPS-O3-LABEL: memset_10000_zeroval: ; GISel-WITHOUT-MOPS-O3-LABEL: memset_10000_zeroval:
; GISel-WITHOUT-MOPS-O3: // %bb.0: // %entry ; GISel-WITHOUT-MOPS-O3: // %bb.0: // %entry
; GISel-WITHOUT-MOPS-O3-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; GISel-WITHOUT-MOPS-O3-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_def_cfa_offset 16 ; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_def_cfa_offset 16
; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16 ; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16
; GISel-WITHOUT-MOPS-O3-NEXT: mov w1, wzr ; GISel-WITHOUT-MOPS-O3-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10000 ; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10000
; GISel-WITHOUT-MOPS-O3-NEXT: bl memset ; GISel-WITHOUT-MOPS-O3-NEXT: bl memset
; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O3-NEXT: ret ; GISel-WITHOUT-MOPS-O3-NEXT: ret
; ;
; GISel-MOPS-O0-LABEL: memset_10000_zeroval: ; GISel-MOPS-O0-LABEL: memset_10000_zeroval:
; GISel-MOPS-O0: // %bb.0: // %entry ; GISel-MOPS-O0: // %bb.0: // %entry
; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: mov w8, #10000 ; GISel-MOPS-O0-NEXT: mov w8, #10000
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: ret ; GISel-MOPS-O0-NEXT: ret
; ;
; GISel-MOPS-O3-LABEL: memset_10000_zeroval: ; GISel-MOPS-O3-LABEL: memset_10000_zeroval:
; GISel-MOPS-O3: // %bb.0: // %entry ; GISel-MOPS-O3: // %bb.0: // %entry
; GISel-MOPS-O3-NEXT: mov w8, #10000 ; GISel-MOPS-O3-NEXT: mov w8, #10000
Show All 26 Lines
} }
define void @memset_10000_zeroval_volatile(ptr %dst) { define void @memset_10000_zeroval_volatile(ptr %dst) {
; GISel-WITHOUT-MOPS-O0-LABEL: memset_10000_zeroval_volatile: ; GISel-WITHOUT-MOPS-O0-LABEL: memset_10000_zeroval_volatile:
; GISel-WITHOUT-MOPS-O0: // %bb.0: // %entry ; GISel-WITHOUT-MOPS-O0: // %bb.0: // %entry
; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; GISel-WITHOUT-MOPS-O0-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 16 ; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_def_cfa_offset 16
; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16 ; GISel-WITHOUT-MOPS-O0-NEXT: .cfi_offset w30, -16
; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: mov w8, #10000 ; GISel-WITHOUT-MOPS-O0-NEXT: mov w8, #10000
; GISel-WITHOUT-MOPS-O0-NEXT: mov w2, w8 ; GISel-WITHOUT-MOPS-O0-NEXT: mov w2, w8
; GISel-WITHOUT-MOPS-O0-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O0-NEXT: bl memset ; GISel-WITHOUT-MOPS-O0-NEXT: bl memset
; GISel-WITHOUT-MOPS-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; GISel-WITHOUT-MOPS-O0-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O0-NEXT: ret ; GISel-WITHOUT-MOPS-O0-NEXT: ret
; ;
; GISel-WITHOUT-MOPS-O3-LABEL: memset_10000_zeroval_volatile: ; GISel-WITHOUT-MOPS-O3-LABEL: memset_10000_zeroval_volatile:
; GISel-WITHOUT-MOPS-O3: // %bb.0: // %entry ; GISel-WITHOUT-MOPS-O3: // %bb.0: // %entry
; GISel-WITHOUT-MOPS-O3-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; GISel-WITHOUT-MOPS-O3-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_def_cfa_offset 16 ; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_def_cfa_offset 16
; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16 ; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16
; GISel-WITHOUT-MOPS-O3-NEXT: mov w1, wzr ; GISel-WITHOUT-MOPS-O3-NEXT: mov w1, wzr
; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10000 ; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10000
; GISel-WITHOUT-MOPS-O3-NEXT: bl memset ; GISel-WITHOUT-MOPS-O3-NEXT: bl memset
; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O3-NEXT: ret ; GISel-WITHOUT-MOPS-O3-NEXT: ret
; ;
; GISel-MOPS-O0-LABEL: memset_10000_zeroval_volatile: ; GISel-MOPS-O0-LABEL: memset_10000_zeroval_volatile:
; GISel-MOPS-O0: // %bb.0: // %entry ; GISel-MOPS-O0: // %bb.0: // %entry
; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: mov w8, #10000 ; GISel-MOPS-O0-NEXT: mov w8, #10000
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
; GISel-MOPS-O0-NEXT: mov x9, xzr
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: ret ; GISel-MOPS-O0-NEXT: ret
; ;
; GISel-MOPS-O3-LABEL: memset_10000_zeroval_volatile: ; GISel-MOPS-O3-LABEL: memset_10000_zeroval_volatile:
; GISel-MOPS-O3: // %bb.0: // %entry ; GISel-MOPS-O3: // %bb.0: // %entry
; GISel-MOPS-O3-NEXT: mov w8, #10000 ; GISel-MOPS-O3-NEXT: mov w8, #10000
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; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16 ; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16
; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10 ; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10
; GISel-WITHOUT-MOPS-O3-NEXT: bl memset ; GISel-WITHOUT-MOPS-O3-NEXT: bl memset
; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O3-NEXT: ret ; GISel-WITHOUT-MOPS-O3-NEXT: ret
; ;
; GISel-MOPS-O0-LABEL: memset_10_volatile: ; GISel-MOPS-O0-LABEL: memset_10_volatile:
; GISel-MOPS-O0: // %bb.0: // %entry ; GISel-MOPS-O0: // %bb.0: // %entry
; GISel-MOPS-O0-NEXT: // implicit-def: $x9
; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: mov w8, #10 ; GISel-MOPS-O0-NEXT: mov w8, #10
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
; GISel-MOPS-O0-NEXT: // implicit-def: $x9
; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: ret ; GISel-MOPS-O0-NEXT: ret
; ;
; GISel-MOPS-O3-LABEL: memset_10_volatile: ; GISel-MOPS-O3-LABEL: memset_10_volatile:
; GISel-MOPS-O3: // %bb.0: // %entry ; GISel-MOPS-O3: // %bb.0: // %entry
; GISel-MOPS-O3-NEXT: mov w8, #10 ; GISel-MOPS-O3-NEXT: mov w8, #10
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; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16 ; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16
; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10000 ; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10000
; GISel-WITHOUT-MOPS-O3-NEXT: bl memset ; GISel-WITHOUT-MOPS-O3-NEXT: bl memset
; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O3-NEXT: ret ; GISel-WITHOUT-MOPS-O3-NEXT: ret
; ;
; GISel-MOPS-O0-LABEL: memset_10000: ; GISel-MOPS-O0-LABEL: memset_10000:
; GISel-MOPS-O0: // %bb.0: // %entry ; GISel-MOPS-O0: // %bb.0: // %entry
; GISel-MOPS-O0-NEXT: // implicit-def: $x9
; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: mov w8, #10000 ; GISel-MOPS-O0-NEXT: mov w8, #10000
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
; GISel-MOPS-O0-NEXT: // implicit-def: $x9
; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: ret ; GISel-MOPS-O0-NEXT: ret
; ;
; GISel-MOPS-O3-LABEL: memset_10000: ; GISel-MOPS-O3-LABEL: memset_10000:
; GISel-MOPS-O3: // %bb.0: // %entry ; GISel-MOPS-O3: // %bb.0: // %entry
; GISel-MOPS-O3-NEXT: mov w8, #10000 ; GISel-MOPS-O3-NEXT: mov w8, #10000
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; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16 ; GISel-WITHOUT-MOPS-O3-NEXT: .cfi_offset w30, -16
; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10000 ; GISel-WITHOUT-MOPS-O3-NEXT: mov w2, #10000
; GISel-WITHOUT-MOPS-O3-NEXT: bl memset ; GISel-WITHOUT-MOPS-O3-NEXT: bl memset
; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; GISel-WITHOUT-MOPS-O3-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; GISel-WITHOUT-MOPS-O3-NEXT: ret ; GISel-WITHOUT-MOPS-O3-NEXT: ret
; ;
; GISel-MOPS-O0-LABEL: memset_10000_volatile: ; GISel-MOPS-O0-LABEL: memset_10000_volatile:
; GISel-MOPS-O0: // %bb.0: // %entry ; GISel-MOPS-O0: // %bb.0: // %entry
; GISel-MOPS-O0-NEXT: // implicit-def: $x9
; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: mov w8, #10000 ; GISel-MOPS-O0-NEXT: mov w8, #10000
; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8 ; GISel-MOPS-O0-NEXT: // kill: def $x8 killed $w8
; GISel-MOPS-O0-NEXT: // implicit-def: $x9
; GISel-MOPS-O0-NEXT: mov w9, w1
; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setp [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: setm [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9 ; GISel-MOPS-O0-NEXT: sete [x0]!, x8!, x9
; GISel-MOPS-O0-NEXT: ret ; GISel-MOPS-O0-NEXT: ret
; ;
; GISel-MOPS-O3-LABEL: memset_10000_volatile: ; GISel-MOPS-O3-LABEL: memset_10000_volatile:
; GISel-MOPS-O3: // %bb.0: // %entry ; GISel-MOPS-O3: // %bb.0: // %entry
; GISel-MOPS-O3-NEXT: mov w8, #10000 ; GISel-MOPS-O3-NEXT: mov w8, #10000
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llvm/test/CodeGen/AArch64/popcount.ll

Show All 36 Lines
; CHECK-NEXT: // implicit-def: $q0 ; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: mov v0.d[0], x9 ; CHECK-NEXT: mov v0.d[0], x9
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: cnt v1.16b, v1.16b ; CHECK-NEXT: cnt v1.16b, v1.16b
; CHECK-NEXT: uaddlv h2, v1.16b ; CHECK-NEXT: uaddlv h2, v1.16b
; CHECK-NEXT: // implicit-def: $q1 ; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: fmov s1, s2 ; CHECK-NEXT: fmov s1, s2
; CHECK-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-NEXT: // kill: def $s1 killed $s1 killed $q1
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: mov w10, wzr ; CHECK-NEXT: mov w10, wzr
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: mov w9, w0 ; CHECK-NEXT: mov w9, w0
; CHECK-NEXT: mov w8, w10 ; CHECK-NEXT: mov w8, w10
; CHECK-NEXT: bfi x9, x8, #32, #32 ; CHECK-NEXT: bfi x9, x8, #32, #32
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: uaddlv h1, v0.16b ; CHECK-NEXT: uaddlv h1, v0.16b
; CHECK-NEXT: // implicit-def: $q0 ; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: fmov s0, s1 ; CHECK-NEXT: fmov s0, s1
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: // implicit-def: $q0 ; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: mov v0.d[0], x0 ; CHECK-NEXT: mov v0.d[0], x0
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: cnt v0.16b, v0.16b ; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: uaddlv h1, v0.16b ; CHECK-NEXT: uaddlv h1, v0.16b
; CHECK-NEXT: // implicit-def: $q0 ; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: fmov s0, s1 ; CHECK-NEXT: fmov s0, s1
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: mov w8, wzr ; CHECK-NEXT: mov w8, wzr
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: // kill: def $x0 killed $w0 ; CHECK-NEXT: // kill: def $x0 killed $w0
; CHECK-NEXT: // kill: def $x8 killed $w8 ; CHECK-NEXT: // kill: def $x8 killed $w8
; CHECK-NEXT: bfi x0, x8, #32, #32 ; CHECK-NEXT: bfi x0, x8, #32, #32
; CHECK-NEXT: mov x1, xzr ; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Entry: Entry:
%1 = tail call <1 x i128> @llvm.ctpop.v1.i128(<1 x i128> %0) %1 = tail call <1 x i128> @llvm.ctpop.v1.i128(<1 x i128> %0)
ret <1 x i128> %1 ret <1 x i128> %1
} }
declare <1 x i128> @llvm.ctpop.v1.i128(<1 x i128>) declare <1 x i128> @llvm.ctpop.v1.i128(<1 x i128>)

llvm/test/Other/print-changed-machine.ll

Show All 16 Lines
; VERBOSE-BAR: *** IR Dump After IRTranslator (irtranslator) on bar *** ; VERBOSE-BAR: *** IR Dump After IRTranslator (irtranslator) on bar ***
; NO-BAR-NOT: on bar *** ; NO-BAR-NOT: on bar ***
; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed=quiet %s 2>&1 | FileCheck %s --check-prefix=QUIET ; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed=quiet %s 2>&1 | FileCheck %s --check-prefix=QUIET
; QUIET: *** IR Dump After IRTranslator (irtranslator) on foo *** ; QUIET: *** IR Dump After IRTranslator (irtranslator) on foo ***
; QUIET-NOT: *** ; QUIET-NOT: ***
; QUIET: *** IR Dump After Legalizer (legalizer) on foo *** ; QUIET: *** IR Dump After Localizer (localizer) on foo ***
; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed -filter-passes=irtranslator,legalizer %s 2>&1 | \ ; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed -filter-passes=irtranslator,legalizer %s 2>&1 | \
; RUN: FileCheck %s --check-prefixes=VERBOSE-FILTER ; RUN: FileCheck %s --check-prefixes=VERBOSE-FILTER
; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed=quiet -filter-passes=irtranslator %s 2>&1 | \ ; RUN: llc -filetype=null -mtriple=aarch64 -O0 -print-changed=quiet -filter-passes=irtranslator %s 2>&1 | \
; RUN: FileCheck %s --check-prefixes=QUIET-FILTER --implicit-check-not='IR Dump' ; RUN: FileCheck %s --check-prefixes=QUIET-FILTER --implicit-check-not='IR Dump'
; VERBOSE-FILTER: *** IR Dump After IRTranslator (irtranslator) on foo *** ; VERBOSE-FILTER: *** IR Dump After IRTranslator (irtranslator) on foo ***
; VERBOSE-FILTER: *** IR Dump After AArch64O0PreLegalizerCombiner (aarch64-O0-prelegalizer-combiner) on foo filtered out *** ; VERBOSE-FILTER: *** IR Dump After AArch64O0PreLegalizerCombiner (aarch64-O0-prelegalizer-combiner) on foo filtered out ***
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llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll