[M68k] Basic FP register files and FMOVE implementations

[myhsu]

Summary

• FP registers and register classes definitions
• MC support for FP registers
• MC support for the FPDR -> FPDR variant of FMOVE/FSMOVE/FDSMOVE

Note that we don't implement 32/64-bit FP registers with subregisters since f32/f64 values will be converted to f80 upon storing into a register, rather than occupying part of the register. So we only use register classes with different value types to distinguish them.

[0x59616e]

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

645

nit: Can "starts_with" do better in terms of readability ?

645–651

nit: Maybe use early exist to reduce indentation ?

[myhsu]

Update the register name parsing logics.

[myhsu]

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

645–651

I wrote in this way so that we can easily plug in the parsing logics for floating point control registers (e.g. fpcr, fpiar) in the future. Please take a look again

[myhsu]

minor updates.

[0x59616e]

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

645–651

It looks even better now.

[0x59616e]

It seems that we still lack the memory operand for floating point, e.g. something like "MxPCIFP32". Am I correct ? What is your plan of this ?

[myhsu]

In D147480#4253102, @0x59616e wrote:

It seems that we still lack the memory operand for floating point, e.g. something like "MxPCIFP32". Am I correct ? What is your plan of this ?

Right, those are currently absent and will be added in subsequent patches, along with variants of FMOVE between data and fp registers.

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

public:
   bool isMemOp() const { return Kind == KindTy::MemOp; }
 
   static void addExpr(MCInst &Inst, const MCExpr *Expr);
 
   // Reg
   bool isReg() const override;
   bool isAReg() const;
   bool isDReg() const;
+  bool isFPDReg() const;
   unsigned getReg() const override;
   void addRegOperands(MCInst &Inst, unsigned N) const;
 
   static std::unique_ptr<M68kOperand> createMemOp(M68kMemOp MemOp, SMLoc Start,
                                                   SMLoc End);
 
   // Token
   bool isToken() const override;

 }
 
 #define GET_REGISTER_MATCHER
 #define GET_MATCHER_IMPLEMENTATION
 #include "M68kGenAsmMatcher.inc"
 
 static inline unsigned getRegisterByIndex(unsigned RegisterIndex) {
   static unsigned RegistersByIndex[] = {
-      M68k::D0, M68k::D1, M68k::D2, M68k::D3, M68k::D4, M68k::D5,
-      M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
-      M68k::A4, M68k::A5, M68k::A6, M68k::SP,
-  };
+      M68k::D0,  M68k::D1,  M68k::D2,  M68k::D3,  M68k::D4,  M68k::D5,
+      M68k::D6,  M68k::D7,  M68k::A0,  M68k::A1,  M68k::A2,  M68k::A3,
+      M68k::A4,  M68k::A5,  M68k::A6,  M68k::SP,  M68k::FP0, M68k::FP1,
+      M68k::FP2, M68k::FP3, M68k::FP4, M68k::FP5, M68k::FP6, M68k::FP7};
   assert(RegisterIndex <=
          sizeof(RegistersByIndex) / sizeof(RegistersByIndex[0]));
   return RegistersByIndex[RegisterIndex];
 }
 
 static inline unsigned getRegisterIndex(unsigned Register) {
   if (Register >= M68k::D0 && Register <= M68k::D7)
     return Register - M68k::D0;
   if (Register >= M68k::A0 && Register <= M68k::A6)
     return Register - M68k::A0 + 8;
+  if (Register >= M68k::FP0 && Register <= M68k::FP7)
+    return Register - M68k::FP0 + 16;
 
   switch (Register) {
   case M68k::SP:
     // SP is sadly not contiguous with the rest of the An registers
     return 15;
 
   case M68k::PC:
   case M68k::CCR:
return isMemOp() &&
          MemOp.OuterReg == M68k::PC;
 }
 void M68kOperand::addPCIOperands(MCInst &Inst, unsigned N) const {
   M68kOperand::addExpr(Inst, MemOp.OuterDisp);
   Inst.addOperand(MCOperand::createReg(MemOp.InnerReg));
 }
 
 static inline bool checkRegisterClass(unsigned RegNo, bool Data, bool Address,
-                                      bool SP) {
+                                      bool SP, bool FPDR = false) {
   switch (RegNo) {
   case M68k::A0:
   case M68k::A1:
   case M68k::A2:
   case M68k::A3:
   case M68k::A4:
   case M68k::A5:
   case M68k::A6:
static inline bool checkRegisterClass(unsigned RegNo, bool Data, bool Address,
   case M68k::D6:
   case M68k::D7:
     return Data;
 
   case M68k::SR:
   case M68k::CCR:
     return false;
 
+  case M68k::FP0:
+  case M68k::FP1:
+  case M68k::FP2:
+  case M68k::FP3:
+  case M68k::FP4:
+  case M68k::FP5:
+  case M68k::FP6:
+  case M68k::FP7:
+    return FPDR;
+
   default:
     llvm_unreachable("unexpected register type");
     return false;
   }
 }
 
 bool M68kOperand::isAReg() const {
   return isReg() && checkRegisterClass(getReg(),
                                        /*Data=*/false,
                                        /*Address=*/true, /*SP=*/true);
 }
 
 bool M68kOperand::isDReg() const {
   return isReg() && checkRegisterClass(getReg(),
                                        /*Data=*/true,
                                        /*Address=*/false, /*SP=*/false);
 }
 
+bool M68kOperand::isFPDReg() const {
+  return isReg() && checkRegisterClass(getReg(),
+                                       /*Data=*/false,
+                                       /*Address=*/false, /*SP=*/false,
+                                       /*FPDR=*/true);
+}
+
 unsigned M68kAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
                                                    unsigned Kind) {
   M68kOperand &Operand = (M68kOperand &)Op;
 
   switch (Kind) {
   case MCK_XR16:
   case MCK_SPILL:
     if (Operand.isReg() &&
if (RegisterNameLower.size() == 2) {
 
     case 'p':
       if (RegisterNameLower[1] == 'c') {
         RegNo = M68k::PC;
         return true;
       }
       break;
     }
+  } else if (RegisterNameLower.size() > 2) {
+    // Floating point data register.
+    if (StringRef(RegisterNameLower).take_front(2) == "fp") {
+      auto RegIndex = unsigned(RegisterNameLower[2] - '0');
+      if (RegIndex < 8) {
+        RegNo = getRegisterByIndex(16 + RegIndex);
+        return true;
+      }
+    }
   }
 
   return false;
 }
 
 OperandMatchResultTy M68kAsmParser::parseRegister(MCRegister &RegNo) {
   bool HasPercent = false;
   AsmToken PercentToken;

llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp

 
 using namespace llvm;
 
 #define DEBUG_TYPE "m68k-disassembler"
 
 typedef MCDisassembler::DecodeStatus DecodeStatus;
 
 static const unsigned RegisterDecode[] = {
-    M68k::D0, M68k::D1, M68k::D2, M68k::D3, M68k::D4, M68k::D5,
-    M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
-    M68k::A4, M68k::A5, M68k::A6, M68k::SP,
-};
+    M68k::D0,  M68k::D1,  M68k::D2,  M68k::D3,  M68k::D4,  M68k::D5,
+    M68k::D6,  M68k::D7,  M68k::A0,  M68k::A1,  M68k::A2,  M68k::A3,
+    M68k::A4,  M68k::A5,  M68k::A6,  M68k::SP,  M68k::FP0, M68k::FP1,
+    M68k::FP2, M68k::FP3, M68k::FP4, M68k::FP5, M68k::FP6, M68k::FP7};
 
 static DecodeStatus DecodeRegisterClass(MCInst &Inst, uint64_t RegNo,
                                         uint64_t Address, const void *Decoder) {
-  if (RegNo >= 16)
+  if (RegNo >= 24)
     return DecodeStatus::Fail;
   Inst.addOperand(MCOperand::createReg(RegisterDecode[RegNo]));
   return DecodeStatus::Success;
 }
 
 static DecodeStatus DecodeDR32RegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {

 }
 
 static DecodeStatus DecodeXR16RegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
+static DecodeStatus DecodeFPDRRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  return DecodeRegisterClass(Inst, RegNo | 16ULL, Address, Decoder);
+}
+#define DecodeFPDR32RegisterClass DecodeFPDRRegisterClass
+#define DecodeFPDR64RegisterClass DecodeFPDRRegisterClass
+#define DecodeFPDR80RegisterClass DecodeFPDRRegisterClass
+
 static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst, APInt &Insn,
                                             uint64_t Address,
                                             const void *Decoder) {
   llvm_unreachable("unimplemented");
 }
 
 static DecodeStatus DecodeImm32(MCInst &Inst, uint64_t Imm, uint64_t Address,
                                 const void *Decoder) {
   Inst.addOperand(MCOperand::createImm(M68k::swapWord<uint32_t>(Imm)));
   return DecodeStatus::Success;
 }
 
 #include "M68kGenDisassemblerTable.inc"
 
+#undef DecodeFPDR32RegisterClass
+#undef DecodeFPDR64RegisterClass
+#undef DecodeFPDR80RegisterClass
+
 /// A disassembler class for M68k.
 struct M68kDisassembler : public MCDisassembler {
   M68kDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
       : MCDisassembler(STI, Ctx) {}
   virtual ~M68kDisassembler() {}
 
   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,

llvm/lib/Target/M68k/M68kInstrData.td

 
 // trunc patterns
 def : Pat<(i16 (trunc i32:$src)),
           (EXTRACT_SUBREG MxXRD32:$src, MxSubRegIndex16Lo)>;
 def : Pat<(i8  (trunc i32:$src)),
           (EXTRACT_SUBREG MxXRD32:$src, MxSubRegIndex8Lo)>;
 def : Pat<(i8  (trunc i16:$src)),
           (EXTRACT_SUBREG MxXRD16:$src, MxSubRegIndex8Lo)>;
+
+//===----------------------------------------------------------------------===//
+// FMOVE
+//===----------------------------------------------------------------------===//
+
+let Defs = [FPS] in
+class MxFMove<string size, dag outs, dag ins, list<dag> pattern,
+              string rounding = "">
+    : MxInst<outs, ins,
+             "f"#rounding#"move."#size#"\t$src, $dst", pattern> {
+  // Only FMOVE uses FPC
+  let Uses = !if(!eq(rounding, ""), [FPC], []);
+
+  // FSMOVE and FDMOVE are only available after M68040
+  let Predicates = [!if(!eq(rounding, ""), AtLeastM68881, AtLeastM68040)];
+}
+
+// FPDR <- FPDR
+class MxFMove_FF<string rounding, int size,
+                 MxOpBundle Opnd = !cast<MxOpBundle>("MxOp"#size#"AddrMode_fpr")>
+    : MxFMove<"x", (outs Opnd.Op:$dst), (ins Opnd.Op:$src),
+              [(null_frag)], rounding> {
+  let Inst = (ascend
+    (descend 0b1111,
+      /*COPROCESSOR ID*/0b001,
+      0b000,
+      /*MODE + REGISTER*/0b000000
+    ),
+    (descend 0b0, /* R/M */0b0, 0b0,
+      /*SOURCE SPECIFIER*/
+      (operand "$src", 3),
+      /*DESTINATION*/
+      (operand "$dst", 3),
+      /*OPMODE*/
+      !cond(!eq(rounding, "s"): 0b1000000,
+            !eq(rounding, "d"): 0b1000100,
+            true: 0b0000000)
+    )
+  );
+}
+
+foreach rounding = ["", "s", "d"] in {
+  def F # !toupper(rounding) # MOV80fp_fp : MxFMove_FF<rounding, 80>;
+
+  // We don't have `fmove.s` or `fmove.d` because values will be converted to
+  // f80 upon storing into the register, but FMOV32/64fp_fp are still needed
+  // to make codegen easier.
+  let isCodeGenOnly = true in
+  foreach size = [32, 64] in
+    def F # !toupper(rounding) # MOV # size # fp_fp : MxFMove_FF<rounding, size>;
+}

llvm/lib/Target/M68k/M68kInstrInfo.td

class MxSize<int num, string id, string full> {
   int Num = num;
   string Id = id;
   string Full = full;
 }
 
 def MxSize8  : MxSize<8,  "b", "byte">;
 def MxSize16 : MxSize<16, "w", "word">;
 def MxSize32 : MxSize<32, "l", "long">;
+def MxSizeF32 : MxSize<32, "s", "f32">;
+def MxSizeF64 : MxSize<64, "d", "f64">;
+def MxSizeF80 : MxSize<80, "x", "f80">;
 
 class MxOpClass<string name,
                 list<AsmOperandClass> superClasses = []> : AsmOperandClass {
   let Name = name;
   let ParserMethod = "parseMemOp";
   let SuperClasses = superClasses;
 }
 
 def MxRegClass : MxOpClass<"Reg">;
 // Splitting asm register class to avoid ambiguous on operands'
 // MatchClassKind. For instance, without this separation,
 // both ADD32dd and ADD32dr has {MCK_RegClass, MCK_RegClass} for
 // their operands, which makes AsmParser unable to pick the correct
 // one in a deterministic way.
 let RenderMethod = "addRegOperands", SuperClasses = [MxRegClass]in {
   def MxARegClass : MxOpClass<"AReg">;
   def MxDRegClass : MxOpClass<"DReg">;
+
+  def MxFPDRegClass : MxOpClass<"FPDReg">;
 }
 
 class MxOperand<ValueType vt, MxSize size, string letter, RegisterClass rc, dag pat = (null_frag)> {
   ValueType VT = vt;
   string Letter = letter;
   MxSize Size = size;
   RegisterClass RC = rc;
   dag Pat = pat;

 let ParserMatchClass = MxARegClass in {
   def MxARD16 : MxRegOp<i16, AR16, MxSize16, "a">;
   def MxARD32 : MxRegOp<i32, AR32, MxSize32, "a">;
 
   def MxARD16_TC : MxRegOp<i16, AR16_TC, MxSize16, "a">;
   def MxARD32_TC : MxRegOp<i32, AR32_TC, MxSize32, "a">;
 }
 
+// FLOATING POINT DATA REGISTER.
+let ParserMatchClass = MxFPDRegClass in {
+  def MxFPR32 : MxRegOp<f32, FPDR32, MxSizeF32, "fp">;
+  def MxFPR64 : MxRegOp<f64, FPDR64, MxSizeF64, "fp">;
+  def MxFPR80 : MxRegOp<f80, FPDR80, MxSizeF80, "fp">;
+}
+
 class MxMemOp<dag ops, MxSize size, string letter,
               string printMethod = "printOperand",
               AsmOperandClass parserMatchClass = ImmAsmOperand>
     : Operand<iPTR>, MxOperand<iPTR, size, letter, ?> {
   let PrintMethod = printMethod;
   let MIOperandInfo = ops;
   let ParserMatchClass = parserMatchClass;
   let OperandType = "OPERAND_MEMORY";
foreach size = [16, 32] in {
   def MxOp#size#AddrMode_a
     : MxOpBundle<size, !cast<MxOperand>("MxARD"#size), ?>;
 
   // Xn
   def MxOp#size#AddrMode_r
     : MxOpBundle<size, !cast<MxOperand>("MxXRD"#size), ?>;
 } // foreach size = [16, 32]
 
+foreach size = [32, 64, 80] in
+def MxOp#size#AddrMode_fpr
+  : MxOpBundle<size, !cast<MxOperand>("MxFPR"#size), ?>;
+
 class MxType8Class<string rLet, MxOperand reg>
     : MxType<i8, "b", "", rLet, reg,
              MxARI8,   MxCP_ARI,
              MxARIPI8, MxCP_ARIPI,
              MxARIPD8, MxCP_ARIPD,
              MxARID8,  MxCP_ARID,
              MxARII8,  MxCP_ARII,
              MxAL8,    MxCP_AL,

llvm/lib/Target/M68k/M68kRegisterInfo.td

 defm A1 : MxAddressRegister<1, "a1">;
 defm A2 : MxAddressRegister<2, "a2">;
 defm A3 : MxAddressRegister<3, "a3">;
 defm A4 : MxAddressRegister<4, "a4">;
 defm A5 : MxAddressRegister<5, "a5", ["bp"]>;
 defm A6 : MxAddressRegister<6, "a6", ["fp"]>;
 defm SP : MxAddressRegister<7, "sp", ["usp", "ssp", "isp", "a7"]>;
 
+// Floating Point Registers
+class MxFPRegister<int INDEX, string REG_NAME, list<string> ALTNAMES = []>
+    : MxReg<REG_NAME, INDEX, /*SUBREGS=*/[], /*SUBIDX=*/[],
+            /*DWREGS=*/[!add(18,INDEX)], ALTNAMES>;
+
+foreach i = {0-7} in
+  def FP#i : MxFPRegister<i, "fp"#i>;
+
+// Unlike their counterparts in integer registers, these
+// control registers can be accessed and modified by instructions.
+def FPC   : MxFPRegister<8,  "fpcr",  ["fpc"]>;
+def FPS   : MxFPRegister<9,  "fpsr",  ["fps"]>;
+def FPIAR : MxFPRegister<10, "fpiar", ["fpi"]>;
 
 // Pseudo Registers
 class MxPseudoReg<string N, list<Register> SUBREGS = [], list<SubRegIndex> SUBIDX = []>
     : MxReg<N, 0, SUBREGS, SUBIDX>;
 
 def CCR : MxPseudoReg<"ccr">;
 def SR  : MxPseudoReg<"sr">;
 

 
 // Index Register Classes
 // FIXME try alternative ordering like `D0, D1, A0, A1, ...`
 def XR16 : MxRegClass<[i16], 16, (add DR16, AR16)>;
 def XR32 : MxRegClass<[i32], 32, (add DR32, AR32)>;
 
 def SPC  : MxRegClass<[i32], 32, (add SP)>;
 
+// Floating Point Data Registers
+def FPDR32 : MxRegClass<[f32], 32, (sequence "FP%u", 0, 7)>;
+def FPDR64 : MxRegClass<[f64], 32, (add FPDR32)>;
+def FPDR80 : MxRegClass<[f80], 32, (add FPDR32)>;
+
 let CopyCost = -1 in {
   def CCRC : MxRegClass<[i8],  16, (add CCR)>;
   def SRC  : MxRegClass<[i16], 16, (add SR)>;
+
+  def FPCR : MxRegClass<[i32], 32, (add FPC, FPS, FPIAR)>;
 }
 
 let isAllocatable = 0 in {
   def PCC  : MxRegClass<[i32], 32, (add PC)>;
 }
 
 // Register used with tail call
 def DR16_TC : MxRegClass<[i16], 16, (add D0, D1)>;

llvm/test/MC/Disassembler/M68k/fp-data.txt

+# RUN: llvm-mc -disassemble -triple m68k -mcpu=M68040 %s | FileCheck %s
+
+# CHECK: fmove.x %fp7, %fp2
+0xf2 0x00 0x1d 0x00
+
+# CHECK: fsmove.x %fp6, %fp1
+0xf2 0x00 0x18 0xc0
+
+# CHECK: fdmove.x %fp3, %fp0
+0xf2 0x00 0x0c 0x44

llvm/test/MC/M68k/Data/Classes/MxFMove_FF.s

+; RUN: llvm-mc -triple=m68k -mcpu=M68040 -show-encoding < %s | FileCheck %s
+
+; CHECK: fmove.x %fp7, %fp2
+; CHECK-SAME: [0xf2,0x00,0x1d,0x00]
+fmove.x %fp7, %fp2
+
+; CHECK: fsmove.x %fp6, %fp1
+; CHECK-SAME: [0xf2,0x00,0x18,0xc0]
+fsmove.x %fp6, %fp1
+
+; CHECK: fdmove.x %fp3, %fp0
+; CHECK-SAME: [0xf2,0x00,0x0c,0x44]
+fdmove.x %fp3, %fp0