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Differential D147098

[RISCV] Made v(f)(w)red* pseudoinstructions SEW-aware
ClosedPublic

Authored by nitinjohnraj on Mar 28 2023, 5:53 PM.

Details

Reviewers
craig.topper
michaelmaitland
• pcwang-thead
Commits
rG50876630b910: [RISCV] Made v(f)(w)red* pseudoinstructions SEW-aware
Summary

This patch part of an ongoing effort to distinguish between pseudoinstructions using different SEWs in the scheduler.

Diff Detail

Event Timeline

nitinjohnraj created this revision.Mar 28 2023, 5:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 28 2023, 5:53 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 29 others. · View Herald Transcript
nitinjohnraj requested review of this revision.Mar 28 2023, 5:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 28 2023, 5:53 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
nitinjohnraj edited the summary of this revision. (Show Details)Mar 28 2023, 5:56 PM
nitinjohnraj added reviewers: craig.topper, michaelmaitland.
michaelmaitland accepted this revision.Mar 28 2023, 7:26 PM

LGTM

This revision is now accepted and ready to land.Mar 28 2023, 7:26 PM
michaelmaitland added a reviewer: • pcwang-thead.Mar 28 2023, 7:31 PM
• pcwang-thead accepted this revision.Mar 28 2023, 8:32 PM

LGTM. Thanks!

Harbormaster completed remote builds in B222381: Diff 509180.Mar 29 2023, 2:02 AM
Closed by commit rG50876630b910: [RISCV] Made v(f)(w)red* pseudoinstructions SEW-aware (authored by nitinjohnraj). · Explain WhyMar 29 2023, 10:45 AM
This revision was automatically updated to reflect the committed changes.
nitinjohnraj added a commit: rG50876630b910: [RISCV] Made v(f)(w)red* pseudoinstructions SEW-aware.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
159 lines
12 lines
test/
CodeGen/
RISCV/
rvv/
4 lines
18 lines
8 lines

Diff 509416

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,156 Lines • ▼ Show 20 Linesmulticlass VPseudoTernaryNoMaskNoPolicy<VReg RetClass,
RegisterClass Op1Class, RegisterClass Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoTernaryNoMask<RetClass, Op1Class, Op2Class, Constraint>; def "_" # MInfo.MX : VPseudoTernaryNoMask<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
} }
} }
multiclass VPseudoTernaryWithTailPolicy<VReg RetClass, multiclass VPseudoTernaryWithTailPolicy_E<VReg RetClass,
RegisterClass Op1Class, RegisterClass Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = "", string Constraint = "",
bit Commutable = 0> { bit Commutable = 0> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
defvar mx = MInfo.MX;
defvar sews = SchedSEWSet<mx>.val;
foreach e = sews in {
let isCommutable = Commutable in let isCommutable = Commutable in
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>; def "_" # mx # "_E" # e : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryTailPolicy<RetClass, Op1Class, Op2Class, Constraint>; def "_" # mx # "_E" # e # "_MASK" : VPseudoBinaryTailPolicy<RetClass, Op1Class, Op2Class, Constraint>;
}
} }
} }
multiclass VPseudoTernaryWithPolicy<VReg RetClass, multiclass VPseudoTernaryWithPolicy<VReg RetClass,
RegisterClass Op1Class, RegisterClass Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = "", string Constraint = "",
bit Commutable = 0> { bit Commutable = 0> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
▲ Show 20 Lines • Show All 240 Lines • ▼ Show 20 Lines defm "" : VPseudoBinaryM_VI<m>,
Sched<[WriteVICmpI_MX, ReadVICmpV_MX, ReadVMask]>; Sched<[WriteVICmpI_MX, ReadVICmpV_MX, ReadVMask]>;
} }
} }
multiclass VPseudoVRED_VS { multiclass VPseudoVRED_VS {
foreach m = MxList in { foreach m = MxList in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVIRedV_From_MX = !cast<SchedWrite>("WriteVIRedV_From_" # mx); defvar WriteVIRedV_From_MX = !cast<SchedWrite>("WriteVIRedV_From_" # mx);
defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>, defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
Sched<[WriteVIRedV_From_MX, ReadVIRedV, ReadVIRedV, ReadVIRedV, Sched<[WriteVIRedV_From_MX, ReadVIRedV, ReadVIRedV, ReadVIRedV,
ReadVMask]>; ReadVMask]>;
} }
} }
multiclass VPseudoVWRED_VS { multiclass VPseudoVWRED_VS {
foreach m = MxList in { foreach m = MxList in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVIWRedV_From_MX = !cast<SchedWrite>("WriteVIWRedV_From_" # mx); defvar WriteVIWRedV_From_MX = !cast<SchedWrite>("WriteVIWRedV_From_" # mx);
defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>, defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
Sched<[WriteVIWRedV_From_MX, ReadVIWRedV, ReadVIWRedV, Sched<[WriteVIWRedV_From_MX, ReadVIWRedV, ReadVIWRedV,
ReadVIWRedV, ReadVMask]>; ReadVIWRedV, ReadVMask]>;
} }
} }
multiclass VPseudoVFRED_VS { multiclass VPseudoVFRED_VS {
foreach m = MxListF in { foreach m = MxListF in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVFRedV_From_MX = !cast<SchedWrite>("WriteVFRedV_From_" # mx); defvar WriteVFRedV_From_MX = !cast<SchedWrite>("WriteVFRedV_From_" # mx);
defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>, defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
Sched<[WriteVFRedV_From_MX, ReadVFRedV, ReadVFRedV, ReadVFRedV, Sched<[WriteVFRedV_From_MX, ReadVFRedV, ReadVFRedV, ReadVFRedV,
ReadVMask]>; ReadVMask]>;
} }
} }
multiclass VPseudoVFREDO_VS { multiclass VPseudoVFREDO_VS {
foreach m = MxListF in { foreach m = MxListF in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVFRedOV_From_MX = !cast<SchedWrite>("WriteVFRedOV_From_" # mx); defvar WriteVFRedOV_From_MX = !cast<SchedWrite>("WriteVFRedOV_From_" # mx);
defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>, defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
Sched<[WriteVFRedOV_From_MX, ReadVFRedOV, ReadVFRedOV, Sched<[WriteVFRedOV_From_MX, ReadVFRedOV, ReadVFRedOV,
ReadVFRedOV, ReadVMask]>; ReadVFRedOV, ReadVMask]>;
} }
} }
multiclass VPseudoVFWRED_VS { multiclass VPseudoVFWRED_VS {
foreach m = MxListF in { foreach m = MxListF in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVFWRedV_From_MX = !cast<SchedWrite>("WriteVFWRedV_From_" # mx); defvar WriteVFWRedV_From_MX = !cast<SchedWrite>("WriteVFWRedV_From_" # mx);
defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>, defm _VS : VPseudoTernaryWithTailPolicy_E<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>,
Sched<[WriteVFWRedV_From_MX, ReadVFWRedV, ReadVFWRedV, Sched<[WriteVFWRedV_From_MX, ReadVFWRedV, ReadVFWRedV,
ReadVFWRedV, ReadVMask]>; ReadVFWRedV, ReadVMask]>;
} }
} }
multiclass VPseudoConversion<VReg RetClass, multiclass VPseudoConversion<VReg RetClass,
VReg Op1Class, VReg Op1Class,
LMULInfo MInfo, LMULInfo MInfo,
▲ Show 20 Lines • Show All 779 Lines • ▼ Show 20 Lines Pat<(result_type (!cast<Intrinsic>(intrinsic)
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
result_reg_class:$rs3, result_reg_class:$rs3,
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
op2_kind:$rs2, op2_kind:$rs2,
GPR:$vl, sew)>; GPR:$vl, sew)>;
class VPatTernaryNoMaskTA<string intrinsic, class VPatTernaryNoMaskTA_E<string intrinsic,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
int sew, int log2sew,
LMULInfo vlmul, LMULInfo vlmul,
int sew,
VReg result_reg_class, VReg result_reg_class,
RegisterClass op1_reg_class, RegisterClass op1_reg_class,
DAGOperand op2_kind> : DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic) Pat<(result_type (!cast<Intrinsic>(intrinsic)
(result_type result_reg_class:$rs3), (result_type result_reg_class:$rs3),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#sew)
result_reg_class:$rs3, result_reg_class:$rs3,
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
op2_kind:$rs2, op2_kind:$rs2,
GPR:$vl, sew, TAIL_AGNOSTIC)>; GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
class VPatTernaryNoMaskWithPolicy<string intrinsic, class VPatTernaryNoMaskWithPolicy<string intrinsic,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
int sew, int sew,
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")
VLOpFrag, (XLenVT timm:$policy))), VLOpFrag, (XLenVT timm:$policy))),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK") (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK")
result_reg_class:$rs3, result_reg_class:$rs3,
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
op2_kind:$rs2, op2_kind:$rs2,
(mask_type V0), (mask_type V0),
GPR:$vl, sew, (XLenVT timm:$policy))>; GPR:$vl, sew, (XLenVT timm:$policy))>;
class VPatTernaryMaskTA<string intrinsic, class VPatTernaryMaskTA_E<string intrinsic,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int sew, int log2sew,
LMULInfo vlmul, LMULInfo vlmul,
int sew,
VReg result_reg_class, VReg result_reg_class,
RegisterClass op1_reg_class, RegisterClass op1_reg_class,
DAGOperand op2_kind> : DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask") Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")
(result_type result_reg_class:$rs3), (result_type result_reg_class:$rs3),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
(mask_type V0), (mask_type V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK") (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#sew# "_MASK")
result_reg_class:$rs3, result_reg_class:$rs3,
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
op2_kind:$rs2, op2_kind:$rs2,
(mask_type V0), (mask_type V0),
GPR:$vl, sew, TAIL_AGNOSTIC)>; GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
multiclass VPatUnaryS_M<string intrinsic_name, multiclass VPatUnaryS_M<string intrinsic_name,
string inst> string inst>
{ {
foreach mti = AllMasks in { foreach mti = AllMasks in {
def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name) def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name)
(mti.Mask VR:$rs1), VLOpFrag)), (mti.Mask VR:$rs1), VLOpFrag)),
(!cast<Instruction>(inst#"_M_"#mti.BX) $rs1, (!cast<Instruction>(inst#"_M_"#mti.BX) $rs1,
▲ Show 20 Lines • Show All 728 Lines • ▼ Show 20 Linesmulticlass VPatTernaryWithPolicy<string intrinsic,
def : VPatTernaryNoMaskWithPolicy<intrinsic, inst, kind, result_type, op1_type, def : VPatTernaryNoMaskWithPolicy<intrinsic, inst, kind, result_type, op1_type,
op2_type, sew, vlmul, result_reg_class, op2_type, sew, vlmul, result_reg_class,
op1_reg_class, op2_kind>; op1_reg_class, op2_kind>;
def : VPatTernaryMaskPolicy<intrinsic, inst, kind, result_type, op1_type, op2_type, def : VPatTernaryMaskPolicy<intrinsic, inst, kind, result_type, op1_type, op2_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class, mask_type, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>; op2_kind>;
} }
multiclass VPatTernaryTA<string intrinsic, multiclass VPatTernaryTA_E<string intrinsic,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int sew, int log2sew,
LMULInfo vlmul, LMULInfo vlmul,
int sew,
VReg result_reg_class, VReg result_reg_class,
RegisterClass op1_reg_class, RegisterClass op1_reg_class,
DAGOperand op2_kind> { DAGOperand op2_kind> {
def : VPatTernaryNoMaskTA<intrinsic, inst, kind, result_type, op1_type, def : VPatTernaryNoMaskTA_E<intrinsic, inst, kind, result_type, op1_type,
op2_type, sew, vlmul, result_reg_class, op2_type, log2sew, vlmul, sew, result_reg_class,
op1_reg_class, op2_kind>;
def : VPatTernaryMaskTA<intrinsic, inst, kind, result_type, op1_type,
op2_type, mask_type, sew, vlmul, result_reg_class,
op1_reg_class, op2_kind>; op1_reg_class, op2_kind>;
def : VPatTernaryMaskTA_E<intrinsic, inst, kind, result_type, op1_type,
op2_type, mask_type, log2sew, vlmul, sew,
result_reg_class, op1_reg_class, op2_kind>;
} }
multiclass VPatTernaryV_VV_AAXA<string intrinsic, string instruction, multiclass VPatTernaryV_VV_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV", defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",
vti.Vector, vti.Vector, vti.Vector, vti.Mask, vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Linesmulticlass VPatBinaryV_VV_VX_VI_INT<string intrinsic, string instruction,
: VPatBinaryV_VV_INT_E<intrinsic#"_vv", instruction, vtilist>, : VPatBinaryV_VV_INT_E<intrinsic#"_vv", instruction, vtilist>,
VPatBinaryV_VX_INT<intrinsic#"_vx", instruction, vtilist>, VPatBinaryV_VX_INT<intrinsic#"_vx", instruction, vtilist>,
VPatBinaryV_VI<intrinsic#"_vx", instruction, vtilist, ImmType>; VPatBinaryV_VI<intrinsic#"_vx", instruction, vtilist, ImmType>;
multiclass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat = 0> { multiclass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat = 0> {
foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in
{ {
defvar vectorM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # vti.SEW # "M1"); defvar vectorM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # vti.SEW # "M1");
defm : VPatTernaryTA<intrinsic, instruction, "VS", defm : VPatTernaryTA_E<intrinsic, instruction, "VS",
vectorM1.Vector, vti.Vector, vectorM1.Vector, vti.Vector,
vectorM1.Vector, vti.Mask, vectorM1.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.Log2SEW, vti.LMul, vti.SEW,
VR, vti.RegClass, VR>; VR, vti.RegClass, VR>;
} }
foreach gvti = !if(IsFloat, GroupFloatVectors, GroupIntegerVectors) in foreach gvti = !if(IsFloat, GroupFloatVectors, GroupIntegerVectors) in
{ {
defm : VPatTernaryTA<intrinsic, instruction, "VS", defm : VPatTernaryTA_E<intrinsic, instruction, "VS",
gvti.VectorM1, gvti.Vector, gvti.VectorM1, gvti.Vector,
gvti.VectorM1, gvti.Mask, gvti.VectorM1, gvti.Mask,
gvti.Log2SEW, gvti.LMul, gvti.Log2SEW, gvti.LMul, gvti.SEW,
VR, gvti.RegClass, VR>; VR, gvti.RegClass, VR>;
} }
} }
multiclass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat = 0> { multiclass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat = 0> {
foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in
{ {
defvar wtiSEW = !mul(vti.SEW, 2); defvar wtiSEW = !mul(vti.SEW, 2);
if !le(wtiSEW, 64) then { if !le(wtiSEW, 64) then {
defvar wtiM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # wtiSEW # "M1"); defvar wtiM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # wtiSEW # "M1");
defm : VPatTernaryTA<intrinsic, instruction, "VS", defm : VPatTernaryTA_E<intrinsic, instruction, "VS",
wtiM1.Vector, vti.Vector, wtiM1.Vector, vti.Vector,
wtiM1.Vector, vti.Mask, wtiM1.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.Log2SEW, vti.LMul, vti.SEW,
wtiM1.RegClass, vti.RegClass, wtiM1.RegClass, vti.RegClass,
wtiM1.RegClass>; wtiM1.RegClass>;
} }
} }
} }
multiclass VPatConversionVI_VF<string intrinsic, multiclass VPatConversionVI_VF<string intrinsic,
string instruction> string instruction>
{ {
foreach fvti = AllFloatVectors in foreach fvti = AllFloatVectors in
▲ Show 20 Lines • Show All 1,478 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 1,102 Lines • ▼ Show 20 Lines
multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> {
foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in {
defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1");
def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge),
(vti.Vector vti.RegClass:$rs1), VR:$rs2, (vti.Vector vti.RegClass:$rs1), VR:$rs2,
(vti.Mask true_mask), VLOpFrag, (vti.Mask true_mask), VLOpFrag,
(XLenVT timm:$policy))), (XLenVT timm:$policy))),
(!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW)
(vti_m1.Vector VR:$merge), (vti_m1.Vector VR:$merge),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
(vti_m1.Vector VR:$rs2), (vti_m1.Vector VR:$rs2),
GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>; GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;
def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge),
(vti.Vector vti.RegClass:$rs1), VR:$rs2, (vti.Vector vti.RegClass:$rs1), VR:$rs2,
(vti.Mask V0), VLOpFrag, (vti.Mask V0), VLOpFrag,
(XLenVT timm:$policy))), (XLenVT timm:$policy))),
(!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")
(vti_m1.Vector VR:$merge), (vti_m1.Vector VR:$merge),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
(vti_m1.Vector VR:$rs2), (vti_m1.Vector VR:$rs2),
(vti.Mask V0), GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>; (vti.Mask V0), GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;
} }
} }
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesmulticlass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {
foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");
def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
(wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))),
VR:$rs2, (vti.Mask true_mask), VLOpFrag, VR:$rs2, (vti.Mask true_mask), VLOpFrag,
(XLenVT timm:$policy))), (XLenVT timm:$policy))),
(!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW)
(wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1),
(wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW, (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW,
(XLenVT timm:$policy))>; (XLenVT timm:$policy))>;
def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
(wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))),
VR:$rs2, (vti.Mask V0), VLOpFrag, VR:$rs2, (vti.Mask V0), VLOpFrag,
(XLenVT timm:$policy))), (XLenVT timm:$policy))),
(!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")
(wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1),
(wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW, (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW,
(XLenVT timm:$policy))>; (XLenVT timm:$policy))>;
} }
} }
multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {
foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");
def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
(wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)),
VR:$rs2, (vti.Mask true_mask), VLOpFrag, VR:$rs2, (vti.Mask true_mask), VLOpFrag,
(XLenVT timm:$policy))), (XLenVT timm:$policy))),
(!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW)
(wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1),
(wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW, (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW,
(XLenVT timm:$policy))>; (XLenVT timm:$policy))>;
def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge),
(wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)),
VR:$rs2, (vti.Mask V0), VLOpFrag, VR:$rs2, (vti.Mask V0), VLOpFrag,
(XLenVT timm:$policy))), (XLenVT timm:$policy))),
(!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")
(wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1),
(wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW, (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW,
(XLenVT timm:$policy))>; (XLenVT timm:$policy))>;
} }
} }
multiclass VPatWidenBinaryFPVL_VV_VF<SDNode op, PatFrags extop, string instruction_name> { multiclass VPatWidenBinaryFPVL_VV_VF<SDNode op, PatFrags extop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in { foreach fvtiToFWti = AllWidenableFloatVectors in {
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llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

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tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x10, $v8, $v26, $v27 liveins: $x10, $v8, $v26, $v27
; CHECK-LABEL: name: copy_with_widening_reduction ; CHECK-LABEL: name: copy_with_widening_reduction
; CHECK: liveins: $x10, $v8, $v26, $v27 ; CHECK: liveins: $x10, $v8, $v26, $v27
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x11 = PseudoVSETIVLI 1, 64 /* e8, m1, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x11 = PseudoVSETIVLI 1, 64 /* e8, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v8 = PseudoVWREDSUM_VS_M1 killed renamable $v8, killed renamable $v26, killed renamable $v27, 1, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = PseudoVWREDSUM_VS_M1_E8 killed renamable $v8, killed renamable $v26, killed renamable $v27, 1, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v26 = VMV1R_V killed $v8 ; CHECK-NEXT: $v26 = VMV1R_V killed $v8
; CHECK-NEXT: $x10 = PseudoVSETVLI killed renamable $x10, 75 /* e16, m8, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x10 = PseudoVSETVLI killed renamable $x10, 75 /* e16, m8, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v8m8 = VL8RE8_V killed $x10 ; CHECK-NEXT: $v8m8 = VL8RE8_V killed $x10
$x11 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype $x11 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype
$v8 = PseudoVWREDSUM_VS_M1 killed renamable $v8, killed renamable $v26, killed renamable $v27, 1, 3, 1, implicit $vl, implicit $vtype $v8 = PseudoVWREDSUM_VS_M1_E8 killed renamable $v8, killed renamable $v26, killed renamable $v27, 1, 3, 1, implicit $vl, implicit $vtype
$v26 = COPY killed renamable $v8 $v26 = COPY killed renamable $v8
$x10 = PseudoVSETVLI killed renamable $x10, 75, implicit-def $vl, implicit-def $vtype $x10 = PseudoVSETVLI killed renamable $x10, 75, implicit-def $vl, implicit-def $vtype
$v8m8 = VL8RE8_V killed $x10 $v8m8 = VL8RE8_V killed $x10
... ...
--- ---
name: copy_zvlsseg_reg name: copy_zvlsseg_reg
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
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llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

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; CHECK-LABEL: name: vsetvli_vcpop ; CHECK-LABEL: name: vsetvli_vcpop
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $x10, $x11 ; CHECK-NEXT: liveins: $x10, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
; CHECK-NEXT: dead %12:gpr = PseudoVSETVLIX0 $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead %13:gpr = PseudoVSETVLIX0 $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 0, -1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 0, -1, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PseudoVMSEQ_VI_MF2_:%[0-9]+]]:vmv0 = PseudoVMSEQ_VI_MF2 killed [[PseudoVID_V_MF2_]], 0, -1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMSEQ_VI_MF2_:%[0-9]+]]:vmv0 = PseudoVMSEQ_VI_MF2 killed [[PseudoVID_V_MF2_]], 0, -1, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v0 = COPY [[PseudoVMSEQ_VI_MF2_]] ; CHECK-NEXT: $v0 = COPY [[PseudoVMSEQ_VI_MF2_]]
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 23 /* e32, mf2, tu, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 23 /* e32, mf2, tu, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
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; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $x10, $x11 ; CHECK-NEXT: liveins: $x10, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB ; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: dead %11:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.1 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.1
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
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; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $x10, $x11 ; CHECK-NEXT: liveins: $x10, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB ; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: dead %11:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.2
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: BNE [[ADDI]], [[COPY4]], %bb.1 ; CHECK-NEXT: BNE [[ADDI]], [[COPY4]], %bb.1
; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: PseudoBR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.middle.block: ; CHECK-NEXT: bb.2.middle.block:
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVMV_S_X_M1_:%[0-9]+]]:vr = PseudoVMV_S_X_M1 [[DEF]], [[COPY5]], 1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_S_X_M1_:%[0-9]+]]:vr = PseudoVMV_S_X_M1 [[DEF]], [[COPY5]], 1, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1 [[DEF1]], [[PseudoVADD_VV_M1_]], killed [[PseudoVMV_S_X_M1_]], 4, 5 /* e32 */, 1 /* ta, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 [[DEF1]], [[PseudoVADD_VV_M1_]], killed [[PseudoVMV_S_X_M1_]], 4, 5 /* e32 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: PseudoVSE32_V_M1 killed [[PseudoVREDSUM_VS_M1_]], [[COPY]], 1, 5 /* e32 */, implicit $vl, implicit $vtype :: (store (s32) into %ir.res) ; CHECK-NEXT: PseudoVSE32_V_M1 killed [[PseudoVREDSUM_VS_M1_E8_]], [[COPY]], 1, 5 /* e32 */, implicit $vl, implicit $vtype :: (store (s32) into %ir.res)
; CHECK-NEXT: PseudoRET ; CHECK-NEXT: PseudoRET
bb.0.entry: bb.0.entry:
liveins: $x10, $x12 liveins: $x10, $x12
%8:gpr = COPY $x12 %8:gpr = COPY $x12
%6:gpr = COPY $x10 %6:gpr = COPY $x10
%11:vr = PseudoVMV_V_I_M1 0, 4, 5 %11:vr = PseudoVMV_V_I_M1 0, 4, 5
%12:vr = COPY %11 %12:vr = COPY %11
Show All 15 Lines bb.1.vector.body:
BNE %4, %18, %bb.1 BNE %4, %18, %bb.1
PseudoBR %bb.2 PseudoBR %bb.2
bb.2.middle.block: bb.2.middle.block:
%19:gpr = COPY $x0 %19:gpr = COPY $x0
%21:vr = IMPLICIT_DEF %21:vr = IMPLICIT_DEF
%20:vr = PseudoVMV_S_X_M1 %21, %19, 1, 5 %20:vr = PseudoVMV_S_X_M1 %21, %19, 1, 5
%24:vr = IMPLICIT_DEF %24:vr = IMPLICIT_DEF
%23:vr = PseudoVREDSUM_VS_M1 %24, %16, killed %20, 4, 5, 1 %23:vr = PseudoVREDSUM_VS_M1_E8 %24, %16, killed %20, 4, 5, 1
PseudoVSE32_V_M1 killed %23, %8, 1, 5 :: (store (s32) into %ir.res) PseudoVSE32_V_M1 killed %23, %8, 1, 5 :: (store (s32) into %ir.res)
PseudoRET PseudoRET
... ...
--- ---
name: vsetvli_vluxei64_regression name: vsetvli_vluxei64_regression
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: vsetvli_vluxei64_regression ; CHECK-LABEL: name: vsetvli_vluxei64_regression
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $x10, $x11, $x12, $v0, $v1, $v2, $v3 ; CHECK-NEXT: liveins: $x10, $x11, $x12, $v0, $v1, $v2, $v3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:gpr = COPY $x10 ; CHECK-NEXT: %a:gpr = COPY $x10
; CHECK-NEXT: %b:gpr = COPY $x11 ; CHECK-NEXT: %b:gpr = COPY $x11
; CHECK-NEXT: %inaddr:gpr = COPY $x12 ; CHECK-NEXT: %inaddr:gpr = COPY $x12
; CHECK-NEXT: %idxs:vr = COPY $v0 ; CHECK-NEXT: %idxs:vr = COPY $v0
; CHECK-NEXT: %t1:vr = COPY $v1 ; CHECK-NEXT: %t1:vr = COPY $v1
; CHECK-NEXT: %t3:vr = COPY $v2 ; CHECK-NEXT: %t3:vr = COPY $v2
; CHECK-NEXT: %t4:vr = COPY $v3 ; CHECK-NEXT: %t4:vr = COPY $v3
; CHECK-NEXT: %t5:vrnov0 = COPY $v1 ; CHECK-NEXT: %t5:vrnov0 = COPY $v1
; CHECK-NEXT: dead %14:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_MF8 %t6, %t3, -1, 0 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_MF8 %t6, %t3, -1, 0 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: %t2:gpr = COPY $x0 ; CHECK-NEXT: %t2:gpr = COPY $x0
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; CHECK-NEXT: %dst:gpr = COPY $x10 ; CHECK-NEXT: %dst:gpr = COPY $x10
; CHECK-NEXT: %src:gpr = COPY $x11 ; CHECK-NEXT: %src:gpr = COPY $x11
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12
; CHECK-NEXT: %tc:gpr = COPY $x13 ; CHECK-NEXT: %tc:gpr = COPY $x13
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x14 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x14
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x15 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x15
; CHECK-NEXT: %vlenb:gpr = PseudoReadVLENB ; CHECK-NEXT: %vlenb:gpr = PseudoReadVLENB
; CHECK-NEXT: %inc:gpr = SRLI killed %vlenb, 3 ; CHECK-NEXT: %inc:gpr = SRLI killed %vlenb, 3
; CHECK-NEXT: dead %21:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.0, %11, %bb.3 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.0, %11, %bb.3
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llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

Show First 20 Lines • Show All 301 Lines • ▼ Show 20 Lines bb.0 (%ir-block.0):
liveins: $x10 liveins: $x10
; CHECK-LABEL: name: vreduce_add_v2i64 ; CHECK-LABEL: name: vreduce_add_v2i64
; CHECK: liveins: $x10 ; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[COPY]], 2, 6 /* e64 */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x) ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[COPY]], 2, 6 /* e64 */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x)
; CHECK-NEXT: dead %6:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1 [[DEF]], killed [[PseudoVLE64_V_M1_]], killed [[PseudoVMV_V_I_M1_]], 2, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 [[DEF]], killed [[PseudoVLE64_V_M1_]], killed [[PseudoVMV_V_I_M1_]], 2, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 killed [[PseudoVREDSUM_VS_M1_]], 6 /* e64 */, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 killed [[PseudoVREDSUM_VS_M1_E8_]], 6 /* e64 */, implicit $vtype
; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S_M1_]] ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S_M1_]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:gpr = COPY $x10 %0:gpr = COPY $x10
%1:vr = PseudoVLE64_V_M1 %0, 2, 6 :: (load (s128) from %ir.x) %1:vr = PseudoVLE64_V_M1 %0, 2, 6 :: (load (s128) from %ir.x)
%2:vr = PseudoVMV_V_I_M1 0, -1, 6 %2:vr = PseudoVMV_V_I_M1 0, -1, 6
%4:vr = IMPLICIT_DEF %4:vr = IMPLICIT_DEF
%3:vr = PseudoVREDSUM_VS_M1 %4, killed %1, killed %2, 2, 6, 1 %3:vr = PseudoVREDSUM_VS_M1_E8 %4, killed %1, killed %2, 2, 6, 1
%5:gpr = PseudoVMV_X_S_M1 killed %3, 6 %5:gpr = PseudoVMV_X_S_M1 killed %3, 6
$x10 = COPY %5 $x10 = COPY %5
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: vsetvli_add name: vsetvli_add
alignment: 4 alignment: 4
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