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Differential D146933

[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
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Authored by asb on Mar 26 2023, 11:26 PM.

Details

Reviewers
reames
craig.topper
Commits
rG5b0705961841: [RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping…
Summary

Table A.6 in the RISC-V ISA Manual indicates that sequentially consistent atomic ops that have a matching instruction should be mapped to amo<op>.{w|d}.aqrl. But sequentially consistent operations that are mapped to lr/sc should produce loop: lr.{w|d}.aqrl; <op>; sc.{w|d}.rl; bnez loop. Previously, LLVM produced an sc.{w|d}.aqrl which was stronger than necessary. This patch adjusts the relevant logic so that a sc.{w|d}.rl is produced.

Diff Detail

Event Timeline

asb created this revision.Mar 26 2023, 11:26 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 26 2023, 11:26 PM
Herald added subscribers: jobnoorman, luke, wingo and 30 others. · View Herald Transcript
asb requested review of this revision.Mar 26 2023, 11:26 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 26 2023, 11:26 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B221889: Diff 508489.Mar 27 2023, 12:22 AM
craig.topper accepted this revision.Mar 29 2023, 10:17 AM

LGTM

This revision is now accepted and ready to land.Mar 29 2023, 10:17 AM
Closed by commit rG5b0705961841: [RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping… (authored by asb). · Explain WhyMar 30 2023, 12:48 PM
This revision was automatically updated to reflect the committed changes.
asb added a commit: rG5b0705961841: [RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping….

Revision Contents

Diff 508489

llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp

Show First 20 Lines • Show All 172 Lines • ▼ Show 20 Lines case AtomicOrdering::Monotonic:
return RISCV::SC_W; return RISCV::SC_W;
case AtomicOrdering::Acquire: case AtomicOrdering::Acquire:
return RISCV::SC_W; return RISCV::SC_W;
case AtomicOrdering::Release: case AtomicOrdering::Release:
return RISCV::SC_W_RL; return RISCV::SC_W_RL;
case AtomicOrdering::AcquireRelease: case AtomicOrdering::AcquireRelease:
return RISCV::SC_W_RL; return RISCV::SC_W_RL;
case AtomicOrdering::SequentiallyConsistent: case AtomicOrdering::SequentiallyConsistent:
return RISCV::SC_W_AQ_RL; return RISCV::SC_W_RL;
} }
} }
static unsigned getLRForRMW64(AtomicOrdering Ordering) { static unsigned getLRForRMW64(AtomicOrdering Ordering) {
switch (Ordering) { switch (Ordering) {
default: default:
llvm_unreachable("Unexpected AtomicOrdering"); llvm_unreachable("Unexpected AtomicOrdering");
case AtomicOrdering::Monotonic: case AtomicOrdering::Monotonic:
Show All 17 Lines case AtomicOrdering::Monotonic:
return RISCV::SC_D; return RISCV::SC_D;
case AtomicOrdering::Acquire: case AtomicOrdering::Acquire:
return RISCV::SC_D; return RISCV::SC_D;
case AtomicOrdering::Release: case AtomicOrdering::Release:
return RISCV::SC_D_RL; return RISCV::SC_D_RL;
case AtomicOrdering::AcquireRelease: case AtomicOrdering::AcquireRelease:
return RISCV::SC_D_RL; return RISCV::SC_D_RL;
case AtomicOrdering::SequentiallyConsistent: case AtomicOrdering::SequentiallyConsistent:
return RISCV::SC_D_AQ_RL; return RISCV::SC_D_RL;
} }
} }
static unsigned getLRForRMW(AtomicOrdering Ordering, int Width) { static unsigned getLRForRMW(AtomicOrdering Ordering, int Width) {
if (Width == 32) if (Width == 32)
return getLRForRMW32(Ordering); return getLRForRMW32(Ordering);
if (Width == 64) if (Width == 64)
return getLRForRMW64(Ordering); return getLRForRMW64(Ordering);
▲ Show 20 Lines • Show All 477 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll

Show All 14 Lines
; CHECK-NEXT: # Child Loop BB0_3 Depth 2 ; CHECK-NEXT: # Child Loop BB0_3 Depth 2
; CHECK-NEXT: .LBB0_3: # %do_cmpxchg ; CHECK-NEXT: .LBB0_3: # %do_cmpxchg
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 ; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: lr.w.aqrl a3, (a0) ; CHECK-NEXT: lr.w.aqrl a3, (a0)
; CHECK-NEXT: bne a3, a1, .LBB0_1 ; CHECK-NEXT: bne a3, a1, .LBB0_1
; CHECK-NEXT: # %bb.4: # %do_cmpxchg ; CHECK-NEXT: # %bb.4: # %do_cmpxchg
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=2 ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=2
; CHECK-NEXT: sc.w.aqrl a4, a2, (a0) ; CHECK-NEXT: sc.w.rl a4, a2, (a0)
; CHECK-NEXT: bnez a4, .LBB0_3 ; CHECK-NEXT: bnez a4, .LBB0_3
; CHECK-NEXT: # %bb.5: # %do_cmpxchg ; CHECK-NEXT: # %bb.5: # %do_cmpxchg
; CHECK-NEXT: # %bb.2: # %exit ; CHECK-NEXT: # %bb.2: # %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %do_cmpxchg br label %do_cmpxchg
do_cmpxchg: do_cmpxchg:
%0 = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst %0 = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst
Show All 11 Lines
; CHECK-NEXT: # Child Loop BB1_3 Depth 2 ; CHECK-NEXT: # Child Loop BB1_3 Depth 2
; CHECK-NEXT: .LBB1_3: # %do_cmpxchg ; CHECK-NEXT: .LBB1_3: # %do_cmpxchg
; CHECK-NEXT: # Parent Loop BB1_1 Depth=1 ; CHECK-NEXT: # Parent Loop BB1_1 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: lr.w.aqrl a3, (a0) ; CHECK-NEXT: lr.w.aqrl a3, (a0)
; CHECK-NEXT: bne a3, a1, .LBB1_5 ; CHECK-NEXT: bne a3, a1, .LBB1_5
; CHECK-NEXT: # %bb.4: # %do_cmpxchg ; CHECK-NEXT: # %bb.4: # %do_cmpxchg
; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=2 ; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=2
; CHECK-NEXT: sc.w.aqrl a4, a2, (a0) ; CHECK-NEXT: sc.w.rl a4, a2, (a0)
; CHECK-NEXT: bnez a4, .LBB1_3 ; CHECK-NEXT: bnez a4, .LBB1_3
; CHECK-NEXT: .LBB1_5: # %do_cmpxchg ; CHECK-NEXT: .LBB1_5: # %do_cmpxchg
; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1
; CHECK-NEXT: beq a3, a1, .LBB1_1 ; CHECK-NEXT: beq a3, a1, .LBB1_1
; CHECK-NEXT: # %bb.2: # %exit ; CHECK-NEXT: # %bb.2: # %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %do_cmpxchg br label %do_cmpxchg
Show All 25 Lines
; RV32IA-NEXT: lr.w.aqrl a4, (a3) ; RV32IA-NEXT: lr.w.aqrl a4, (a3)
; RV32IA-NEXT: and a5, a4, a0 ; RV32IA-NEXT: and a5, a4, a0
; RV32IA-NEXT: bne a5, a1, .LBB2_1 ; RV32IA-NEXT: bne a5, a1, .LBB2_1
; RV32IA-NEXT: # %bb.4: # %do_cmpxchg ; RV32IA-NEXT: # %bb.4: # %do_cmpxchg
; RV32IA-NEXT: # in Loop: Header=BB2_3 Depth=2 ; RV32IA-NEXT: # in Loop: Header=BB2_3 Depth=2
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a5, a4, a2
; RV32IA-NEXT: and a5, a5, a0 ; RV32IA-NEXT: and a5, a5, a0
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB2_3 ; RV32IA-NEXT: bnez a5, .LBB2_3
; RV32IA-NEXT: # %bb.5: # %do_cmpxchg ; RV32IA-NEXT: # %bb.5: # %do_cmpxchg
; RV32IA-NEXT: # %bb.2: # %exit ; RV32IA-NEXT: # %bb.2: # %exit
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_masked_and_branch1: ; RV64IA-LABEL: cmpxchg_masked_and_branch1:
; RV64IA: # %bb.0: # %entry ; RV64IA: # %bb.0: # %entry
; RV64IA-NEXT: andi a3, a0, -4 ; RV64IA-NEXT: andi a3, a0, -4
Show All 13 Lines
; RV64IA-NEXT: lr.w.aqrl a4, (a3) ; RV64IA-NEXT: lr.w.aqrl a4, (a3)
; RV64IA-NEXT: and a5, a4, a0 ; RV64IA-NEXT: and a5, a4, a0
; RV64IA-NEXT: bne a5, a1, .LBB2_1 ; RV64IA-NEXT: bne a5, a1, .LBB2_1
; RV64IA-NEXT: # %bb.4: # %do_cmpxchg ; RV64IA-NEXT: # %bb.4: # %do_cmpxchg
; RV64IA-NEXT: # in Loop: Header=BB2_3 Depth=2 ; RV64IA-NEXT: # in Loop: Header=BB2_3 Depth=2
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a5, a4, a2
; RV64IA-NEXT: and a5, a5, a0 ; RV64IA-NEXT: and a5, a5, a0
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB2_3 ; RV64IA-NEXT: bnez a5, .LBB2_3
; RV64IA-NEXT: # %bb.5: # %do_cmpxchg ; RV64IA-NEXT: # %bb.5: # %do_cmpxchg
; RV64IA-NEXT: # %bb.2: # %exit ; RV64IA-NEXT: # %bb.2: # %exit
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
entry: entry:
br label %do_cmpxchg br label %do_cmpxchg
do_cmpxchg: do_cmpxchg:
%0 = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst seq_cst %0 = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst seq_cst
Show All 23 Lines
; RV32IA-NEXT: lr.w.aqrl a4, (a3) ; RV32IA-NEXT: lr.w.aqrl a4, (a3)
; RV32IA-NEXT: and a5, a4, a0 ; RV32IA-NEXT: and a5, a4, a0
; RV32IA-NEXT: bne a5, a1, .LBB3_5 ; RV32IA-NEXT: bne a5, a1, .LBB3_5
; RV32IA-NEXT: # %bb.4: # %do_cmpxchg ; RV32IA-NEXT: # %bb.4: # %do_cmpxchg
; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=2 ; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=2
; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: xor a5, a4, a2
; RV32IA-NEXT: and a5, a5, a0 ; RV32IA-NEXT: and a5, a5, a0
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB3_3 ; RV32IA-NEXT: bnez a5, .LBB3_3
; RV32IA-NEXT: .LBB3_5: # %do_cmpxchg ; RV32IA-NEXT: .LBB3_5: # %do_cmpxchg
; RV32IA-NEXT: # in Loop: Header=BB3_1 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB3_1 Depth=1
; RV32IA-NEXT: and a4, a4, a0 ; RV32IA-NEXT: and a4, a4, a0
; RV32IA-NEXT: beq a1, a4, .LBB3_1 ; RV32IA-NEXT: beq a1, a4, .LBB3_1
; RV32IA-NEXT: # %bb.2: # %exit ; RV32IA-NEXT: # %bb.2: # %exit
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
Show All 16 Lines
; RV64IA-NEXT: lr.w.aqrl a4, (a3) ; RV64IA-NEXT: lr.w.aqrl a4, (a3)
; RV64IA-NEXT: and a5, a4, a0 ; RV64IA-NEXT: and a5, a4, a0
; RV64IA-NEXT: bne a5, a1, .LBB3_5 ; RV64IA-NEXT: bne a5, a1, .LBB3_5
; RV64IA-NEXT: # %bb.4: # %do_cmpxchg ; RV64IA-NEXT: # %bb.4: # %do_cmpxchg
; RV64IA-NEXT: # in Loop: Header=BB3_3 Depth=2 ; RV64IA-NEXT: # in Loop: Header=BB3_3 Depth=2
; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: xor a5, a4, a2
; RV64IA-NEXT: and a5, a5, a0 ; RV64IA-NEXT: and a5, a5, a0
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB3_3 ; RV64IA-NEXT: bnez a5, .LBB3_3
; RV64IA-NEXT: .LBB3_5: # %do_cmpxchg ; RV64IA-NEXT: .LBB3_5: # %do_cmpxchg
; RV64IA-NEXT: # in Loop: Header=BB3_1 Depth=1 ; RV64IA-NEXT: # in Loop: Header=BB3_1 Depth=1
; RV64IA-NEXT: and a4, a4, a0 ; RV64IA-NEXT: and a4, a4, a0
; RV64IA-NEXT: beq a1, a4, .LBB3_1 ; RV64IA-NEXT: beq a1, a4, .LBB3_1
; RV64IA-NEXT: # %bb.2: # %exit ; RV64IA-NEXT: # %bb.2: # %exit
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
entry: entry:
Show All 14 Lines
; CHECK-NEXT: # Child Loop BB4_3 Depth 2 ; CHECK-NEXT: # Child Loop BB4_3 Depth 2
; CHECK-NEXT: .LBB4_3: # %do_cmpxchg ; CHECK-NEXT: .LBB4_3: # %do_cmpxchg
; CHECK-NEXT: # Parent Loop BB4_1 Depth=1 ; CHECK-NEXT: # Parent Loop BB4_1 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: lr.w.aqrl a4, (a0) ; CHECK-NEXT: lr.w.aqrl a4, (a0)
; CHECK-NEXT: bne a4, a1, .LBB4_5 ; CHECK-NEXT: bne a4, a1, .LBB4_5
; CHECK-NEXT: # %bb.4: # %do_cmpxchg ; CHECK-NEXT: # %bb.4: # %do_cmpxchg
; CHECK-NEXT: # in Loop: Header=BB4_3 Depth=2 ; CHECK-NEXT: # in Loop: Header=BB4_3 Depth=2
; CHECK-NEXT: sc.w.aqrl a5, a2, (a0) ; CHECK-NEXT: sc.w.rl a5, a2, (a0)
; CHECK-NEXT: bnez a5, .LBB4_3 ; CHECK-NEXT: bnez a5, .LBB4_3
; CHECK-NEXT: .LBB4_5: # %do_cmpxchg ; CHECK-NEXT: .LBB4_5: # %do_cmpxchg
; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1
; CHECK-NEXT: beqz a3, .LBB4_1 ; CHECK-NEXT: beqz a3, .LBB4_1
; CHECK-NEXT: # %bb.2: # %exit ; CHECK-NEXT: # %bb.2: # %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %do_cmpxchg br label %do_cmpxchg
do_cmpxchg: do_cmpxchg:
%0 = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst %0 = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst
%1 = extractvalue { i32, i1 } %0, 1 %1 = extractvalue { i32, i1 } %0, 1
br i1 %bool, label %exit, label %do_cmpxchg br i1 %bool, label %exit, label %do_cmpxchg
exit: exit:
ret void ret void
} }

llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll

Show All 9 Lines
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA: # %bb.0: # %entry ; RV64IA: # %bb.0: # %entry
; RV64IA-NEXT: .LBB0_1: # %entry ; RV64IA-NEXT: .LBB0_1: # %entry
; RV64IA-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB0_3 ; RV64IA-NEXT: bne a3, a1, .LBB0_3
; RV64IA-NEXT: # %bb.2: # %entry ; RV64IA-NEXT: # %bb.2: # %entry
; RV64IA-NEXT: # in Loop: Header=BB0_1 Depth=1 ; RV64IA-NEXT: # in Loop: Header=BB0_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB0_1 ; RV64IA-NEXT: bnez a4, .LBB0_1
; RV64IA-NEXT: .LBB0_3: # %entry ; RV64IA-NEXT: .LBB0_3: # %entry
; RV64IA-NEXT: xor a1, a3, a1 ; RV64IA-NEXT: xor a1, a3, a1
; RV64IA-NEXT: seqz a0, a1 ; RV64IA-NEXT: seqz a0, a1
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
i32 signext %val) nounwind { i32 signext %val) nounwind {
entry: entry:
%0 = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst %0 = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst
%1 = extractvalue { i32, i1 } %0, 1 %1 = extractvalue { i32, i1 } %0, 1
ret i1 %1 ret i1 %1
} }

llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll

Show First 20 Lines • Show All 570 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a5, a2, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB7_3 ; RV32IA-NEXT: bne a5, a1, .LBB7_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
; RV32IA-NEXT: xor a5, a2, a0 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a2, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB7_1 ; RV32IA-NEXT: bnez a5, .LBB7_1
; RV32IA-NEXT: .LBB7_3: ; RV32IA-NEXT: .LBB7_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i8_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
Show All 19 Lines
; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a5, a2, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB7_3 ; RV64IA-NEXT: bne a5, a1, .LBB7_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
; RV64IA-NEXT: xor a5, a2, a0 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a2, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB7_1 ; RV64IA-NEXT: bnez a5, .LBB7_1
; RV64IA-NEXT: .LBB7_3: ; RV64IA-NEXT: .LBB7_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst monotonic %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
Show All 23 Lines
; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a5, a2, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB8_3 ; RV32IA-NEXT: bne a5, a1, .LBB8_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
; RV32IA-NEXT: xor a5, a2, a0 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a2, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB8_1 ; RV32IA-NEXT: bnez a5, .LBB8_1
; RV32IA-NEXT: .LBB8_3: ; RV32IA-NEXT: .LBB8_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i8_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a5, a2, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB8_3 ; RV64IA-NEXT: bne a5, a1, .LBB8_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
; RV64IA-NEXT: xor a5, a2, a0 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a2, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB8_1 ; RV64IA-NEXT: bnez a5, .LBB8_1
; RV64IA-NEXT: .LBB8_3: ; RV64IA-NEXT: .LBB8_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst acquire %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i8_seq_cst_seq_cst(ptr %ptr, i8 %cmp, i8 %val) nounwind { define void @cmpxchg_i8_seq_cst_seq_cst(ptr %ptr, i8 %cmp, i8 %val) nounwind {
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; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a5, a2, a4 ; RV32IA-NEXT: and a5, a2, a4
; RV32IA-NEXT: bne a5, a1, .LBB9_3 ; RV32IA-NEXT: bne a5, a1, .LBB9_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
; RV32IA-NEXT: xor a5, a2, a0 ; RV32IA-NEXT: xor a5, a2, a0
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a2, a5 ; RV32IA-NEXT: xor a5, a2, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
; RV32IA-NEXT: bnez a5, .LBB9_1 ; RV32IA-NEXT: bnez a5, .LBB9_1
; RV32IA-NEXT: .LBB9_3: ; RV32IA-NEXT: .LBB9_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i8_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a5, a2, a4 ; RV64IA-NEXT: and a5, a2, a4
; RV64IA-NEXT: bne a5, a1, .LBB9_3 ; RV64IA-NEXT: bne a5, a1, .LBB9_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
; RV64IA-NEXT: xor a5, a2, a0 ; RV64IA-NEXT: xor a5, a2, a0
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a2, a5 ; RV64IA-NEXT: xor a5, a2, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a3) ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
; RV64IA-NEXT: bnez a5, .LBB9_1 ; RV64IA-NEXT: bnez a5, .LBB9_1
; RV64IA-NEXT: .LBB9_3: ; RV64IA-NEXT: .LBB9_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst seq_cst %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i16_monotonic_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_monotonic_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind {
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; RV32IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a4, a2, a5 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a4, a1, .LBB17_3 ; RV32IA-NEXT: bne a4, a1, .LBB17_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
; RV32IA-NEXT: xor a4, a2, a0 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a4, a4, a5 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a4, a2, a4 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB17_1 ; RV32IA-NEXT: bnez a4, .LBB17_1
; RV32IA-NEXT: .LBB17_3: ; RV32IA-NEXT: .LBB17_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i16_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a4, a2, a5 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a4, a1, .LBB17_3 ; RV64IA-NEXT: bne a4, a1, .LBB17_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
; RV64IA-NEXT: xor a4, a2, a0 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a4, a4, a5 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a4, a2, a4 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
; RV64IA-NEXT: bnez a4, .LBB17_1 ; RV64IA-NEXT: bnez a4, .LBB17_1
; RV64IA-NEXT: .LBB17_3: ; RV64IA-NEXT: .LBB17_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst monotonic %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind {
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; RV32IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a4, a2, a5 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a4, a1, .LBB18_3 ; RV32IA-NEXT: bne a4, a1, .LBB18_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
; RV32IA-NEXT: xor a4, a2, a0 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a4, a4, a5 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a4, a2, a4 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB18_1 ; RV32IA-NEXT: bnez a4, .LBB18_1
; RV32IA-NEXT: .LBB18_3: ; RV32IA-NEXT: .LBB18_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i16_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a4, a2, a5 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a4, a1, .LBB18_3 ; RV64IA-NEXT: bne a4, a1, .LBB18_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
; RV64IA-NEXT: xor a4, a2, a0 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a4, a4, a5 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a4, a2, a4 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
; RV64IA-NEXT: bnez a4, .LBB18_1 ; RV64IA-NEXT: bnez a4, .LBB18_1
; RV64IA-NEXT: .LBB18_3: ; RV64IA-NEXT: .LBB18_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst acquire %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind { define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind {
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; RV32IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a3) ; RV32IA-NEXT: lr.w.aqrl a2, (a3)
; RV32IA-NEXT: and a4, a2, a5 ; RV32IA-NEXT: and a4, a2, a5
; RV32IA-NEXT: bne a4, a1, .LBB19_3 ; RV32IA-NEXT: bne a4, a1, .LBB19_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
; RV32IA-NEXT: xor a4, a2, a0 ; RV32IA-NEXT: xor a4, a2, a0
; RV32IA-NEXT: and a4, a4, a5 ; RV32IA-NEXT: and a4, a4, a5
; RV32IA-NEXT: xor a4, a2, a4 ; RV32IA-NEXT: xor a4, a2, a4
; RV32IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
; RV32IA-NEXT: bnez a4, .LBB19_1 ; RV32IA-NEXT: bnez a4, .LBB19_1
; RV32IA-NEXT: .LBB19_3: ; RV32IA-NEXT: .LBB19_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i16_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a3) ; RV64IA-NEXT: lr.w.aqrl a2, (a3)
; RV64IA-NEXT: and a4, a2, a5 ; RV64IA-NEXT: and a4, a2, a5
; RV64IA-NEXT: bne a4, a1, .LBB19_3 ; RV64IA-NEXT: bne a4, a1, .LBB19_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
; RV64IA-NEXT: xor a4, a2, a0 ; RV64IA-NEXT: xor a4, a2, a0
; RV64IA-NEXT: and a4, a4, a5 ; RV64IA-NEXT: and a4, a4, a5
; RV64IA-NEXT: xor a4, a2, a4 ; RV64IA-NEXT: xor a4, a2, a4
; RV64IA-NEXT: sc.w.aqrl a4, a4, (a3) ; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
; RV64IA-NEXT: bnez a4, .LBB19_1 ; RV64IA-NEXT: bnez a4, .LBB19_1
; RV64IA-NEXT: .LBB19_3: ; RV64IA-NEXT: .LBB19_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst seq_cst %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind {
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; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV32IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB27_3 ; RV32IA-NEXT: bne a3, a1, .LBB27_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB27_1 ; RV32IA-NEXT: bnez a4, .LBB27_1
; RV32IA-NEXT: .LBB27_3: ; RV32IA-NEXT: .LBB27_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV64I-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB27_3 ; RV64IA-NEXT: bne a3, a1, .LBB27_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB27_1 ; RV64IA-NEXT: bnez a4, .LBB27_1
; RV64IA-NEXT: .LBB27_3: ; RV64IA-NEXT: .LBB27_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst monotonic %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind {
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; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV32IA-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB28_3 ; RV32IA-NEXT: bne a3, a1, .LBB28_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB28_1 ; RV32IA-NEXT: bnez a4, .LBB28_1
; RV32IA-NEXT: .LBB28_3: ; RV32IA-NEXT: .LBB28_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV64I-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB28_3 ; RV64IA-NEXT: bne a3, a1, .LBB28_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB28_1 ; RV64IA-NEXT: bnez a4, .LBB28_1
; RV64IA-NEXT: .LBB28_3: ; RV64IA-NEXT: .LBB28_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst acquire %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind { define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind {
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; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV32IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a0) ; RV32IA-NEXT: lr.w.aqrl a3, (a0)
; RV32IA-NEXT: bne a3, a1, .LBB29_3 ; RV32IA-NEXT: bne a3, a1, .LBB29_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
; RV32IA-NEXT: bnez a4, .LBB29_1 ; RV32IA-NEXT: bnez a4, .LBB29_1
; RV32IA-NEXT: .LBB29_3: ; RV32IA-NEXT: .LBB29_3:
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64I-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sw a1, 4(sp) ; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4 ; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: sext.w a1, a1
; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0) ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB29_3 ; RV64IA-NEXT: bne a3, a1, .LBB29_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB29_1 ; RV64IA-NEXT: bnez a4, .LBB29_1
; RV64IA-NEXT: .LBB29_3: ; RV64IA-NEXT: .LBB29_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst
ret void ret void
} }
define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind {
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; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic: ; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a3, (a0) ; RV64IA-NEXT: lr.d.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB37_3 ; RV64IA-NEXT: bne a3, a1, .LBB37_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB37_1 ; RV64IA-NEXT: bnez a4, .LBB37_1
; RV64IA-NEXT: .LBB37_3: ; RV64IA-NEXT: .LBB37_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst monotonic %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst monotonic
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind {
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; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire: ; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a3, (a0) ; RV64IA-NEXT: lr.d.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB38_3 ; RV64IA-NEXT: bne a3, a1, .LBB38_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB38_1 ; RV64IA-NEXT: bnez a4, .LBB38_1
; RV64IA-NEXT: .LBB38_3: ; RV64IA-NEXT: .LBB38_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst acquire %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst acquire
ret void ret void
} }
define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind { define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind {
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; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a3, (a0) ; RV64IA-NEXT: lr.d.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB39_3 ; RV64IA-NEXT: bne a3, a1, .LBB39_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0) ; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB39_1 ; RV64IA-NEXT: bnez a4, .LBB39_1
; RV64IA-NEXT: .LBB39_3: ; RV64IA-NEXT: .LBB39_3:
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst seq_cst %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst seq_cst
ret void ret void
} }

llvm/test/CodeGen/RISCV/atomic-rmw.ll

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; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: mv a5, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB4_1 ; RV32IA-NEXT: bnez a5, .LBB4_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
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; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: mv a5, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB4_1 ; RV64IA-NEXT: bnez a5, .LBB4_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b seq_cst %1 = atomicrmw xchg ptr %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
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; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: add a5, a4, a1 ; RV32IA-NEXT: add a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB9_1 ; RV32IA-NEXT: bnez a5, .LBB9_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i8_seq_cst: ; RV64I-LABEL: atomicrmw_add_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
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; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: add a5, a4, a1 ; RV64IA-NEXT: add a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB9_1 ; RV64IA-NEXT: bnez a5, .LBB9_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b seq_cst %1 = atomicrmw add ptr %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
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; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: sub a5, a4, a1 ; RV32IA-NEXT: sub a5, a4, a1
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB14_1 ; RV32IA-NEXT: bnez a5, .LBB14_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
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; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: sub a5, a4, a1 ; RV64IA-NEXT: sub a5, a4, a1
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB14_1 ; RV64IA-NEXT: bnez a5, .LBB14_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b seq_cst %1 = atomicrmw sub ptr %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
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; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a2) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: and a5, a4, a1 ; RV32IA-NEXT: and a5, a4, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB24_1 ; RV32IA-NEXT: bnez a5, .LBB24_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
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; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a2) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: and a5, a4, a1 ; RV64IA-NEXT: and a5, a4, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB24_1 ; RV64IA-NEXT: bnez a5, .LBB24_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b seq_cst %1 = atomicrmw nand ptr %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
▲ Show 20 Lines • Show All 1,082 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: sll a7, a7, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a7, a7, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a7, a1, .LBB39_3 ; RV32IA-NEXT: bge a7, a1, .LBB39_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV32IA-NEXT: xor a6, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a6, a6, a4 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a6, a5, a6 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1 ; RV32IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a6, a6, (a2) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a6, .LBB39_1 ; RV32IA-NEXT: bnez a6, .LBB39_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_seq_cst: ; RV64I-LABEL: atomicrmw_max_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; RV64IA-NEXT: sll a7, a7, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a7, a7, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a7, a1, .LBB39_3 ; RV64IA-NEXT: bge a7, a1, .LBB39_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: xor a6, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a6, a6, a4 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a6, a5, a6 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1 ; RV64IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a6, a6, (a2) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a6, .LBB39_1 ; RV64IA-NEXT: bnez a6, .LBB39_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b seq_cst %1 = atomicrmw max ptr %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
▲ Show 20 Lines • Show All 642 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: sll a7, a7, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a7, a7, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a7, .LBB44_3 ; RV32IA-NEXT: bge a1, a7, .LBB44_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1
; RV32IA-NEXT: xor a6, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a6, a6, a4 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a6, a5, a6 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1 ; RV32IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a6, a6, (a2) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a6, .LBB44_1 ; RV32IA-NEXT: bnez a6, .LBB44_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_seq_cst: ; RV64I-LABEL: atomicrmw_min_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; RV64IA-NEXT: sll a7, a7, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a7, a7, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a7, .LBB44_3 ; RV64IA-NEXT: bge a1, a7, .LBB44_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1
; RV64IA-NEXT: xor a6, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a6, a6, a4 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a6, a5, a6 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1 ; RV64IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a6, a6, (a2) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a6, .LBB44_1 ; RV64IA-NEXT: bnez a6, .LBB44_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b seq_cst %1 = atomicrmw min ptr %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
▲ Show 20 Lines • Show All 579 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: and a6, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a6, a1, .LBB49_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB49_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 ; RV32IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB49_1 ; RV32IA-NEXT: bnez a5, .LBB49_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; RV64IA-NEXT: and a6, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a6, a1, .LBB49_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB49_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 ; RV64IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB49_1 ; RV64IA-NEXT: bnez a5, .LBB49_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b seq_cst %1 = atomicrmw umax ptr %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
▲ Show 20 Lines • Show All 579 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: and a6, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a6, .LBB54_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB54_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 ; RV32IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB54_1 ; RV32IA-NEXT: bnez a5, .LBB54_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; RV64IA-NEXT: and a6, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a6, .LBB54_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB54_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 ; RV64IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB54_1 ; RV64IA-NEXT: bnez a5, .LBB54_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b seq_cst %1 = atomicrmw umin ptr %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
▲ Show 20 Lines • Show All 282 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a2) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: mv a5, a1 ; RV32IA-NEXT: mv a5, a1
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB59_1 ; RV32IA-NEXT: bnez a5, .LBB59_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
Show All 14 Lines
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a2) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: mv a5, a1 ; RV64IA-NEXT: mv a5, a1
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB59_1 ; RV64IA-NEXT: bnez a5, .LBB59_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b seq_cst %1 = atomicrmw xchg ptr %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
▲ Show 20 Lines • Show All 282 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a2) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: add a5, a3, a1 ; RV32IA-NEXT: add a5, a3, a1
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB64_1 ; RV32IA-NEXT: bnez a5, .LBB64_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_add_i16_seq_cst: ; RV64I-LABEL: atomicrmw_add_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
Show All 14 Lines
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a2) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: add a5, a3, a1 ; RV64IA-NEXT: add a5, a3, a1
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB64_1 ; RV64IA-NEXT: bnez a5, .LBB64_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b seq_cst %1 = atomicrmw add ptr %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
▲ Show 20 Lines • Show All 282 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a2) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: sub a5, a3, a1 ; RV32IA-NEXT: sub a5, a3, a1
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB69_1 ; RV32IA-NEXT: bnez a5, .LBB69_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64I-LABEL: atomicrmw_sub_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
Show All 14 Lines
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a2) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: sub a5, a3, a1 ; RV64IA-NEXT: sub a5, a3, a1
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB69_1 ; RV64IA-NEXT: bnez a5, .LBB69_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b seq_cst %1 = atomicrmw sub ptr %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
▲ Show 20 Lines • Show All 561 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a2) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: and a5, a3, a1 ; RV32IA-NEXT: and a5, a3, a1
; RV32IA-NEXT: not a5, a5 ; RV32IA-NEXT: not a5, a5
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB79_1 ; RV32IA-NEXT: bnez a5, .LBB79_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
Show All 15 Lines
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB79_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a2) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: and a5, a3, a1 ; RV64IA-NEXT: and a5, a3, a1
; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: not a5, a5
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB79_1 ; RV64IA-NEXT: bnez a5, .LBB79_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b seq_cst %1 = atomicrmw nand ptr %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
▲ Show 20 Lines • Show All 1,120 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: sll a7, a7, a5 ; RV32IA-NEXT: sll a7, a7, a5
; RV32IA-NEXT: sra a7, a7, a5 ; RV32IA-NEXT: sra a7, a7, a5
; RV32IA-NEXT: bge a7, a1, .LBB94_3 ; RV32IA-NEXT: bge a7, a1, .LBB94_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1
; RV32IA-NEXT: xor a6, a3, a1 ; RV32IA-NEXT: xor a6, a3, a1
; RV32IA-NEXT: and a6, a6, a4 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a6, a3, a6 ; RV32IA-NEXT: xor a6, a3, a6
; RV32IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1 ; RV32IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a6, a6, (a2) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a6, .LBB94_1 ; RV32IA-NEXT: bnez a6, .LBB94_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_seq_cst: ; RV64I-LABEL: atomicrmw_max_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; RV64IA-NEXT: sll a7, a7, a5 ; RV64IA-NEXT: sll a7, a7, a5
; RV64IA-NEXT: sra a7, a7, a5 ; RV64IA-NEXT: sra a7, a7, a5
; RV64IA-NEXT: bge a7, a1, .LBB94_3 ; RV64IA-NEXT: bge a7, a1, .LBB94_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1
; RV64IA-NEXT: xor a6, a3, a1 ; RV64IA-NEXT: xor a6, a3, a1
; RV64IA-NEXT: and a6, a6, a4 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a6, a3, a6 ; RV64IA-NEXT: xor a6, a3, a6
; RV64IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1 ; RV64IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a6, a6, (a2) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a6, .LBB94_1 ; RV64IA-NEXT: bnez a6, .LBB94_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b seq_cst %1 = atomicrmw max ptr %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
▲ Show 20 Lines • Show All 660 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: sll a7, a7, a5 ; RV32IA-NEXT: sll a7, a7, a5
; RV32IA-NEXT: sra a7, a7, a5 ; RV32IA-NEXT: sra a7, a7, a5
; RV32IA-NEXT: bge a1, a7, .LBB99_3 ; RV32IA-NEXT: bge a1, a7, .LBB99_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1
; RV32IA-NEXT: xor a6, a3, a1 ; RV32IA-NEXT: xor a6, a3, a1
; RV32IA-NEXT: and a6, a6, a4 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a6, a3, a6 ; RV32IA-NEXT: xor a6, a3, a6
; RV32IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1 ; RV32IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a6, a6, (a2) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a6, .LBB99_1 ; RV32IA-NEXT: bnez a6, .LBB99_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_seq_cst: ; RV64I-LABEL: atomicrmw_min_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; RV64IA-NEXT: sll a7, a7, a5 ; RV64IA-NEXT: sll a7, a7, a5
; RV64IA-NEXT: sra a7, a7, a5 ; RV64IA-NEXT: sra a7, a7, a5
; RV64IA-NEXT: bge a1, a7, .LBB99_3 ; RV64IA-NEXT: bge a1, a7, .LBB99_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1
; RV64IA-NEXT: xor a6, a3, a1 ; RV64IA-NEXT: xor a6, a3, a1
; RV64IA-NEXT: and a6, a6, a4 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a6, a3, a6 ; RV64IA-NEXT: xor a6, a3, a6
; RV64IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1 ; RV64IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a6, a6, (a2) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a6, .LBB99_1 ; RV64IA-NEXT: bnez a6, .LBB99_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b seq_cst %1 = atomicrmw min ptr %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
▲ Show 20 Lines • Show All 624 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: and a6, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a6, a1, .LBB104_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB104_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1 ; RV32IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB104_1 ; RV32IA-NEXT: bnez a5, .LBB104_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; RV64IA-NEXT: and a6, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a6, a1, .LBB104_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB104_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1 ; RV64IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB104_1 ; RV64IA-NEXT: bnez a5, .LBB104_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b seq_cst %1 = atomicrmw umax ptr %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
▲ Show 20 Lines • Show All 624 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: and a6, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a6, .LBB109_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB109_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1 ; RV32IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB109_1 ; RV32IA-NEXT: bnez a5, .LBB109_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; RV64IA-NEXT: and a6, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a6, .LBB109_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB109_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1 ; RV64IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB109_1 ; RV64IA-NEXT: bnez a5, .LBB109_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b seq_cst %1 = atomicrmw umin ptr %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
▲ Show 20 Lines • Show All 891 Lines • ▼ Show 20 Lines
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_nand_i32_seq_cst: ; RV32IA-LABEL: atomicrmw_nand_i32_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a2, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a0)
; RV32IA-NEXT: and a3, a2, a1 ; RV32IA-NEXT: and a3, a2, a1
; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: not a3, a3
; RV32IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV32IA-NEXT: sc.w.rl a3, a3, (a0)
; RV32IA-NEXT: bnez a3, .LBB134_1 ; RV32IA-NEXT: bnez a3, .LBB134_1
; RV32IA-NEXT: # %bb.2: ; RV32IA-NEXT: # %bb.2:
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_nand_i32_seq_cst: ; RV64I-LABEL: atomicrmw_nand_i32_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: li a2, 5 ; RV64I-NEXT: li a2, 5
; RV64I-NEXT: call __atomic_fetch_nand_4@plt ; RV64I-NEXT: call __atomic_fetch_nand_4@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i32_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i32_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB134_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a2, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.w.aqrl a3, a3, (a0) ; RV64IA-NEXT: sc.w.rl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB134_1 ; RV64IA-NEXT: bnez a3, .LBB134_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b seq_cst %1 = atomicrmw nand ptr %a, i32 %b seq_cst
ret i32 %1 ret i32 %1
} }
▲ Show 20 Lines • Show All 3,118 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_nand_i64_seq_cst: ; RV64IA-LABEL: atomicrmw_nand_i64_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: .LBB189_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB189_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.d.aqrl a2, (a0) ; RV64IA-NEXT: lr.d.aqrl a2, (a0)
; RV64IA-NEXT: and a3, a2, a1 ; RV64IA-NEXT: and a3, a2, a1
; RV64IA-NEXT: not a3, a3 ; RV64IA-NEXT: not a3, a3
; RV64IA-NEXT: sc.d.aqrl a3, a3, (a0) ; RV64IA-NEXT: sc.d.rl a3, a3, (a0)
; RV64IA-NEXT: bnez a3, .LBB189_1 ; RV64IA-NEXT: bnez a3, .LBB189_1
; RV64IA-NEXT: # %bb.2: ; RV64IA-NEXT: # %bb.2:
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b seq_cst %1 = atomicrmw nand ptr %a, i64 %b seq_cst
ret i64 %1 ret i64 %1
} }
▲ Show 20 Lines • Show All 3,469 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; RV32IA-NEXT: or a6, a6, a4 ; RV32IA-NEXT: or a6, a6, a4
; RV32IA-NEXT: .LBB0_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB0_3: # %atomicrmw.start
; RV32IA-NEXT: # Parent Loop BB0_1 Depth=1 ; RV32IA-NEXT: # Parent Loop BB0_1 Depth=1
; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2
; RV32IA-NEXT: lr.w.aqrl a4, (a2) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: bne a4, a5, .LBB0_1 ; RV32IA-NEXT: bne a4, a5, .LBB0_1
; RV32IA-NEXT: # %bb.4: # %atomicrmw.start ; RV32IA-NEXT: # %bb.4: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB0_3 Depth=2 ; RV32IA-NEXT: # in Loop: Header=BB0_3 Depth=2
; RV32IA-NEXT: sc.w.aqrl a7, a6, (a2) ; RV32IA-NEXT: sc.w.rl a7, a6, (a2)
; RV32IA-NEXT: bnez a7, .LBB0_3 ; RV32IA-NEXT: bnez a7, .LBB0_3
; RV32IA-NEXT: # %bb.5: # %atomicrmw.start ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
; RV32IA-NEXT: # %bb.2: # %atomicrmw.end ; RV32IA-NEXT: # %bb.2: # %atomicrmw.end
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_uinc_wrap_i8: ; RV64I-LABEL: atomicrmw_uinc_wrap_i8:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
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; RV64IA-NEXT: or a5, a4, a5 ; RV64IA-NEXT: or a5, a4, a5
; RV64IA-NEXT: .LBB0_3: # %atomicrmw.start ; RV64IA-NEXT: .LBB0_3: # %atomicrmw.start
; RV64IA-NEXT: # Parent Loop BB0_1 Depth=1 ; RV64IA-NEXT: # Parent Loop BB0_1 Depth=1
; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2
; RV64IA-NEXT: lr.w.aqrl a4, (a2) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: bne a4, a6, .LBB0_1 ; RV64IA-NEXT: bne a4, a6, .LBB0_1
; RV64IA-NEXT: # %bb.4: # %atomicrmw.start ; RV64IA-NEXT: # %bb.4: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB0_3 Depth=2 ; RV64IA-NEXT: # in Loop: Header=BB0_3 Depth=2
; RV64IA-NEXT: sc.w.aqrl a7, a5, (a2) ; RV64IA-NEXT: sc.w.rl a7, a5, (a2)
; RV64IA-NEXT: bnez a7, .LBB0_3 ; RV64IA-NEXT: bnez a7, .LBB0_3
; RV64IA-NEXT: # %bb.5: # %atomicrmw.start ; RV64IA-NEXT: # %bb.5: # %atomicrmw.start
; RV64IA-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%result = atomicrmw uinc_wrap ptr %ptr, i8 %val seq_cst %result = atomicrmw uinc_wrap ptr %ptr, i8 %val seq_cst
ret i8 %result ret i8 %result
} }
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; RV32IA-NEXT: or a7, a7, a5 ; RV32IA-NEXT: or a7, a7, a5
; RV32IA-NEXT: .LBB1_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB1_3: # %atomicrmw.start
; RV32IA-NEXT: # Parent Loop BB1_1 Depth=1 ; RV32IA-NEXT: # Parent Loop BB1_1 Depth=1
; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2
; RV32IA-NEXT: lr.w.aqrl a5, (a2) ; RV32IA-NEXT: lr.w.aqrl a5, (a2)
; RV32IA-NEXT: bne a5, a6, .LBB1_1 ; RV32IA-NEXT: bne a5, a6, .LBB1_1
; RV32IA-NEXT: # %bb.4: # %atomicrmw.start ; RV32IA-NEXT: # %bb.4: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB1_3 Depth=2 ; RV32IA-NEXT: # in Loop: Header=BB1_3 Depth=2
; RV32IA-NEXT: sc.w.aqrl t0, a7, (a2) ; RV32IA-NEXT: sc.w.rl t0, a7, (a2)
; RV32IA-NEXT: bnez t0, .LBB1_3 ; RV32IA-NEXT: bnez t0, .LBB1_3
; RV32IA-NEXT: # %bb.5: # %atomicrmw.start ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
; RV32IA-NEXT: # %bb.2: # %atomicrmw.end ; RV32IA-NEXT: # %bb.2: # %atomicrmw.end
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_uinc_wrap_i16: ; RV64I-LABEL: atomicrmw_uinc_wrap_i16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
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; RV64IA-NEXT: or a6, a5, a6 ; RV64IA-NEXT: or a6, a5, a6
; RV64IA-NEXT: .LBB1_3: # %atomicrmw.start ; RV64IA-NEXT: .LBB1_3: # %atomicrmw.start
; RV64IA-NEXT: # Parent Loop BB1_1 Depth=1 ; RV64IA-NEXT: # Parent Loop BB1_1 Depth=1
; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2
; RV64IA-NEXT: lr.w.aqrl a5, (a2) ; RV64IA-NEXT: lr.w.aqrl a5, (a2)
; RV64IA-NEXT: bne a5, a7, .LBB1_1 ; RV64IA-NEXT: bne a5, a7, .LBB1_1
; RV64IA-NEXT: # %bb.4: # %atomicrmw.start ; RV64IA-NEXT: # %bb.4: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB1_3 Depth=2 ; RV64IA-NEXT: # in Loop: Header=BB1_3 Depth=2
; RV64IA-NEXT: sc.w.aqrl t0, a6, (a2) ; RV64IA-NEXT: sc.w.rl t0, a6, (a2)
; RV64IA-NEXT: bnez t0, .LBB1_3 ; RV64IA-NEXT: bnez t0, .LBB1_3
; RV64IA-NEXT: # %bb.5: # %atomicrmw.start ; RV64IA-NEXT: # %bb.5: # %atomicrmw.start
; RV64IA-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%result = atomicrmw uinc_wrap ptr %ptr, i16 %val seq_cst %result = atomicrmw uinc_wrap ptr %ptr, i16 %val seq_cst
ret i16 %result ret i16 %result
} }
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; RV32IA-NEXT: and a4, a4, a2 ; RV32IA-NEXT: and a4, a4, a2
; RV32IA-NEXT: .LBB2_3: # %atomicrmw.start ; RV32IA-NEXT: .LBB2_3: # %atomicrmw.start
; RV32IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV32IA-NEXT: # Parent Loop BB2_1 Depth=1
; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2
; RV32IA-NEXT: lr.w.aqrl a2, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a0)
; RV32IA-NEXT: bne a2, a3, .LBB2_1 ; RV32IA-NEXT: bne a2, a3, .LBB2_1
; RV32IA-NEXT: # %bb.4: # %atomicrmw.start ; RV32IA-NEXT: # %bb.4: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB2_3 Depth=2 ; RV32IA-NEXT: # in Loop: Header=BB2_3 Depth=2
; RV32IA-NEXT: sc.w.aqrl a5, a4, (a0) ; RV32IA-NEXT: sc.w.rl a5, a4, (a0)
; RV32IA-NEXT: bnez a5, .LBB2_3 ; RV32IA-NEXT: bnez a5, .LBB2_3
; RV32IA-NEXT: # %bb.5: # %atomicrmw.start ; RV32IA-NEXT: # %bb.5: # %atomicrmw.start
; RV32IA-NEXT: # %bb.2: # %atomicrmw.end ; RV32IA-NEXT: # %bb.2: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: mv a0, a2
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_uinc_wrap_i32: ; RV64I-LABEL: atomicrmw_uinc_wrap_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
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; RV64IA-NEXT: and a3, a2, a3 ; RV64IA-NEXT: and a3, a2, a3
; RV64IA-NEXT: .LBB2_3: # %atomicrmw.start ; RV64IA-NEXT: .LBB2_3: # %atomicrmw.start
; RV64IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV64IA-NEXT: # Parent Loop BB2_1 Depth=1
; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2
; RV64IA-NEXT: lr.w.aqrl a2, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a0)
; RV64IA-NEXT: bne a2, a4, .LBB2_1 ; RV64IA-NEXT: bne a2, a4, .LBB2_1
; RV64IA-NEXT: # %bb.4: # %atomicrmw.start ; RV64IA-NEXT: # %bb.4: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB2_3 Depth=2 ; RV64IA-NEXT: # in Loop: Header=BB2_3 Depth=2
; RV64IA-NEXT: sc.w.aqrl a5, a3, (a0) ; RV64IA-NEXT: sc.w.rl a5, a3, (a0)
; RV64IA-NEXT: bnez a5, .LBB2_3 ; RV64IA-NEXT: bnez a5, .LBB2_3
; RV64IA-NEXT: # %bb.5: # %atomicrmw.start ; RV64IA-NEXT: # %bb.5: # %atomicrmw.start
; RV64IA-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%result = atomicrmw uinc_wrap ptr %ptr, i32 %val seq_cst %result = atomicrmw uinc_wrap ptr %ptr, i32 %val seq_cst
ret i32 %result ret i32 %result
} }
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; RV64IA-NEXT: and a4, a4, a2 ; RV64IA-NEXT: and a4, a4, a2
; RV64IA-NEXT: .LBB3_3: # %atomicrmw.start ; RV64IA-NEXT: .LBB3_3: # %atomicrmw.start
; RV64IA-NEXT: # Parent Loop BB3_1 Depth=1 ; RV64IA-NEXT: # Parent Loop BB3_1 Depth=1
; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2
; RV64IA-NEXT: lr.d.aqrl a2, (a0) ; RV64IA-NEXT: lr.d.aqrl a2, (a0)
; RV64IA-NEXT: bne a2, a3, .LBB3_1 ; RV64IA-NEXT: bne a2, a3, .LBB3_1
; RV64IA-NEXT: # %bb.4: # %atomicrmw.start ; RV64IA-NEXT: # %bb.4: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB3_3 Depth=2 ; RV64IA-NEXT: # in Loop: Header=BB3_3 Depth=2
; RV64IA-NEXT: sc.d.aqrl a5, a4, (a0) ; RV64IA-NEXT: sc.d.rl a5, a4, (a0)
; RV64IA-NEXT: bnez a5, .LBB3_3 ; RV64IA-NEXT: bnez a5, .LBB3_3
; RV64IA-NEXT: # %bb.5: # %atomicrmw.start ; RV64IA-NEXT: # %bb.5: # %atomicrmw.start
; RV64IA-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: mv a0, a2
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%result = atomicrmw uinc_wrap ptr %ptr, i64 %val seq_cst %result = atomicrmw uinc_wrap ptr %ptr, i64 %val seq_cst
ret i64 %result ret i64 %result
} }
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; RV32IA-NEXT: or a7, a7, a6 ; RV32IA-NEXT: or a7, a7, a6
; RV32IA-NEXT: .LBB4_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB4_5: # %atomicrmw.start
; RV32IA-NEXT: # Parent Loop BB4_2 Depth=1 ; RV32IA-NEXT: # Parent Loop BB4_2 Depth=1
; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2
; RV32IA-NEXT: lr.w.aqrl a6, (a2) ; RV32IA-NEXT: lr.w.aqrl a6, (a2)
; RV32IA-NEXT: bne a6, a5, .LBB4_7 ; RV32IA-NEXT: bne a6, a5, .LBB4_7
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB4_5 Depth=2 ; RV32IA-NEXT: # in Loop: Header=BB4_5 Depth=2
; RV32IA-NEXT: sc.w.aqrl t0, a7, (a2) ; RV32IA-NEXT: sc.w.rl t0, a7, (a2)
; RV32IA-NEXT: bnez t0, .LBB4_5 ; RV32IA-NEXT: bnez t0, .LBB4_5
; RV32IA-NEXT: .LBB4_7: # %atomicrmw.start ; RV32IA-NEXT: .LBB4_7: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB4_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB4_2 Depth=1
; RV32IA-NEXT: beq a6, a5, .LBB4_4 ; RV32IA-NEXT: beq a6, a5, .LBB4_4
; RV32IA-NEXT: .LBB4_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB4_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Loop Header: Depth=1
; RV32IA-NEXT: # Child Loop BB4_5 Depth 2 ; RV32IA-NEXT: # Child Loop BB4_5 Depth 2
; RV32IA-NEXT: mv a5, a6 ; RV32IA-NEXT: mv a5, a6
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; RV64IA-NEXT: or a7, a4, a7 ; RV64IA-NEXT: or a7, a4, a7
; RV64IA-NEXT: .LBB4_5: # %atomicrmw.start ; RV64IA-NEXT: .LBB4_5: # %atomicrmw.start
; RV64IA-NEXT: # Parent Loop BB4_2 Depth=1 ; RV64IA-NEXT: # Parent Loop BB4_2 Depth=1
; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2
; RV64IA-NEXT: lr.w.aqrl a4, (a2) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: bne a4, a6, .LBB4_7 ; RV64IA-NEXT: bne a4, a6, .LBB4_7
; RV64IA-NEXT: # %bb.6: # %atomicrmw.start ; RV64IA-NEXT: # %bb.6: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB4_5 Depth=2 ; RV64IA-NEXT: # in Loop: Header=BB4_5 Depth=2
; RV64IA-NEXT: sc.w.aqrl t0, a7, (a2) ; RV64IA-NEXT: sc.w.rl t0, a7, (a2)
; RV64IA-NEXT: bnez t0, .LBB4_5 ; RV64IA-NEXT: bnez t0, .LBB4_5
; RV64IA-NEXT: .LBB4_7: # %atomicrmw.start ; RV64IA-NEXT: .LBB4_7: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB4_2 Depth=1 ; RV64IA-NEXT: # in Loop: Header=BB4_2 Depth=1
; RV64IA-NEXT: beq a4, a6, .LBB4_4 ; RV64IA-NEXT: beq a4, a6, .LBB4_4
; RV64IA-NEXT: .LBB4_2: # %atomicrmw.start ; RV64IA-NEXT: .LBB4_2: # %atomicrmw.start
; RV64IA-NEXT: # =>This Loop Header: Depth=1 ; RV64IA-NEXT: # =>This Loop Header: Depth=1
; RV64IA-NEXT: # Child Loop BB4_5 Depth 2 ; RV64IA-NEXT: # Child Loop BB4_5 Depth 2
; RV64IA-NEXT: srlw a6, a4, a0 ; RV64IA-NEXT: srlw a6, a4, a0
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; RV32IA-NEXT: or t0, t0, a7 ; RV32IA-NEXT: or t0, t0, a7
; RV32IA-NEXT: .LBB5_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB5_5: # %atomicrmw.start
; RV32IA-NEXT: # Parent Loop BB5_2 Depth=1 ; RV32IA-NEXT: # Parent Loop BB5_2 Depth=1
; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2
; RV32IA-NEXT: lr.w.aqrl a7, (a2) ; RV32IA-NEXT: lr.w.aqrl a7, (a2)
; RV32IA-NEXT: bne a7, a6, .LBB5_7 ; RV32IA-NEXT: bne a7, a6, .LBB5_7
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB5_5 Depth=2 ; RV32IA-NEXT: # in Loop: Header=BB5_5 Depth=2
; RV32IA-NEXT: sc.w.aqrl t1, t0, (a2) ; RV32IA-NEXT: sc.w.rl t1, t0, (a2)
; RV32IA-NEXT: bnez t1, .LBB5_5 ; RV32IA-NEXT: bnez t1, .LBB5_5
; RV32IA-NEXT: .LBB5_7: # %atomicrmw.start ; RV32IA-NEXT: .LBB5_7: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB5_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB5_2 Depth=1
; RV32IA-NEXT: beq a7, a6, .LBB5_4 ; RV32IA-NEXT: beq a7, a6, .LBB5_4
; RV32IA-NEXT: .LBB5_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB5_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Loop Header: Depth=1
; RV32IA-NEXT: # Child Loop BB5_5 Depth 2 ; RV32IA-NEXT: # Child Loop BB5_5 Depth 2
; RV32IA-NEXT: mv a6, a7 ; RV32IA-NEXT: mv a6, a7
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; RV64IA-NEXT: or t0, a5, t0 ; RV64IA-NEXT: or t0, a5, t0
; RV64IA-NEXT: .LBB5_5: # %atomicrmw.start ; RV64IA-NEXT: .LBB5_5: # %atomicrmw.start
; RV64IA-NEXT: # Parent Loop BB5_2 Depth=1 ; RV64IA-NEXT: # Parent Loop BB5_2 Depth=1
; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2
; RV64IA-NEXT: lr.w.aqrl a5, (a2) ; RV64IA-NEXT: lr.w.aqrl a5, (a2)
; RV64IA-NEXT: bne a5, a7, .LBB5_7 ; RV64IA-NEXT: bne a5, a7, .LBB5_7
; RV64IA-NEXT: # %bb.6: # %atomicrmw.start ; RV64IA-NEXT: # %bb.6: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB5_5 Depth=2 ; RV64IA-NEXT: # in Loop: Header=BB5_5 Depth=2
; RV64IA-NEXT: sc.w.aqrl t1, t0, (a2) ; RV64IA-NEXT: sc.w.rl t1, t0, (a2)
; RV64IA-NEXT: bnez t1, .LBB5_5 ; RV64IA-NEXT: bnez t1, .LBB5_5
; RV64IA-NEXT: .LBB5_7: # %atomicrmw.start ; RV64IA-NEXT: .LBB5_7: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB5_2 Depth=1 ; RV64IA-NEXT: # in Loop: Header=BB5_2 Depth=1
; RV64IA-NEXT: beq a5, a7, .LBB5_4 ; RV64IA-NEXT: beq a5, a7, .LBB5_4
; RV64IA-NEXT: .LBB5_2: # %atomicrmw.start ; RV64IA-NEXT: .LBB5_2: # %atomicrmw.start
; RV64IA-NEXT: # =>This Loop Header: Depth=1 ; RV64IA-NEXT: # =>This Loop Header: Depth=1
; RV64IA-NEXT: # Child Loop BB5_5 Depth 2 ; RV64IA-NEXT: # Child Loop BB5_5 Depth 2
; RV64IA-NEXT: srlw a7, a5, a0 ; RV64IA-NEXT: srlw a7, a5, a0
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; RV32IA-NEXT: # in Loop: Header=BB6_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB6_2 Depth=1
; RV32IA-NEXT: .LBB6_5: # %atomicrmw.start ; RV32IA-NEXT: .LBB6_5: # %atomicrmw.start
; RV32IA-NEXT: # Parent Loop BB6_2 Depth=1 ; RV32IA-NEXT: # Parent Loop BB6_2 Depth=1
; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2
; RV32IA-NEXT: lr.w.aqrl a2, (a0) ; RV32IA-NEXT: lr.w.aqrl a2, (a0)
; RV32IA-NEXT: bne a2, a3, .LBB6_7 ; RV32IA-NEXT: bne a2, a3, .LBB6_7
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start ; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB6_5 Depth=2 ; RV32IA-NEXT: # in Loop: Header=BB6_5 Depth=2
; RV32IA-NEXT: sc.w.aqrl a5, a4, (a0) ; RV32IA-NEXT: sc.w.rl a5, a4, (a0)
; RV32IA-NEXT: bnez a5, .LBB6_5 ; RV32IA-NEXT: bnez a5, .LBB6_5
; RV32IA-NEXT: .LBB6_7: # %atomicrmw.start ; RV32IA-NEXT: .LBB6_7: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB6_2 Depth=1 ; RV32IA-NEXT: # in Loop: Header=BB6_2 Depth=1
; RV32IA-NEXT: beq a2, a3, .LBB6_4 ; RV32IA-NEXT: beq a2, a3, .LBB6_4
; RV32IA-NEXT: .LBB6_2: # %atomicrmw.start ; RV32IA-NEXT: .LBB6_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Loop Header: Depth=1 ; RV32IA-NEXT: # =>This Loop Header: Depth=1
; RV32IA-NEXT: # Child Loop BB6_5 Depth 2 ; RV32IA-NEXT: # Child Loop BB6_5 Depth 2
; RV32IA-NEXT: mv a3, a2 ; RV32IA-NEXT: mv a3, a2
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; RV64IA-NEXT: # in Loop: Header=BB6_2 Depth=1 ; RV64IA-NEXT: # in Loop: Header=BB6_2 Depth=1
; RV64IA-NEXT: .LBB6_5: # %atomicrmw.start ; RV64IA-NEXT: .LBB6_5: # %atomicrmw.start
; RV64IA-NEXT: # Parent Loop BB6_2 Depth=1 ; RV64IA-NEXT: # Parent Loop BB6_2 Depth=1
; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2
; RV64IA-NEXT: lr.w.aqrl a2, (a0) ; RV64IA-NEXT: lr.w.aqrl a2, (a0)
; RV64IA-NEXT: bne a2, a4, .LBB6_7 ; RV64IA-NEXT: bne a2, a4, .LBB6_7
; RV64IA-NEXT: # %bb.6: # %atomicrmw.start ; RV64IA-NEXT: # %bb.6: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB6_5 Depth=2 ; RV64IA-NEXT: # in Loop: Header=BB6_5 Depth=2
; RV64IA-NEXT: sc.w.aqrl a6, a5, (a0) ; RV64IA-NEXT: sc.w.rl a6, a5, (a0)
; RV64IA-NEXT: bnez a6, .LBB6_5 ; RV64IA-NEXT: bnez a6, .LBB6_5
; RV64IA-NEXT: .LBB6_7: # %atomicrmw.start ; RV64IA-NEXT: .LBB6_7: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB6_2 Depth=1 ; RV64IA-NEXT: # in Loop: Header=BB6_2 Depth=1
; RV64IA-NEXT: beq a2, a4, .LBB6_4 ; RV64IA-NEXT: beq a2, a4, .LBB6_4
; RV64IA-NEXT: .LBB6_2: # %atomicrmw.start ; RV64IA-NEXT: .LBB6_2: # %atomicrmw.start
; RV64IA-NEXT: # =>This Loop Header: Depth=1 ; RV64IA-NEXT: # =>This Loop Header: Depth=1
; RV64IA-NEXT: # Child Loop BB6_5 Depth 2 ; RV64IA-NEXT: # Child Loop BB6_5 Depth 2
; RV64IA-NEXT: sext.w a4, a2 ; RV64IA-NEXT: sext.w a4, a2
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; RV64IA-NEXT: # in Loop: Header=BB7_2 Depth=1 ; RV64IA-NEXT: # in Loop: Header=BB7_2 Depth=1
; RV64IA-NEXT: .LBB7_5: # %atomicrmw.start ; RV64IA-NEXT: .LBB7_5: # %atomicrmw.start
; RV64IA-NEXT: # Parent Loop BB7_2 Depth=1 ; RV64IA-NEXT: # Parent Loop BB7_2 Depth=1
; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2
; RV64IA-NEXT: lr.d.aqrl a2, (a0) ; RV64IA-NEXT: lr.d.aqrl a2, (a0)
; RV64IA-NEXT: bne a2, a3, .LBB7_7 ; RV64IA-NEXT: bne a2, a3, .LBB7_7
; RV64IA-NEXT: # %bb.6: # %atomicrmw.start ; RV64IA-NEXT: # %bb.6: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB7_5 Depth=2 ; RV64IA-NEXT: # in Loop: Header=BB7_5 Depth=2
; RV64IA-NEXT: sc.d.aqrl a5, a4, (a0) ; RV64IA-NEXT: sc.d.rl a5, a4, (a0)
; RV64IA-NEXT: bnez a5, .LBB7_5 ; RV64IA-NEXT: bnez a5, .LBB7_5
; RV64IA-NEXT: .LBB7_7: # %atomicrmw.start ; RV64IA-NEXT: .LBB7_7: # %atomicrmw.start
; RV64IA-NEXT: # in Loop: Header=BB7_2 Depth=1 ; RV64IA-NEXT: # in Loop: Header=BB7_2 Depth=1
; RV64IA-NEXT: beq a2, a3, .LBB7_4 ; RV64IA-NEXT: beq a2, a3, .LBB7_4
; RV64IA-NEXT: .LBB7_2: # %atomicrmw.start ; RV64IA-NEXT: .LBB7_2: # %atomicrmw.start
; RV64IA-NEXT: # =>This Loop Header: Depth=1 ; RV64IA-NEXT: # =>This Loop Header: Depth=1
; RV64IA-NEXT: # Child Loop BB7_5 Depth 2 ; RV64IA-NEXT: # Child Loop BB7_5 Depth 2
; RV64IA-NEXT: mv a3, a2 ; RV64IA-NEXT: mv a3, a2
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