[CodeGen] Don't include aliases in RegisterClassInfo::IgnoreCSRForAllocOrder

[foad]

Summary

Previously we called ignoreCSRForAllocationOrder on every alias of every
CSR which was expensive on targets like AMDGPU which define a very large
number of overlapping register tuples.

On such targets it is simpler and faster to call
ignoreCSRForAllocationOrder once for every physical register.

[foad]

This code was introduced in D126565 with no tests. I don't understand what it could mean for STI.ignoreCSRForAllocationOrder to return different results for registers that alias, so I hope it is sufficient to call it only on the registers that are directly specified in the CSR list.

[foad]

Incidentally the two patches in this stack give me about a 10% speedup in running llc -march=amdgcn -mcpu=gfx1100 on a trivial .ll file that just contains a single empty function.

[qcolombet]

llvm/lib/CodeGen/RegisterClassInfo.cpp

95–96

Given the only spot where ::ignoreCSRForAllocationOrder is used is guarded by CalleeSavedAliases and that one is populated with regunits (after your other change), I think we should go through the regunits too here.

[foad]

Update.

[foad]

llvm/lib/CodeGen/RegisterClassInfo.cpp

95–96

How about this brute force approach, calling ignoreCSRForAllocationOrder on every physical register? This is the simplest fastest thing I could come up with for AMDGPU, where ignoreCSRForAllocationOrder is just a virtual call to default implementation that returns false.

[qcolombet]

llvm/lib/CodeGen/RegisterClassInfo.cpp

95–96

Isn't it cheaper (compile-time wise) to go through only the relevant regunits?

[foad]

llvm/lib/CodeGen/RegisterClassInfo.cpp

95–96

How? I can't call STI.ignoreCSRForAllocationOrder on a regunit, only on a register, so I would somehow have to find all registers that contain any regunit that is contained by any CSR - is that what you're suggesting? I don't think I can do that more cheaply than just iterating through all registers once each.

[Srividya-Karumuri]

llvm/lib/CodeGen/RegisterClassInfo.cpp

95–96

Regarding the below comment, what is the "other change" that is being referred here?

<Given the only spot where ::ignoreCSRForAllocationOrder is used is guarded by CalleeSavedAliases and that one is populated with regunits (after your other change), I think we should go through the regunits too here.>

[foad]

llvm/lib/CodeGen/RegisterClassInfo.cpp

95–96

D146734

[qcolombet]

llvm/lib/CodeGen/RegisterClassInfo.cpp

95–96

I was thinking that we would go through the roots of the regunits, but you're right technically that may not be enough.
Brute force here sounds fine.

llvm/lib/CodeGen/RegisterClassInfo.cpp

for (const MCPhysReg *I = CSR; *I; ++I) {
       LastCalleeSavedRegs.push_back(*I);
     }
 
     Update = true;
   }
 
   // Even if CSR list is same, we could have had a different allocation order
   // if ignoreCSRForAllocationOrder is evaluated differently.
   BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
-  for (const MCPhysReg *I = CSR; *I; ++I)
-    for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
-      CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
-  if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
-      IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
+  for (MCPhysReg I = 1, E = TRI->getNumRegs(); I != E; ++I)
+    CSRHintsForAllocOrder[I] = STI.ignoreCSRForAllocationOrder(mf, I);
+  if (IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
     Update = true;
     IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
   }
 
   RegCosts = TRI->getRegisterCosts(*MF);
 
   // Different reserved registers?
   const BitVector &RR = MF->getRegInfo().getReservedRegs();