[BOLT][NFC] Return instruction list from createInstrIncMemory

[Amir]

Summary

Leverage move semantics for std::vector.

This also makes it consistent with createInstrumentationSnippet.

[yota9]

@Elvina Please check :)
LGTM

[Elvina]

LGTM

bolt/include/bolt/Core/MCPlusBuilder.h

virtual bool createDirectCall(MCInst &Inst, const MCSymbol *Target,
                                 MCContext *Ctx, bool IsTailCall) {
     llvm_unreachable("not implemented");
     return false;
   }
 
   virtual MCPhysReg getX86R11() const { llvm_unreachable("not implemented"); }
 
   /// Create increment contents of target by 1 for Instrumentation
-  virtual void createInstrIncMemory(InstructionListType &Instrs,
-                                    const MCSymbol *Target, MCContext *Ctx,
+  virtual InstructionListType createInstrIncMemory(const MCSymbol *Target,
+                                                   MCContext *Ctx,
                                                    bool IsLeaf) const {
     llvm_unreachable("not implemented");
+    return InstructionListType();
   }
 
   /// Return a register number that is guaranteed to not match with
   /// any real register on the underlying architecture.
   MCPhysReg getNoRegister() const { return MCRegister::NoRegister; }
 
   /// Return a register corresponding to a function integer argument \p ArgNo
   /// if the argument is passed in a register. Or return the result of

bolt/lib/Passes/Instrumentation.cpp

void Instrumentation::createLeafNodeDescription(FunctionDescription &FuncDesc,
   IN.Counter = Summary->Counters.size();
   ++LeafNodeCounters;
   FuncDesc.LeafNodes.emplace_back(IN);
 }
 
 InstructionListType
 Instrumentation::createInstrumentationSnippet(BinaryContext &BC, bool IsLeaf) {
   auto L = BC.scopeLock();
-  MCSymbol *Label;
-  Label = BC.Ctx->createNamedTempSymbol("InstrEntry");
+  MCSymbol *Label = BC.Ctx->createNamedTempSymbol("InstrEntry");
   Summary->Counters.emplace_back(Label);
-  InstructionListType CounterInstrs;
-  BC.MIB->createInstrIncMemory(CounterInstrs, Label, &*BC.Ctx, IsLeaf);
-  return CounterInstrs;
+  return BC.MIB->createInstrIncMemory(Label, BC.Ctx.get(), IsLeaf);
 }
 
 // Helper instruction sequence insertion function
 static BinaryBasicBlock::iterator
 insertInstructions(InstructionListType &Instrs, BinaryBasicBlock &BB,
                    BinaryBasicBlock::iterator Iter) {
   for (MCInst &NewInst : Instrs) {
     Iter = BB.insertInstruction(Iter, NewInst);

 }
 
 bool Instrumentation::instrumentOneTarget(
     SplitWorklistTy &SplitWorklist, SplitInstrsTy &SplitInstrs,
     BinaryBasicBlock::iterator &Iter, BinaryFunction &FromFunction,
     BinaryBasicBlock &FromBB, uint32_t From, BinaryFunction &ToFunc,
     BinaryBasicBlock *TargetBB, uint32_t ToOffset, bool IsLeaf, bool IsInvoke,
     FunctionDescription *FuncDesc, uint32_t FromNodeID, uint32_t ToNodeID) {
+  BinaryContext &BC = FromFunction.getBinaryContext();
   {
-    auto L = FromFunction.getBinaryContext().scopeLock();
+    auto L = BC.scopeLock();
     bool Created = true;
     if (!TargetBB)
       Created = createCallDescription(*FuncDesc, FromFunction, From, FromNodeID,
                                       ToFunc, ToOffset, IsInvoke);
     else
       Created = createEdgeDescription(*FuncDesc, FromFunction, From, FromNodeID,
                                       ToFunc, ToOffset, ToNodeID,
                                       /*Instrumented=*/true);
     if (!Created)
       return false;
   }
 
-  InstructionListType CounterInstrs =
-      createInstrumentationSnippet(FromFunction.getBinaryContext(), IsLeaf);
+  InstructionListType CounterInstrs = createInstrumentationSnippet(BC, IsLeaf);
 
-  BinaryContext &BC = FromFunction.getBinaryContext();
   const MCInst &Inst = *Iter;
   if (BC.MIB->isCall(Inst)) {
     // This code handles both
     // - (regular) inter-function calls (cross-function control transfer),
     // - (rare) intra-function calls (function-local control transfer)
     Iter = insertInstructions(CounterInstrs, FromBB, Iter);
     return true;
   }

bolt/lib/Target/X86/X86MCPlusBuilder.cpp

void createX86Lahf(MCInst &Inst) const {
     Inst.clear();
   }
 
   void createX86Sahf(MCInst &Inst) const {
     Inst.setOpcode(X86::SAHF);
     Inst.clear();
   }
 
-  void createInstrIncMemory(InstructionListType &Instrs, const MCSymbol *Target,
-                            MCContext *Ctx, bool IsLeaf) const override {
+  InstructionListType createInstrIncMemory(const MCSymbol *Target,
+                                           MCContext *Ctx,
+                                           bool IsLeaf) const override {
+    InstructionListType Instrs(IsLeaf ? 13 : 11);
     unsigned int I = 0;
 
-    Instrs.resize(IsLeaf ? 13 : 11);
     // Don't clobber application red zone (ABI dependent)
     if (IsLeaf)
       createStackPointerIncrement(Instrs[I++], 128,
                                   /*NoFlagsClobber=*/true);
 
     // Performance improvements based on the optimization discussed at
     // https://reviews.llvm.org/D6629
     // LAHF/SAHF are used instead of PUSHF/POPF
InstructionListType createInstrIncMemory(const MCSymbol *Target,
     createAddRegImm(Instrs[I++], X86::AL, 127, 1);
     createPopRegister(Instrs[I++], X86::RAX, 8);
     createX86Sahf(Instrs[I++]);
     createPopRegister(Instrs[I++], X86::RAX, 8);
 
     if (IsLeaf)
       createStackPointerDecrement(Instrs[I], 128,
                                   /*NoFlagsClobber=*/true);
+    return Instrs;
   }
 
   void createSwap(MCInst &Inst, MCPhysReg Source, MCPhysReg MemBaseReg,
                   int64_t Disp) const {
     Inst.setOpcode(X86::XCHG64rm);
     Inst.addOperand(MCOperand::createReg(Source));
     Inst.addOperand(MCOperand::createReg(Source));
     Inst.addOperand(MCOperand::createReg(MemBaseReg));      // BaseReg