[AMDGPU] Fix invalid instid value in s_delay_alu instruction

llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp

struct DelayInfo {
     // One larger than the maximum number of (non-TRANS) VALU instructions we
     // can encode in an s_delay_alu instruction.
     static const unsigned VALU_MAX = 5;
 
     // One larger than the maximum number of TRANS instructions we can encode in
     // an s_delay_alu instruction.
     static const unsigned TRANS_MAX = 4;
 
+    // The maximum number of SALU cycles we can encode in an s_delay_alu
+    // instruction.
+    static const unsigned SALU_CYCLES_MAX = 3;
+
     // If it was written by a (non-TRANS) VALU, remember how many clock cycles
     // are left until it completes, and how many other (non-TRANS) VALU we have
     // seen since it was issued.
     uint8_t VALUCycles = 0;
     uint8_t VALUNum = VALU_MAX;
 
     // If it was written by a TRANS, remember how many clock cycles are left
     // until it completes, and how many other TRANS we have seen since it was
DelayInfo(DelayType Type, unsigned Cycles) {
         VALUNum = 0;
         break;
       case TRANS:
         TRANSCycles = Cycles;
         TRANSNum = 0;
         TRANSNumVALU = 0;
         break;
       case SALU:
-        SALUCycles = Cycles;
+        // Guard against pseudo-instructions like SI_CALL which are marked as
+        // SALU but with a very high latency.
+        SALUCycles = std::min(Cycles, SALU_CYCLES_MAX);
         break;
       }
     }
 
     bool operator==(const DelayInfo &RHS) const {
       return VALUCycles == RHS.VALUCycles && VALUNum == RHS.VALUNum &&
              TRANSCycles == RHS.TRANSCycles && TRANSNum == RHS.TRANSNum &&
              TRANSNumVALU == RHS.TRANSNumVALU && SALUCycles == RHS.SALUCycles;
for (auto &MI : MBB.instrs()) {
       case AMDGPU::SI_RETURN_TO_EPILOG:
         continue;
       }
 
       DelayType Type = getDelayType(MI.getDesc().TSFlags);
 
       if (instructionWaitsForVALU(MI)) {
         // Forget about all outstanding VALU delays.
+        // TODO: This is overkill since it also forgets about SALU delays.
         State = DelayState();
       } else if (Type != OTHER) {
         DelayInfo Delay;
         // TODO: Scan implicit uses too?
         for (const auto &Op : MI.explicit_uses()) {
           if (Op.isReg()) {
             // One of the operands of the writelane is also the output operand.
             // This creates the insertion of redundant delays. Hence, we have to

llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll

 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_mul_hi_u32 s2, s29, s28
 ; GFX11-NEXT:    s_mul_i32 s3, s29, s28
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_alignbit_b32 v0, s2, s3, 1
 ; GFX11-NEXT:    s_mov_b32 s3, 0
 ; GFX11-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s25
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(/* invalid instid value */)
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_or_b32 s2, s2, 1
 ; GFX11-NEXT:    s_lshr_b32 s2, s2, s30
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_mul_i32 s2, s2, s22
 ; GFX11-NEXT:    s_mul_i32 s2, s2, s20
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_or_b32 s2, s24, s2
 ; GFX11-NEXT:    s_lshl_b64 s[22:23], s[2:3], 1