[X86][InstCombine] Simplify some `pternlog` intrinsics

[goldstein.w.n]

Summary

Currently pternlog intrinsics stay as a function call and are unable
to merge with other bin-ops / constant-fold.

This commit adds support for reducing all pternlog intrinsics to
their base logic-ops so that they can be further reduced in other
passes.

Since the x86 backend doesn't do a great job creating vpternlog
instructions from stray logic ops, the current logic only simplifies
in the cases were we obviously will be able to do as good or
better. As the x86 backend improves, more cases can be simplified.

[craig.topper]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

588

If everything is const can we someone use the immediate as a lookup table instead of manually describing every case?

588

somehow* not someone

[craig.topper]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

585

Do we need to make sure we are looking at vectors of ConstantInts rather than vectors of ConstantExpr?

[pengfei]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

591–594

Maybe better to do it in FE and remove all these intrinsics finally?

[goldstein.w.n]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

585

Will the ALU not fold with ConstantExpr? How can I test that?

588

If everything is const can we someone use the immediate as a lookup table instead of manually describing every case?

Yes although there are some IMM where we only need AC/AB/BC so think we would still want to check the IMM.

Are you concerned about compile time overhead? If not keeping the same logic for const / non-const seems simpler and less error prone.

591–594

What do you mean? Like in the header for _mm_ternarylogic_.... add a switch statement? Or something else?

But would prefer to keep it somewhere we have const/non-const info on A/B/C because it will currently cause regressions to simplify many of the cases (working on a patch for backend generation, but a ways away).

[goldstein.w.n]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

588

If everything is const can we someone use the immediate as a lookup table instead of manually describing every case?

Yes although there are some IMM where we only need AC/AB/BC so think we would still want to check the IMM.

Are you concerned about compile time overhead? If not keeping the same logic for const / non-const seems simpler and less error prone.

If all three are const we can just implement it with a loop above all the bits. Its just:

for(i : bitwidth()) {
res[i] = (imm >> ((A[i] << 2) + (B[i] << 1) + (C[i] << 0))) & 1
}

but still issue of we will miss cases where C is non-constant but also truly unneeded.

[craig.topper]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

585

ConstantExpr can involve things that are conceptually constant but aren’t known to the compiler. Like the address of a global variable. SelectionDAG will expand ConstantExprs into instructions.

588

I really want there to be some nice algorithm to do this optimization. It’s not easy to see that all 256 entries in the switch are correct. We have to trust that you transcribed them from Intel’s table correctly or we need to check that ourselves.

[goldstein.w.n]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

585

I see, the issue with isa<ConstantInt> is then it only works for splats, is there a check for evaluatable constant?

588

I really want there to be some nice algorithm to do this optimization. It’s not easy to see that all 256 entries in the switch are correct. We have to trust that you transcribed them from Intel’s table correctly or we need to check that ourselves.

We can do the constant case with the algorithm but I couldn't figure out how to generic turn the imm -> logic ops.

not intels table (don't know if there is one).
Use the following not so clean pyscript: https://godbolt.org/z/aahK7qEhM
tested that the results are correct (turned off the constant guards and use the following): https://godbolt.org/z/KMrMdoY3f

[craig.topper]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

585

isa<ConstantInt> doesn't work for splats. It only works for scalars. Splats are usually handled in InstCombine by using m_APInt which calls getSplatValue() on the Constant.

I think you would need to loop over all elements, call getAggregateElement, and make sure it returns a ConstantInt for each element. From a quick search, I see InstCombinerImpl::dyn_castNegVal does something like that.

588

Intel has a table at the start of CHAPTER 5 INSTRUCTION SET REFERENCE, V in Volume 2C of the SDM

[goldstein.w.n]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

585

Thanks, will update.

588

That would have saved a moment :/

Given that they recommend a table as well not sure if there is a generic algorithm that has reasonable perf.

[goldstein.w.n]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

591–594

What do you mean? Like in the header for _mm_ternarylogic_.... add a switch statement? Or something else?

But would prefer to keep it somewhere we have const/non-const info on A/B/C because it will currently cause regressions to simplify many of the cases (working on a patch for backend generation, but a ways away).

We can handle the constants algorithimically if you prefer (my feeling however is 1 implementation is preferred and if we need the table would be simpler to just use that).

[craig.topper]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

591–594

How many entries are there that do something for non-constant in the current patch?

I'm bit nervous about replacing vpternlog intrinsics with complex sequences and hoping to turn it back in the backend. If there are many logic ops involved we might make a different decision than the programmer. We already get bugs from time to time that we changed the shuffles that a programmer wrote and generated worse code.

[goldstein.w.n]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

591–594

How many entries are there that do something for non-constant in the current patch?

At the moment only have 11 cases actually on. The rest are placaeholder for when backend gets improved.

I'm bit nervous about replacing vpternlog intrinsics with complex sequences and hoping to turn it back in the backend. If there are many logic ops involved we might make a different decision than the programmer. We already get bugs from time to time that we changed the shuffles that a programmer wrote and generated worse code.

Agreed, thats why most are off at the moment. I am working on a patch to improve vpternlog generation at which point we will hopefully be able to turn more on w.o causing regressions.

Think ternlogd is a bit simpler. Unlike shuffles the pattern for creating them is pretty simple. Take an arbitrary number of logic ops that use the same 3 operands -> ternlog. The issue we have now is we only look at 3-ops instead of looking at 3-operands.

But OFC will test results and won't turn on cases that still cause regressions.

[goldstein.w.n]

Correct constant detection for vec + verification

[goldstein.w.n]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

588

I really want there to be some nice algorithm to do this optimization. It’s not easy to see that all 256 entries in the switch are correct. We have to trust that you transcribed them from Intel’s table correctly or we need to check that ourselves.

I added asserts for all cases. Could still be a typeof in the future if someone changes the return but forgets to do the assert, but does verify that what we have now is correct.

[goldstein.w.n]

Make verification impossible to mess up

[goldstein.w.n]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

588

I really want there to be some nice algorithm to do this optimization. It’s not easy to see that all 256 entries in the switch are correct. We have to trust that you transcribed them from Intel’s table correctly or we need to check that ourselves.

I added asserts for all cases. Could still be a typeof in the future if someone changes the return but forgets to do the assert, but does verify that what we have now is correct.

Changed so it tracks the imm along with creating the return value. Should be impossible to accidentally mess up now.

[nikic]

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

590

You are looking for match(V, m_ImmConstant()) I think.

[goldstein.w.n]

Use match(V, m_ImmConstant())

[goldstein.w.n]

done.

[goldstein.w.n]

Fix from imm 3rd arg

[goldstein.w.n]

ping.

[pengfei]

llvm/test/Transforms/InstCombine/X86/x86-ternlog.ll

2312

The following constant tests are too tedium and hard to review. Can we use a unittest instead?

[goldstein.w.n]

Add unit tests

[goldstein.w.n]

llvm/test/Transforms/InstCombine/X86/x86-ternlog.ll

2312

Done, see new file TernlogTest.cpp

[pengfei]

LGTM.

llvm/test/Transforms/InstCombine/X86/x86-ternlog.ll

2312

Thanks! Do we still need these constant tests?

llvm/unittests/Transforms/InstCombine/X86/TernlogTest.cpp

188

What is loop used for?

[goldstein.w.n]

llvm/test/Transforms/InstCombine/X86/x86-ternlog.ll

2312

Thanks! Do we still need these constant tests?

I prefer to keep. I was less so trying to test that the values produced a correct than sanity test that we properly get constant folding in codegen.

llvm/unittests/Transforms/InstCombine/X86/TernlogTest.cpp

188

Because the tests use random values it may make sense to increase number of rand iterations. I can remove if you think its unnecessary.

[goldstein.w.n]

Remove unnecessary NTests loop

[goldstein.w.n]

llvm/unittests/Transforms/InstCombine/X86/TernlogTest.cpp

188

Removed it.

[mehdi_amini]

llvm/unittests/Transforms/InstCombine/X86/CMakeLists.txt

14

This breaks the build when the X86 target is not configured, you likely need to filter out this directory somehow. Can you look into it quickly or revert temporarily?

[goldstein.w.n]

llvm/unittests/Transforms/InstCombine/X86/CMakeLists.txt

14

Reverted, Sorry about that!

[mehdi_amini]

llvm/unittests/Transforms/InstCombine/X86/CMakeLists.txt

14

Thanks!

(FYI: in general revert commit should mention the reason for the revert)

[goldstein.w.n]

Fix test issues

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

if (match(CarryIn, PatternMatch::m_ZeroInt())) {
     Value *Res = PoisonValue::get(RetTy);
     Res = Builder.CreateInsertValue(Res, UAddOV, 0);
     return Builder.CreateInsertValue(Res, UAddResult, 1);
   }
 
   return nullptr;
 }
 
+static Value *simplifyTernarylogic(const IntrinsicInst &II,
+                                   InstCombiner::BuilderTy &Builder) {
+
+  auto *ArgImm = dyn_cast<ConstantInt>(II.getArgOperand(3));
+  if (!ArgImm || ArgImm->getValue().uge(256))
+    return nullptr;
+
+  Value *ArgA = II.getArgOperand(0);
+  Value *ArgB = II.getArgOperand(1);
+  Value *ArgC = II.getArgOperand(2);
+
+  Type *Ty = II.getType();
+
+  auto Or = [&](auto Lhs, auto Rhs) -> std::pair<Value *, uint8_t> {
+    return {Builder.CreateOr(Lhs.first, Rhs.first), Lhs.second | Rhs.second};
+  };
+  auto Xor = [&](auto Lhs, auto Rhs) -> std::pair<Value *, uint8_t> {
+    return {Builder.CreateXor(Lhs.first, Rhs.first), Lhs.second ^ Rhs.second};
+  };
+  auto And = [&](auto Lhs, auto Rhs) -> std::pair<Value *, uint8_t> {
+    return {Builder.CreateAnd(Lhs.first, Rhs.first), Lhs.second & Rhs.second};
+  };
+  auto Not = [&](auto V) -> std::pair<Value *, uint8_t> {
+    return {Builder.CreateNot(V.first), ~V.second};
+  };
+  auto Nor = [&](auto Lhs, auto Rhs) { return Not(Or(Lhs, Rhs)); };
+  auto Xnor = [&](auto Lhs, auto Rhs) { return Not(Xor(Lhs, Rhs)); };
+  auto Nand = [&](auto Lhs, auto Rhs) { return Not(And(Lhs, Rhs)); };
+
+  bool AIsConst = match(ArgA, PatternMatch::m_ImmConstant());
+  bool BIsConst = match(ArgB, PatternMatch::m_ImmConstant());
+  bool CIsConst = match(ArgC, PatternMatch::m_ImmConstant());
+
+  bool ABIsConst = AIsConst && BIsConst;
+  bool ACIsConst = AIsConst && CIsConst;
+  bool BCIsConst = BIsConst && CIsConst;
+  bool ABCIsConst = AIsConst && BIsConst && CIsConst;
+
+  // Use for verification. Its a big table. Its difficult to go from Imm ->
+  // logic ops, but easy to verify that a set of logic ops is correct. We track
+  // the logic ops through the second value in the pair. At the end it should
+  // equal Imm.
+  std::pair<Value *, uint8_t> A = {ArgA, 0xf0};
+  std::pair<Value *, uint8_t> B = {ArgB, 0xcc};
+  std::pair<Value *, uint8_t> C = {ArgC, 0xaa};
+  std::pair<Value *, uint8_t> Res = {nullptr, 0};
+
+  // Currently we only handle cases that convert directly to another instruction
+  // or cases where all the ops are constant.  This is because we don't properly
+  // handle creating ternary ops in the backend, so splitting them here may
+  // cause regressions. As the backend improves, uncomment more cases.
+
+  uint8_t Imm = ArgImm->getValue().getZExtValue();
+  switch (Imm) {
+  case 0x0:
+    Res = {Constant::getNullValue(Ty), 0};
+    break;
+  case 0x1:
+    if (ABCIsConst)
+      Res = Nor(Or(A, B), C);
+    break;
+  case 0x2:
+    if (ABCIsConst)
+      Res = And(Nor(A, B), C);
+    break;
+  case 0x3:
+    if (ABIsConst)
+      Res = Nor(A, B);
+    break;
+  case 0x4:
+    if (ABCIsConst)
+      Res = And(Nor(A, C), B);
+    break;
+  case 0x5:
+    if (ACIsConst)
+      Res = Nor(A, C);
+    break;
+  case 0x6:
+    if (ABCIsConst)
+      Res = Nor(A, Xnor(B, C));
+    break;
+  case 0x7:
+    if (ABCIsConst)
+      Res = Nor(A, And(B, C));
+    break;
+  case 0x8:
+    if (ABCIsConst)
+      Res = Nor(A, Nand(B, C));
+    break;
+  case 0x9:
+    if (ABCIsConst)
+      Res = Nor(A, Xor(B, C));
+    break;
+  case 0xa:
+    if (ACIsConst)
+      Res = Nor(A, Not(C));
+    break;
+  case 0xb:
+    if (ABCIsConst)
+      Res = Nor(A, Nor(C, Not(B)));
+    break;
+  case 0xc:
+    if (ABIsConst)
+      Res = Nor(A, Not(B));
+    break;
+  case 0xd:
+    if (ABCIsConst)
+      Res = Nor(A, Nor(B, Not(C)));
+    break;
+  case 0xe:
+    if (ABCIsConst)
+      Res = Nor(A, Nor(B, C));
+    break;
+  case 0xf:
+    Res = Not(A);
+    break;
+  case 0x10:
+    if (ABCIsConst)
+      Res = And(A, Nor(B, C));
+    break;
+  case 0x11:
+    if (BCIsConst)
+      Res = Nor(B, C);
+    break;
+  case 0x12:
+    if (ABCIsConst)
+      Res = Nor(Xnor(A, C), B);
+    break;
+  case 0x13:
+    if (ABCIsConst)
+      Res = Nor(And(A, C), B);
+    break;
+  case 0x14:
+    if (ABCIsConst)
+      Res = Nor(Xnor(A, B), C);
+    break;
+  case 0x15:
+    if (ABCIsConst)
+      Res = Nor(And(A, B), C);
+    break;
+  case 0x16:
+    if (ABCIsConst)
+      Res = Xor(Xor(A, B), And(Nand(A, B), C));
+    break;
+  case 0x17:
+    if (ABCIsConst)
+      Res = Xor(Or(A, B), Or(Xnor(A, B), C));
+    break;
+  case 0x18:
+    if (ABCIsConst)
+      Res = Nor(Xnor(A, B), Xnor(A, C));
+    break;
+  case 0x19:
+    if (ABCIsConst)
+      Res = And(Nand(A, B), Xnor(B, C));
+    break;
+  case 0x1a:
+    if (ABCIsConst)
+      Res = Xor(A, Or(And(A, B), C));
+    break;
+  case 0x1b:
+    if (ABCIsConst)
+      Res = Xor(A, Or(Xnor(A, B), C));
+    break;
+  case 0x1c:
+    if (ABCIsConst)
+      Res = Xor(A, Or(And(A, C), B));
+    break;
+  case 0x1d:
+    if (ABCIsConst)
+      Res = Xor(A, Or(Xnor(A, C), B));
+    break;
+  case 0x1e:
+    if (ABCIsConst)
+      Res = Xor(A, Or(B, C));
+    break;
+  case 0x1f:
+    if (ABCIsConst)
+      Res = Nand(A, Or(B, C));
+    break;
+  case 0x20:
+    if (ABCIsConst)
+      Res = Nor(Nand(A, C), B);
+    break;
+  case 0x21:
+    if (ABCIsConst)
+      Res = Nor(Xor(A, C), B);
+    break;
+  case 0x22:
+    if (BCIsConst)
+      Res = Nor(B, Not(C));
+    break;
+  case 0x23:
+    if (ABCIsConst)
+      Res = Nor(B, Nor(C, Not(A)));
+    break;
+  case 0x24:
+    if (ABCIsConst)
+      Res = Nor(Xnor(A, B), Xor(A, C));
+    break;
+  case 0x25:
+    if (ABCIsConst)
+      Res = Xor(A, Nand(Nand(A, B), C));
+    break;
+  case 0x26:
+    if (ABCIsConst)
+      Res = And(Nand(A, B), Xor(B, C));
+    break;
+  case 0x27:
+    if (ABCIsConst)
+      Res = Xor(Or(Xnor(A, B), C), B);
+    break;
+  case 0x28:
+    if (ABCIsConst)
+      Res = And(Xor(A, B), C);
+    break;
+  case 0x29:
+    if (ABCIsConst)
+      Res = Xor(Xor(A, B), Nor(And(A, B), C));
+    break;
+  case 0x2a:
+    if (ABCIsConst)
+      Res = And(Nand(A, B), C);
+    break;
+  case 0x2b:
+    if (ABCIsConst)
+      Res = Xor(Or(Xnor(A, B), Xor(A, C)), A);
+    break;
+  case 0x2c:
+    if (ABCIsConst)
+      Res = Nor(Xnor(A, B), Nor(B, C));
+    break;
+  case 0x2d:
+    if (ABCIsConst)
+      Res = Xor(A, Or(B, Not(C)));
+    break;
+  case 0x2e:
+    if (ABCIsConst)
+      Res = Xor(A, Or(Xor(A, C), B));
+    break;
+  case 0x2f:
+    if (ABCIsConst)
+      Res = Nand(A, Or(B, Not(C)));
+    break;
+  case 0x30:
+    if (ABIsConst)
+      Res = Nor(B, Not(A));
+    break;
+  case 0x31:
+    if (ABCIsConst)
+      Res = Nor(Nor(A, Not(C)), B);
+    break;
+  case 0x32:
+    if (ABCIsConst)
+      Res = Nor(Nor(A, C), B);
+    break;
+  case 0x33:
+    Res = Not(B);
+    break;
+  case 0x34:
+    if (ABCIsConst)
+      Res = And(Xor(A, B), Nand(B, C));
+    break;
+  case 0x35:
+    if (ABCIsConst)
+      Res = Xor(B, Or(A, Xnor(B, C)));
+    break;
+  case 0x36:
+    if (ABCIsConst)
+      Res = Xor(Or(A, C), B);
+    break;
+  case 0x37:
+    if (ABCIsConst)
+      Res = Nand(Or(A, C), B);
+    break;
+  case 0x38:
+    if (ABCIsConst)
+      Res = Nor(Xnor(A, B), Nor(A, C));
+    break;
+  case 0x39:
+    if (ABCIsConst)
+      Res = Xor(Or(A, Not(C)), B);
+    break;
+  case 0x3a:
+    if (ABCIsConst)
+      Res = Xor(B, Or(A, Xor(B, C)));
+    break;
+  case 0x3b:
+    if (ABCIsConst)
+      Res = Nand(Or(A, Not(C)), B);
+    break;
+  case 0x3c:
+    Res = Xor(A, B);
+    break;
+  case 0x3d:
+    if (ABCIsConst)
+      Res = Xor(A, Or(Nor(A, C), B));
+    break;
+  case 0x3e:
+    if (ABCIsConst)
+      Res = Xor(A, Or(Nor(A, Not(C)), B));
+    break;
+  case 0x3f:
+    if (ABIsConst)
+      Res = Nand(A, B);
+    break;
+  case 0x40:
+    if (ABCIsConst)
+      Res = Nor(Nand(A, B), C);
+    break;
+  case 0x41:
+    if (ABCIsConst)
+      Res = Nor(Xor(A, B), C);
+    break;
+  case 0x42:
+    if (ABCIsConst)
+      Res = Nor(Xor(A, B), Xnor(A, C));
+    break;
+  case 0x43:
+    if (ABCIsConst)
+      Res = Xor(A, Nand(Nand(A, C), B));
+    break;
+  case 0x44:
+    if (BCIsConst)
+      Res = Nor(C, Not(B));
+    break;
+  case 0x45:
+    if (ABCIsConst)
+      Res = Nor(Nor(B, Not(A)), C);
+    break;
+  case 0x46:
+    if (ABCIsConst)
+      Res = Xor(Or(And(A, C), B), C);
+    break;
+  case 0x47:
+    if (ABCIsConst)
+      Res = Xor(Or(Xnor(A, C), B), C);
+    break;
+  case 0x48:
+    if (ABCIsConst)
+      Res = And(Xor(A, C), B);
+    break;
+  case 0x49:
+    if (ABCIsConst)
+      Res = Xor(Or(Xnor(A, B), And(A, C)), C);
+    break;
+  case 0x4a:
+    if (ABCIsConst)
+      Res = Nor(Xnor(A, C), Nor(B, C));
+    break;
+  case 0x4b:
+    if (ABCIsConst)
+      Res = Xor(A, Or(C, Not(B)));
+    break;
+  case 0x4c:
+    if (ABCIsConst)
+      Res = And(Nand(A, C), B);
+    break;
+  case 0x4d:
+    if (ABCIsConst)
+      Res = Xor(Or(Xor(A, B), Xnor(A, C)), A);
+    break;
+  case 0x4e:
+    if (ABCIsConst)
+      Res = Xor(A, Or(Xor(A, B), C));
+    break;
+  case 0x4f:
+    if (ABCIsConst)
+      Res = Nand(A, Nand(B, Not(C)));
+    break;
+  case 0x50:
+    if (ACIsConst)
+      Res = Nor(C, Not(A));
+    break;
+  case 0x51:
+    if (ABCIsConst)
+      Res = Nor(Nor(A, Not(B)), C);
+    break;
+  case 0x52:
+    if (ABCIsConst)
+      Res = And(Xor(A, C), Nand(B, C));
+    break;
+  case 0x53:
+    if (ABCIsConst)
+      Res = Xor(Or(Xnor(B, C), A), C);
+    break;
+  case 0x54:
+    if (ABCIsConst)
+      Res = Nor(Nor(A, B), C);
+    break;
+  case 0x55:
+    Res = Not(C);
+    break;
+  case 0x56:
+    if (ABCIsConst)
+      Res = Xor(Or(A, B), C);
+    break;
+  case 0x57:
+    if (ABCIsConst)
+      Res = Nand(Or(A, B), C);
+    break;
+  case 0x58:
+    if (ABCIsConst)
+      Res = Nor(Nor(A, B), Xnor(A, C));
+    break;
+  case 0x59:
+    if (ABCIsConst)
+      Res = Xor(Or(A, Not(B)), C);
+    break;
+  case 0x5a:
+    Res = Xor(A, C);
+    break;
+  case 0x5b:
+    if (ABCIsConst)
+      Res = Xor(A, Or(Nor(A, B), C));
+    break;
+  case 0x5c:
+    if (ABCIsConst)
+      Res = Xor(Or(Xor(B, C), A), C);
+    break;
+  case 0x5d:
+    if (ABCIsConst)
+      Res = Nand(Or(A, Not(B)), C);
+    break;
+  case 0x5e:
+    if (ABCIsConst)
+      Res = Xor(A, Or(Nor(A, Not(B)), C));
+    break;
+  case 0x5f:
+    if (ACIsConst)
+      Res = Nand(A, C);
+    break;
+  case 0x60:
+    if (ABCIsConst)
+      Res = And(A, Xor(B, C));
+    break;
+  case 0x61:
+    if (ABCIsConst)
+      Res = Xor(Or(Xnor(A, B), And(B, C)), C);
+    break;
+  case 0x62:
+    if (ABCIsConst)
+      Res = Nor(Nor(A, C), Xnor(B, C));
+    break;
+  case 0x63:
+    if (ABCIsConst)
+      Res = Xor(B, Or(C, Not(A)));
+    break;
+  case 0x64:
+    if (ABCIsConst)
+      Res = Nor(Nor(A, B), Xnor(B, C));
+    break;
+  case 0x65:
+    if (ABCIsConst)
+      Res = Xor(Or(B, Not(A)), C);
+    break;
+  case 0x66:
+    Res = Xor(B, C);
+    break;
+  case 0x67:
+    if (ABCIsConst)
+      Res = Or(Nor(A, B), Xor(B, C));
+    break;
+  case 0x68:
+    if (ABCIsConst)
+      Res = Xor(Xor(A, B), Nor(Nor(A, B), C));
+    break;
+  case 0x69:
+    if (ABCIsConst)
+      Res = Xor(Xnor(A, B), C);
+    break;
+  case 0x6a:
+    if (ABCIsConst)
+      Res = Xor(And(A, B), C);
+    break;
+  case 0x6b:
+    if (ABCIsConst)
+      Res = Or(Nor(A, B), Xor(Xnor(A, B), C));
+    break;
+  case 0x6c:
+    if (ABCIsConst)
+      Res = Xor(And(A, C), B);
+    break;
+  case 0x6d:
+    if (ABCIsConst)
+      Res = Xor(Or(Xnor(A, B), Nor(A, C)), C);
+    break;
+  case 0x6e:
+    if (ABCIsConst)
+      Res = Or(Nor(A, Not(B)), Xor(B, C));
+    break;
+  case 0x6f:
+    if (ABCIsConst)
+      Res = Nand(A, Xnor(B, C));
+    break;
+  case 0x70:
+    if (ABCIsConst)
+      Res = And(A, Nand(B, C));
+    break;
+  case 0x71:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xor(A, B), Xor(A, C)), A);
+    break;
+  case 0x72:
+    if (ABCIsConst)
+      Res = Xor(Or(Xor(A, B), C), B);
+    break;
+  case 0x73:
+    if (ABCIsConst)
+      Res = Nand(Nand(A, Not(C)), B);
+    break;
+  case 0x74:
+    if (ABCIsConst)
+      Res = Xor(Or(Xor(A, C), B), C);
+    break;
+  case 0x75:
+    if (ABCIsConst)
+      Res = Nand(Nand(A, Not(B)), C);
+    break;
+  case 0x76:
+    if (ABCIsConst)
+      Res = Xor(B, Or(Nor(B, Not(A)), C));
+    break;
+  case 0x77:
+    if (BCIsConst)
+      Res = Nand(B, C);
+    break;
+  case 0x78:
+    if (ABCIsConst)
+      Res = Xor(A, And(B, C));
+    break;
+  case 0x79:
+    if (ABCIsConst)
+      Res = Xor(Or(Xnor(A, B), Nor(B, C)), C);
+    break;
+  case 0x7a:
+    if (ABCIsConst)
+      Res = Or(Xor(A, C), Nor(B, Not(A)));
+    break;
+  case 0x7b:
+    if (ABCIsConst)
+      Res = Nand(Xnor(A, C), B);
+    break;
+  case 0x7c:
+    if (ABCIsConst)
+      Res = Or(Xor(A, B), Nor(C, Not(A)));
+    break;
+  case 0x7d:
+    if (ABCIsConst)
+      Res = Nand(Xnor(A, B), C);
+    break;
+  case 0x7e:
+    if (ABCIsConst)
+      Res = Or(Xor(A, B), Xor(A, C));
+    break;
+  case 0x7f:
+    if (ABCIsConst)
+      Res = Nand(And(A, B), C);
+    break;
+  case 0x80:
+    if (ABCIsConst)
+      Res = And(And(A, B), C);
+    break;
+  case 0x81:
+    if (ABCIsConst)
+      Res = Nor(Xor(A, B), Xor(A, C));
+    break;
+  case 0x82:
+    if (ABCIsConst)
+      Res = And(Xnor(A, B), C);
+    break;
+  case 0x83:
+    if (ABCIsConst)
+      Res = Nor(Xor(A, B), Nor(C, Not(A)));
+    break;
+  case 0x84:
+    if (ABCIsConst)
+      Res = And(Xnor(A, C), B);
+    break;
+  case 0x85:
+    if (ABCIsConst)
+      Res = Nor(Xor(A, C), Nor(B, Not(A)));
+    break;
+  case 0x86:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xnor(A, B), Nor(B, C)), C);
+    break;
+  case 0x87:
+    if (ABCIsConst)
+      Res = Xor(A, Nand(B, C));
+    break;
+  case 0x88:
+    Res = And(B, C);
+    break;
+  case 0x89:
+    if (ABCIsConst)
+      Res = Xor(B, Nor(Nor(B, Not(A)), C));
+    break;
+  case 0x8a:
+    if (ABCIsConst)
+      Res = And(Nand(A, Not(B)), C);
+    break;
+  case 0x8b:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xor(A, C), B), C);
+    break;
+  case 0x8c:
+    if (ABCIsConst)
+      Res = And(Nand(A, Not(C)), B);
+    break;
+  case 0x8d:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xor(A, B), C), B);
+    break;
+  case 0x8e:
+    if (ABCIsConst)
+      Res = Xor(Or(Xor(A, B), Xor(A, C)), A);
+    break;
+  case 0x8f:
+    if (ABCIsConst)
+      Res = Nand(A, Nand(B, C));
+    break;
+  case 0x90:
+    if (ABCIsConst)
+      Res = And(A, Xnor(B, C));
+    break;
+  case 0x91:
+    if (ABCIsConst)
+      Res = Nor(Nor(A, Not(B)), Xor(B, C));
+    break;
+  case 0x92:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xnor(A, B), Nor(A, C)), C);
+    break;
+  case 0x93:
+    if (ABCIsConst)
+      Res = Xor(Nand(A, C), B);
+    break;
+  case 0x94:
+    if (ABCIsConst)
+      Res = Nor(Nor(A, B), Xor(Xnor(A, B), C));
+    break;
+  case 0x95:
+    if (ABCIsConst)
+      Res = Xor(Nand(A, B), C);
+    break;
+  case 0x96:
+    if (ABCIsConst)
+      Res = Xor(Xor(A, B), C);
+    break;
+  case 0x97:
+    if (ABCIsConst)
+      Res = Xor(Xor(A, B), Or(Nor(A, B), C));
+    break;
+  case 0x98:
+    if (ABCIsConst)
+      Res = Nor(Nor(A, B), Xor(B, C));
+    break;
+  case 0x99:
+    if (BCIsConst)
+      Res = Xnor(B, C);
+    break;
+  case 0x9a:
+    if (ABCIsConst)
+      Res = Xor(Nor(B, Not(A)), C);
+    break;
+  case 0x9b:
+    if (ABCIsConst)
+      Res = Or(Nor(A, B), Xnor(B, C));
+    break;
+  case 0x9c:
+    if (ABCIsConst)
+      Res = Xor(B, Nor(C, Not(A)));
+    break;
+  case 0x9d:
+    if (ABCIsConst)
+      Res = Or(Nor(A, C), Xnor(B, C));
+    break;
+  case 0x9e:
+    if (ABCIsConst)
+      Res = Xor(And(Xor(A, B), Nand(B, C)), C);
+    break;
+  case 0x9f:
+    if (ABCIsConst)
+      Res = Nand(A, Xor(B, C));
+    break;
+  case 0xa0:
+    Res = And(A, C);
+    break;
+  case 0xa1:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(Nor(A, Not(B)), C));
+    break;
+  case 0xa2:
+    if (ABCIsConst)
+      Res = And(Or(A, Not(B)), C);
+    break;
+  case 0xa3:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xor(B, C), A), C);
+    break;
+  case 0xa4:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(Nor(A, B), C));
+    break;
+  case 0xa5:
+    if (ACIsConst)
+      Res = Xnor(A, C);
+    break;
+  case 0xa6:
+    if (ABCIsConst)
+      Res = Xor(Nor(A, Not(B)), C);
+    break;
+  case 0xa7:
+    if (ABCIsConst)
+      Res = Or(Nor(A, B), Xnor(A, C));
+    break;
+  case 0xa8:
+    if (ABCIsConst)
+      Res = And(Or(A, B), C);
+    break;
+  case 0xa9:
+    if (ABCIsConst)
+      Res = Xor(Nor(A, B), C);
+    break;
+  case 0xaa:
+    Res = C;
+    break;
+  case 0xab:
+    if (ABCIsConst)
+      Res = Or(Nor(A, B), C);
+    break;
+  case 0xac:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xnor(B, C), A), C);
+    break;
+  case 0xad:
+    if (ABCIsConst)
+      Res = Or(Xnor(A, C), And(B, C));
+    break;
+  case 0xae:
+    if (ABCIsConst)
+      Res = Or(Nor(A, Not(B)), C);
+    break;
+  case 0xaf:
+    if (ACIsConst)
+      Res = Or(C, Not(A));
+    break;
+  case 0xb0:
+    if (ABCIsConst)
+      Res = And(A, Nand(B, Not(C)));
+    break;
+  case 0xb1:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(Xor(A, B), C));
+    break;
+  case 0xb2:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xor(A, B), Xnor(A, C)), A);
+    break;
+  case 0xb3:
+    if (ABCIsConst)
+      Res = Nand(Nand(A, C), B);
+    break;
+  case 0xb4:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(C, Not(B)));
+    break;
+  case 0xb5:
+    if (ABCIsConst)
+      Res = Or(Xnor(A, C), Nor(B, C));
+    break;
+  case 0xb6:
+    if (ABCIsConst)
+      Res = Xor(And(Xor(A, B), Nand(A, C)), C);
+    break;
+  case 0xb7:
+    if (ABCIsConst)
+      Res = Nand(Xor(A, C), B);
+    break;
+  case 0xb8:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xnor(A, C), B), C);
+    break;
+  case 0xb9:
+    if (ABCIsConst)
+      Res = Xor(Nor(And(A, C), B), C);
+    break;
+  case 0xba:
+    if (ABCIsConst)
+      Res = Or(Nor(B, Not(A)), C);
+    break;
+  case 0xbb:
+    if (BCIsConst)
+      Res = Or(C, Not(B));
+    break;
+  case 0xbc:
+    if (ABCIsConst)
+      Res = Xor(A, And(Nand(A, C), B));
+    break;
+  case 0xbd:
+    if (ABCIsConst)
+      Res = Or(Xor(A, B), Xnor(A, C));
+    break;
+  case 0xbe:
+    if (ABCIsConst)
+      Res = Or(Xor(A, B), C);
+    break;
+  case 0xbf:
+    if (ABCIsConst)
+      Res = Or(Nand(A, B), C);
+    break;
+  case 0xc0:
+    Res = And(A, B);
+    break;
+  case 0xc1:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(Nor(A, Not(C)), B));
+    break;
+  case 0xc2:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(Nor(A, C), B));
+    break;
+  case 0xc3:
+    if (ABIsConst)
+      Res = Xnor(A, B);
+    break;
+  case 0xc4:
+    if (ABCIsConst)
+      Res = And(Or(A, Not(C)), B);
+    break;
+  case 0xc5:
+    if (ABCIsConst)
+      Res = Xor(B, Nor(A, Xor(B, C)));
+    break;
+  case 0xc6:
+    if (ABCIsConst)
+      Res = Xor(Nor(A, Not(C)), B);
+    break;
+  case 0xc7:
+    if (ABCIsConst)
+      Res = Or(Xnor(A, B), Nor(A, C));
+    break;
+  case 0xc8:
+    if (ABCIsConst)
+      Res = And(Or(A, C), B);
+    break;
+  case 0xc9:
+    if (ABCIsConst)
+      Res = Xor(Nor(A, C), B);
+    break;
+  case 0xca:
+    if (ABCIsConst)
+      Res = Xor(B, Nor(A, Xnor(B, C)));
+    break;
+  case 0xcb:
+    if (ABCIsConst)
+      Res = Or(Xnor(A, B), And(B, C));
+    break;
+  case 0xcc:
+    Res = B;
+    break;
+  case 0xcd:
+    if (ABCIsConst)
+      Res = Or(Nor(A, C), B);
+    break;
+  case 0xce:
+    if (ABCIsConst)
+      Res = Or(Nor(A, Not(C)), B);
+    break;
+  case 0xcf:
+    if (ABIsConst)
+      Res = Or(B, Not(A));
+    break;
+  case 0xd0:
+    if (ABCIsConst)
+      Res = And(A, Or(B, Not(C)));
+    break;
+  case 0xd1:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(Xor(A, C), B));
+    break;
+  case 0xd2:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(B, Not(C)));
+    break;
+  case 0xd3:
+    if (ABCIsConst)
+      Res = Or(Xnor(A, B), Nor(B, C));
+    break;
+  case 0xd4:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xnor(A, B), Xor(A, C)), A);
+    break;
+  case 0xd5:
+    if (ABCIsConst)
+      Res = Nand(Nand(A, B), C);
+    break;
+  case 0xd6:
+    if (ABCIsConst)
+      Res = Xor(Xor(A, B), Or(And(A, B), C));
+    break;
+  case 0xd7:
+    if (ABCIsConst)
+      Res = Nand(Xor(A, B), C);
+    break;
+  case 0xd8:
+    if (ABCIsConst)
+      Res = Xor(Nor(Xnor(A, B), C), B);
+    break;
+  case 0xd9:
+    if (ABCIsConst)
+      Res = Or(And(A, B), Xnor(B, C));
+    break;
+  case 0xda:
+    if (ABCIsConst)
+      Res = Xor(A, And(Nand(A, B), C));
+    break;
+  case 0xdb:
+    if (ABCIsConst)
+      Res = Or(Xnor(A, B), Xor(A, C));
+    break;
+  case 0xdc:
+    if (ABCIsConst)
+      Res = Or(B, Nor(C, Not(A)));
+    break;
+  case 0xdd:
+    if (BCIsConst)
+      Res = Or(B, Not(C));
+    break;
+  case 0xde:
+    if (ABCIsConst)
+      Res = Or(Xor(A, C), B);
+    break;
+  case 0xdf:
+    if (ABCIsConst)
+      Res = Or(Nand(A, C), B);
+    break;
+  case 0xe0:
+    if (ABCIsConst)
+      Res = And(A, Or(B, C));
+    break;
+  case 0xe1:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(B, C));
+    break;
+  case 0xe2:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(Xnor(A, C), B));
+    break;
+  case 0xe3:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(And(A, C), B));
+    break;
+  case 0xe4:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(Xnor(A, B), C));
+    break;
+  case 0xe5:
+    if (ABCIsConst)
+      Res = Xor(A, Nor(And(A, B), C));
+    break;
+  case 0xe6:
+    if (ABCIsConst)
+      Res = Or(And(A, B), Xor(B, C));
+    break;
+  case 0xe7:
+    if (ABCIsConst)
+      Res = Or(Xnor(A, B), Xnor(A, C));
+    break;
+  case 0xe8:
+    if (ABCIsConst)
+      Res = Xor(Or(A, B), Nor(Xnor(A, B), C));
+    break;
+  case 0xe9:
+    if (ABCIsConst)
+      Res = Xor(Xor(A, B), Nand(Nand(A, B), C));
+    break;
+  case 0xea:
+    if (ABCIsConst)
+      Res = Or(And(A, B), C);
+    break;
+  case 0xeb:
+    if (ABCIsConst)
+      Res = Or(Xnor(A, B), C);
+    break;
+  case 0xec:
+    if (ABCIsConst)
+      Res = Or(And(A, C), B);
+    break;
+  case 0xed:
+    if (ABCIsConst)
+      Res = Or(Xnor(A, C), B);
+    break;
+  case 0xee:
+    Res = Or(B, C);
+    break;
+  case 0xef:
+    if (ABCIsConst)
+      Res = Nand(A, Nor(B, C));
+    break;
+  case 0xf0:
+    Res = A;
+    break;
+  case 0xf1:
+    if (ABCIsConst)
+      Res = Or(A, Nor(B, C));
+    break;
+  case 0xf2:
+    if (ABCIsConst)
+      Res = Or(A, Nor(B, Not(C)));
+    break;
+  case 0xf3:
+    if (ABIsConst)
+      Res = Or(A, Not(B));
+    break;
+  case 0xf4:
+    if (ABCIsConst)
+      Res = Or(A, Nor(C, Not(B)));
+    break;
+  case 0xf5:
+    if (ACIsConst)
+      Res = Or(A, Not(C));
+    break;
+  case 0xf6:
+    if (ABCIsConst)
+      Res = Or(A, Xor(B, C));
+    break;
+  case 0xf7:
+    if (ABCIsConst)
+      Res = Or(A, Nand(B, C));
+    break;
+  case 0xf8:
+    if (ABCIsConst)
+      Res = Or(A, And(B, C));
+    break;
+  case 0xf9:
+    if (ABCIsConst)
+      Res = Or(A, Xnor(B, C));
+    break;
+  case 0xfa:
+    Res = Or(A, C);
+    break;
+  case 0xfb:
+    if (ABCIsConst)
+      Res = Nand(Nor(A, C), B);
+    break;
+  case 0xfc:
+    Res = Or(A, B);
+    break;
+  case 0xfd:
+    if (ABCIsConst)
+      Res = Nand(Nor(A, B), C);
+    break;
+  case 0xfe:
+    if (ABCIsConst)
+      Res = Or(Or(A, B), C);
+    break;
+  case 0xff:
+    Res = {Constant::getAllOnesValue(Ty), 0xff};
+    break;
+  }
+
+  assert(Res.first == nullptr ||
+         Res.second == Imm &&
+             "Simplification of ternary logic does not verify!");
+  return Res.first;
+}
+
 static Value *simplifyX86insertps(const IntrinsicInst &II,
                                   InstCombiner::BuilderTy &Builder) {
   auto *CInt = dyn_cast<ConstantInt>(II.getArgOperand(2));
   if (!CInt)
     return nullptr;
 
   auto *VecTy = cast<FixedVectorType>(II.getType());
   assert(VecTy->getNumElements() == 4 && "insertps with wrong vector type");
X86TTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
 
   case Intrinsic::x86_addcarry_32:
   case Intrinsic::x86_addcarry_64:
     if (Value *V = simplifyX86addcarry(II, IC.Builder)) {
       return IC.replaceInstUsesWith(II, V);
     }
     break;
 
+  case Intrinsic::x86_avx512_pternlog_d_128:
+  case Intrinsic::x86_avx512_pternlog_d_256:
+  case Intrinsic::x86_avx512_pternlog_d_512:
+  case Intrinsic::x86_avx512_pternlog_q_128:
+  case Intrinsic::x86_avx512_pternlog_q_256:
+  case Intrinsic::x86_avx512_pternlog_q_512:
+    if (Value *V = simplifyTernarylogic(II, IC.Builder)) {
+      return IC.replaceInstUsesWith(II, V);
+    }
+    break;
   default:
     break;
   }
   return std::nullopt;
 }
 
 std::optional<Value *> X86TTIImpl::simplifyDemandedUseBitsIntrinsic(
     InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,

llvm/test/CodeGen/X86/ternlog.ll

 declare <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i32 immarg)
 declare <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i32 immarg)
 declare <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i32 immarg)
 declare <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i32 immarg)
 
 define <16 x i32> @vpternlog_d_v512_imm0(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v512_imm0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $0, %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 0)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm1(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v128_imm1:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 14)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_v512_imm15(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v512_imm15:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogq $15, %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:    vpternlogq $51, %zmm0, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 15)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm16(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v128_imm16:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 50)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_v512_imm51(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v512_imm51:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogq $51, %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:    vmovdqa64 %zmm1, %zmm0
+; CHECK-NEXT:    vpternlogq $15, %zmm1, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 51)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm52(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v128_imm52:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 59)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm60(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v512_imm60:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $60, %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:    vpxord %zmm1, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 60)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm61(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v128_imm61:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 84)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm85(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v128_imm85:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogq $85, %xmm2, %xmm1, %xmm0
+; CHECK-NEXT:    vmovdqa %xmm2, %xmm0
+; CHECK-NEXT:    vpternlogq $15, %xmm2, %xmm2, %xmm0
 ; CHECK-NEXT:    retq
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 85)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_v256_imm86(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v256_imm86:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 89)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm90(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v512_imm90:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $90, %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:    vpxord %zmm2, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 90)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm91(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v128_imm91:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 101)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm102(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v512_imm102:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $102, %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:    vpxord %zmm2, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 102)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm103(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v128_imm103:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 135)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm136(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v128_imm136:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $136, %xmm2, %xmm1, %xmm0
+; CHECK-NEXT:    vandps %xmm2, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 136)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_v256_imm137(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v256_imm137:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 159)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm160(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v128_imm160:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $160, %xmm2, %xmm1, %xmm0
+; CHECK-NEXT:    vandps %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 160)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_v256_imm161(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v256_imm161:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 169)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_v256_imm170(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v256_imm170:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $170, %ymm2, %ymm1, %ymm0
+; CHECK-NEXT:    vmovaps %ymm2, %ymm0
 ; CHECK-NEXT:    retq
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 170)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_v512_imm171(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v512_imm171:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 191)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm192(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v512_imm192:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $192, %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:    vpandd %zmm1, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 192)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm193(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v128_imm193:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 203)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm204(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v512_imm204:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $204, %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:    vmovaps %zmm1, %zmm0
 ; CHECK-NEXT:    retq
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 204)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm205(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v128_imm205:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 237)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm238(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v128_imm238:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $238, %xmm2, %xmm1, %xmm0
+; CHECK-NEXT:    vorps %xmm2, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 238)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_v256_imm239(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v256_imm239:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vpternlogq $239, %ymm2, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 239)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm240(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v512_imm240:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $240, %zmm2, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 240)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm241(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v128_imm241:
 ; CHECK:       # %bb.0:

 ; CHECK-NEXT:    retq
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 249)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm250(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v128_imm250:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $250, %xmm2, %xmm1, %xmm0
+; CHECK-NEXT:    vorps %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 250)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_v256_imm251(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v256_imm251:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vpternlogq $251, %ymm2, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 251)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm252(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_d_v512_imm252:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogd $252, %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:    vpord %zmm1, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 252)
   ret <16 x i32> %r
 }
 
 ; This is bitselect pattern
 define <2 x i64> @vpternlog_q_v128_imm253(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v128_imm253:

 ; CHECK-NEXT:    retq
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 254)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_v512_imm255(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) nounwind {
 ; CHECK-LABEL: vpternlog_q_v512_imm255:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpternlogq $255, %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:    vpternlogd $255, %zmm0, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 255)
   ret <8 x i64> %r
 }
 
 define <8 x i32> @vpternlog_vselect_8xi32(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, <8 x i32> %v3) nounwind {
 ; CHECK-LABEL: vpternlog_vselect_8xi32:
 ; CHECK:       # %bb.0:

llvm/test/Transforms/InstCombine/X86/x86-ternlog.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
 
 declare <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i32 immarg)
 declare <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i32 immarg)
 declare <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i32 immarg)
 declare <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i32 immarg)
 declare <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i32 immarg)
 declare <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i32 immarg)
 
 define <16 x i32> @vpternlog_d_v512_imm0(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v512_imm0(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 0)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> zeroinitializer
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 0)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm1(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v128_imm1(
 ; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 1)

 ; CHECK-NEXT:    ret <8 x i32> [[R]]
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 14)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_v512_imm15(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v512_imm15(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 15)
+; CHECK-NEXT:    [[R:%.*]] = xor <8 x i64> [[V0:%.*]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
 ; CHECK-NEXT:    ret <8 x i64> [[R]]
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 15)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm16(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v128_imm16(

 ; CHECK-NEXT:    ret <8 x i32> [[R]]
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 50)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_v512_imm51(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v512_imm51(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 51)
+; CHECK-NEXT:    [[R:%.*]] = xor <8 x i64> [[V1:%.*]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
 ; CHECK-NEXT:    ret <8 x i64> [[R]]
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 51)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm52(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v128_imm52(

 ; CHECK-NEXT:    ret <4 x i64> [[R]]
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 59)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm60(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v512_imm60(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 60)
+; CHECK-NEXT:    [[R:%.*]] = xor <16 x i32> [[V0:%.*]], [[V1:%.*]]
 ; CHECK-NEXT:    ret <16 x i32> [[R]]
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 60)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm61(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v128_imm61(

 ; CHECK-NEXT:    ret <16 x i32> [[R]]
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 84)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm85(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v128_imm85(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 85)
+; CHECK-NEXT:    [[R:%.*]] = xor <2 x i64> [[V2:%.*]], <i64 -1, i64 -1>
 ; CHECK-NEXT:    ret <2 x i64> [[R]]
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 85)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_v256_imm86(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v256_imm86(

 ; CHECK-NEXT:    ret <4 x i64> [[R]]
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 89)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm90(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v512_imm90(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 90)
+; CHECK-NEXT:    [[R:%.*]] = xor <16 x i32> [[V0:%.*]], [[V2:%.*]]
 ; CHECK-NEXT:    ret <16 x i32> [[R]]
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 90)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm91(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v128_imm91(

 ; CHECK-NEXT:    ret <4 x i64> [[R]]
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 101)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm102(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v512_imm102(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 102)
+; CHECK-NEXT:    [[R:%.*]] = xor <16 x i32> [[V1:%.*]], [[V2:%.*]]
 ; CHECK-NEXT:    ret <16 x i32> [[R]]
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 102)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm103(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v128_imm103(

 ; CHECK-NEXT:    ret <8 x i64> [[R]]
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 135)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm136(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v128_imm136(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 136)
+; CHECK-NEXT:    [[R:%.*]] = and <4 x i32> [[V1:%.*]], [[V2:%.*]]
 ; CHECK-NEXT:    ret <4 x i32> [[R]]
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 136)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_v256_imm137(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v256_imm137(

 ; CHECK-NEXT:    ret <8 x i64> [[R]]
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 159)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm160(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v128_imm160(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 160)
+; CHECK-NEXT:    [[R:%.*]] = and <4 x i32> [[V0:%.*]], [[V2:%.*]]
 ; CHECK-NEXT:    ret <4 x i32> [[R]]
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 160)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_v256_imm161(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v256_imm161(

 ; CHECK-NEXT:    ret <2 x i64> [[R]]
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 169)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_v256_imm170(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v256_imm170(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 170)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> [[V2:%.*]]
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 170)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_v512_imm171(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v512_imm171(
 ; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 171)

 ; CHECK-NEXT:    ret <4 x i64> [[R]]
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 191)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm192(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v512_imm192(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 192)
+; CHECK-NEXT:    [[R:%.*]] = and <16 x i32> [[V0:%.*]], [[V1:%.*]]
 ; CHECK-NEXT:    ret <16 x i32> [[R]]
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 192)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm193(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v128_imm193(

 ; CHECK-NEXT:    ret <4 x i64> [[R]]
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 203)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm204(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v512_imm204(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 204)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> [[V1:%.*]]
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 204)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm205(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v128_imm205(
 ; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 205)

 ; CHECK-NEXT:    ret <8 x i64> [[R]]
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 237)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm238(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v128_imm238(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 238)
+; CHECK-NEXT:    [[R:%.*]] = or <4 x i32> [[V1:%.*]], [[V2:%.*]]
 ; CHECK-NEXT:    ret <4 x i32> [[R]]
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 238)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_v256_imm239(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v256_imm239(
 ; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 239)
 ; CHECK-NEXT:    ret <4 x i64> [[R]]
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 239)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm240(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v512_imm240(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 240)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> [[V0:%.*]]
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 240)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm241(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v128_imm241(
 ; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 241)

 ; CHECK-NEXT:    ret <8 x i64> [[R]]
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 249)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_v128_imm250(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v128_imm250(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 250)
+; CHECK-NEXT:    [[R:%.*]] = or <4 x i32> [[V0:%.*]], [[V2:%.*]]
 ; CHECK-NEXT:    ret <4 x i32> [[R]]
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 250)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_v256_imm251(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v256_imm251(
 ; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 251)
 ; CHECK-NEXT:    ret <4 x i64> [[R]]
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 251)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_v512_imm252(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
 ; CHECK-LABEL: @vpternlog_d_v512_imm252(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 252)
+; CHECK-NEXT:    [[R:%.*]] = or <16 x i32> [[V0:%.*]], [[V1:%.*]]
 ; CHECK-NEXT:    ret <16 x i32> [[R]]
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 252)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_v128_imm253(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v128_imm253(

 ; CHECK-NEXT:    ret <8 x i32> [[R]]
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 254)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_v512_imm255(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
 ; CHECK-LABEL: @vpternlog_q_v512_imm255(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 255)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 255)
   ret <8 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm0() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm0(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 0, i32 6, i32 1, i32 8, i32 1, i32 8, i32 7, i32 9, i32 1, i32 0, i32 8, i32 8, i32 4, i32 7, i32 0, i32 3>, <16 x i32> <i32 2, i32 7, i32 1, i32 6, i32 8, i32 5, i32 0, i32 2, i32 3, i32 5, i32 6, i32 4, i32 9, i32 4, i32 4, i32 5>, <16 x i32> <i32 2, i32 2, i32 0, i32 9, i32 3, i32 1, i32 2, i32 0, i32 8, i32 0, i32 8, i32 5, i32 5, i32 1, i32 4, i32 9>, i32 0)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> zeroinitializer
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 0, i32 6, i32 1, i32 8, i32 1, i32 8, i32 7, i32 9, i32 1, i32 0, i32 8, i32 8, i32 4, i32 7, i32 0, i32 3>, <16 x i32> <i32 2, i32 7, i32 1, i32 6, i32 8, i32 5, i32 0, i32 2, i32 3, i32 5, i32 6, i32 4, i32 9, i32 4, i32 4, i32 5>, <16 x i32> <i32 2, i32 2, i32 0, i32 9, i32 3, i32 1, i32 2, i32 0, i32 8, i32 0, i32 8, i32 5, i32 5, i32 1, i32 4, i32 9>, i32 0)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm1() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm1(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 0>, <2 x i64> <i64 6, i64 1>, <2 x i64> <i64 1, i64 9>, i32 1)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -8, i64 -10>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 0>, <2 x i64> <i64 6, i64 1>, <2 x i64> <i64 1, i64 9>, i32 1)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm2() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm2(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 3, i32 4, i32 2, i32 4, i32 7, i32 6, i32 7>, <8 x i32> <i32 9, i32 6, i32 3, i32 5, i32 3, i32 5, i32 0, i32 9>, <8 x i32> <i32 1, i32 5, i32 4, i32 2, i32 6, i32 6, i32 4, i32 9>, i32 2)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> zeroinitializer
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 3, i32 4, i32 2, i32 4, i32 7, i32 6, i32 7>, <8 x i32> <i32 9, i32 6, i32 3, i32 5, i32 3, i32 5, i32 0, i32 9>, <8 x i32> <i32 1, i32 5, i32 4, i32 2, i32 6, i32 6, i32 4, i32 9>, i32 2)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm3() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm3(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 4, i64 7, i64 0, i64 6, i64 5, i64 5, i64 5>, <8 x i64> <i64 8, i64 1, i64 8, i64 7, i64 3, i64 7, i64 1, i64 0>, <8 x i64> <i64 7, i64 8, i64 8, i64 2, i64 3, i64 0, i64 7, i64 5>, i32 3)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -12, i64 -6, i64 -16, i64 -8, i64 -8, i64 -8, i64 -6, i64 -6>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 4, i64 7, i64 0, i64 6, i64 5, i64 5, i64 5>, <8 x i64> <i64 8, i64 1, i64 8, i64 7, i64 3, i64 7, i64 1, i64 0>, <8 x i64> <i64 7, i64 8, i64 8, i64 2, i64 3, i64 0, i64 7, i64 5>, i32 3)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm4() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm4(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 9, i32 1, i32 7>, <4 x i32> <i32 6, i32 0, i32 9, i32 9>, <4 x i32> <i32 0, i32 8, i32 1, i32 1>, i32 4)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 6, i32 0, i32 8, i32 8>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 9, i32 1, i32 7>, <4 x i32> <i32 6, i32 0, i32 9, i32 9>, <4 x i32> <i32 0, i32 8, i32 1, i32 1>, i32 4)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm5() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm5(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 2, i64 5, i64 5>, <4 x i64> <i64 5, i64 0, i64 6, i64 5>, <4 x i64> <i64 6, i64 3, i64 2, i64 5>, i32 5)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -8, i64 -4, i64 -8, i64 -6>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 2, i64 5, i64 5>, <4 x i64> <i64 5, i64 0, i64 6, i64 5>, <4 x i64> <i64 6, i64 3, i64 2, i64 5>, i32 5)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm6() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm6(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 2, i32 7, i32 5, i32 5, i32 5, i32 0, i32 3, i32 3, i32 2, i32 6, i32 3, i32 4, i32 3, i32 9, i32 4>, <16 x i32> <i32 9, i32 3, i32 3, i32 6, i32 7, i32 4, i32 0, i32 9, i32 4, i32 9, i32 2, i32 4, i32 7, i32 1, i32 3, i32 8>, <16 x i32> <i32 1, i32 1, i32 9, i32 0, i32 7, i32 0, i32 1, i32 8, i32 4, i32 3, i32 4, i32 2, i32 1, i32 5, i32 0, i32 7>, i32 6)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 8, i32 0, i32 8, i32 2, i32 0, i32 0, i32 1, i32 0, i32 0, i32 8, i32 0, i32 4, i32 2, i32 4, i32 2, i32 11>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 2, i32 7, i32 5, i32 5, i32 5, i32 0, i32 3, i32 3, i32 2, i32 6, i32 3, i32 4, i32 3, i32 9, i32 4>, <16 x i32> <i32 9, i32 3, i32 3, i32 6, i32 7, i32 4, i32 0, i32 9, i32 4, i32 9, i32 2, i32 4, i32 7, i32 1, i32 3, i32 8>, <16 x i32> <i32 1, i32 1, i32 9, i32 0, i32 7, i32 0, i32 1, i32 8, i32 4, i32 3, i32 4, i32 2, i32 1, i32 5, i32 0, i32 7>, i32 6)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm7() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm7(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 2>, <2 x i64> <i64 0, i64 5>, <2 x i64> <i64 1, i64 6>, i32 7)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -8, i64 -7>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 2>, <2 x i64> <i64 0, i64 5>, <2 x i64> <i64 1, i64 6>, i32 7)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm8() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm8(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 1, i32 7, i32 9, i32 8, i32 8, i32 9, i32 4>, <8 x i32> <i32 2, i32 9, i32 3, i32 6, i32 1, i32 9, i32 8, i32 8>, <8 x i32> <i32 1, i32 6, i32 8, i32 5, i32 1, i32 2, i32 0, i32 0>, i32 8)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 0, i32 0, i32 4, i32 1, i32 0, i32 0, i32 0>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 1, i32 7, i32 9, i32 8, i32 8, i32 9, i32 4>, <8 x i32> <i32 2, i32 9, i32 3, i32 6, i32 1, i32 9, i32 8, i32 8>, <8 x i32> <i32 1, i32 6, i32 8, i32 5, i32 1, i32 2, i32 0, i32 0>, i32 8)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm9() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm9(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 8, i64 5, i64 9, i64 7, i64 3, i64 1, i64 2, i64 3>, <8 x i64> <i64 8, i64 0, i64 7, i64 5, i64 9, i64 1, i64 9, i64 7>, <8 x i64> <i64 6, i64 2, i64 2, i64 2, i64 6, i64 4, i64 7, i64 0>, i32 9)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -15, i64 -8, i64 -14, i64 -8, i64 -16, i64 -6, i64 -15, i64 -8>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 8, i64 5, i64 9, i64 7, i64 3, i64 1, i64 2, i64 3>, <8 x i64> <i64 8, i64 0, i64 7, i64 5, i64 9, i64 1, i64 9, i64 7>, <8 x i64> <i64 6, i64 2, i64 2, i64 2, i64 6, i64 4, i64 7, i64 0>, i32 9)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm10() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm10(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 5, i32 4, i32 4>, <4 x i32> <i32 1, i32 1, i32 2, i32 8>, <4 x i32> <i32 6, i32 2, i32 9, i32 4>, i32 10)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 6, i32 2, i32 9, i32 0>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 5, i32 4, i32 4>, <4 x i32> <i32 1, i32 1, i32 2, i32 8>, <4 x i32> <i32 6, i32 2, i32 9, i32 4>, i32 10)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm11() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm11(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 1, i64 0, i64 2>, <4 x i64> <i64 6, i64 9, i64 1, i64 1>, <4 x i64> <i64 1, i64 2, i64 8, i64 6>, i32 11)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -10, i64 -2, i64 -4>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 1, i64 0, i64 2>, <4 x i64> <i64 6, i64 9, i64 1, i64 1>, <4 x i64> <i64 1, i64 2, i64 8, i64 6>, i32 11)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm12() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm12(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 5, i32 4, i32 1, i32 3, i32 6, i32 9, i32 7, i32 5, i32 0, i32 3, i32 1, i32 8, i32 2, i32 8, i32 6>, <16 x i32> <i32 8, i32 0, i32 0, i32 8, i32 9, i32 2, i32 3, i32 3, i32 4, i32 2, i32 9, i32 2, i32 1, i32 9, i32 0, i32 6>, <16 x i32> <i32 1, i32 8, i32 4, i32 9, i32 1, i32 4, i32 1, i32 0, i32 9, i32 6, i32 9, i32 1, i32 0, i32 7, i32 4, i32 3>, i32 12)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 8, i32 0, i32 0, i32 8, i32 8, i32 0, i32 2, i32 0, i32 0, i32 2, i32 8, i32 2, i32 1, i32 9, i32 0, i32 0>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 5, i32 4, i32 1, i32 3, i32 6, i32 9, i32 7, i32 5, i32 0, i32 3, i32 1, i32 8, i32 2, i32 8, i32 6>, <16 x i32> <i32 8, i32 0, i32 0, i32 8, i32 9, i32 2, i32 3, i32 3, i32 4, i32 2, i32 9, i32 2, i32 1, i32 9, i32 0, i32 6>, <16 x i32> <i32 1, i32 8, i32 4, i32 9, i32 1, i32 4, i32 1, i32 0, i32 9, i32 6, i32 9, i32 1, i32 0, i32 7, i32 4, i32 3>, i32 12)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm13() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm13(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 6>, <2 x i64> <i64 1, i64 8>, <2 x i64> <i64 8, i64 7>, i32 13)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -10, i64 -8>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 6>, <2 x i64> <i64 1, i64 8>, <2 x i64> <i64 8, i64 7>, i32 13)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm14() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm14(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 6, i32 0, i32 5, i32 9, i32 1, i32 3, i32 1>, <8 x i32> <i32 4, i32 3, i32 9, i32 1, i32 3, i32 5, i32 2, i32 1>, <8 x i32> <i32 2, i32 2, i32 5, i32 3, i32 8, i32 6, i32 0, i32 8>, i32 14)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 1, i32 13, i32 2, i32 2, i32 6, i32 0, i32 8>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 6, i32 0, i32 5, i32 9, i32 1, i32 3, i32 1>, <8 x i32> <i32 4, i32 3, i32 9, i32 1, i32 3, i32 5, i32 2, i32 1>, <8 x i32> <i32 2, i32 2, i32 5, i32 3, i32 8, i32 6, i32 0, i32 8>, i32 14)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm15() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm15(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 9, i64 3, i64 9, i64 9, i64 4, i64 6, i64 3, i64 5>, <8 x i64> <i64 0, i64 5, i64 5, i64 3, i64 4, i64 2, i64 5, i64 5>, <8 x i64> <i64 7, i64 5, i64 2, i64 6, i64 5, i64 2, i64 4, i64 1>, i32 15)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -4, i64 -10, i64 -10, i64 -5, i64 -7, i64 -4, i64 -6>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 9, i64 3, i64 9, i64 9, i64 4, i64 6, i64 3, i64 5>, <8 x i64> <i64 0, i64 5, i64 5, i64 3, i64 4, i64 2, i64 5, i64 5>, <8 x i64> <i64 7, i64 5, i64 2, i64 6, i64 5, i64 2, i64 4, i64 1>, i32 15)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm16() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm16(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 8, i32 2, i32 7>, <4 x i32> <i32 5, i32 0, i32 0, i32 9>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>, i32 16)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 8, i32 0, i32 4>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 8, i32 2, i32 7>, <4 x i32> <i32 5, i32 0, i32 0, i32 9>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>, i32 16)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm17() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm17(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 5, i64 2, i64 3>, <4 x i64> <i64 8, i64 5, i64 9, i64 0>, <4 x i64> <i64 0, i64 8, i64 6, i64 4>, i32 17)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -9, i64 -14, i64 -16, i64 -5>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 5, i64 2, i64 3>, <4 x i64> <i64 8, i64 5, i64 9, i64 0>, <4 x i64> <i64 0, i64 8, i64 6, i64 4>, i32 17)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm18() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm18(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 5, i32 7, i32 0, i32 1, i32 4, i32 9, i32 3, i32 7, i32 2, i32 0, i32 4, i32 3, i32 3, i32 7, i32 5>, <16 x i32> <i32 2, i32 7, i32 7, i32 1, i32 2, i32 5, i32 5, i32 6, i32 6, i32 7, i32 2, i32 1, i32 3, i32 4, i32 4, i32 6>, <16 x i32> <i32 8, i32 8, i32 7, i32 6, i32 2, i32 7, i32 2, i32 6, i32 1, i32 8, i32 0, i32 9, i32 0, i32 0, i32 6, i32 6>, i32 18)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 9, i32 8, i32 0, i32 6, i32 1, i32 2, i32 10, i32 1, i32 0, i32 8, i32 0, i32 12, i32 0, i32 3, i32 1, i32 1>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 5, i32 7, i32 0, i32 1, i32 4, i32 9, i32 3, i32 7, i32 2, i32 0, i32 4, i32 3, i32 3, i32 7, i32 5>, <16 x i32> <i32 2, i32 7, i32 7, i32 1, i32 2, i32 5, i32 5, i32 6, i32 6, i32 7, i32 2, i32 1, i32 3, i32 4, i32 4, i32 6>, <16 x i32> <i32 8, i32 8, i32 7, i32 6, i32 2, i32 7, i32 2, i32 6, i32 1, i32 8, i32 0, i32 9, i32 0, i32 0, i32 6, i32 6>, i32 18)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm19() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm19(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 4>, <2 x i64> <i64 2, i64 0>, <2 x i64> <i64 6, i64 8>, i32 19)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -3, i64 -1>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 4>, <2 x i64> <i64 2, i64 0>, <2 x i64> <i64 6, i64 8>, i32 19)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm20() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm20(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 3, i32 5, i32 6, i32 1, i32 6, i32 8, i32 8>, <8 x i32> <i32 8, i32 2, i32 3, i32 4, i32 2, i32 1, i32 0, i32 8>, <8 x i32> <i32 5, i32 8, i32 1, i32 1, i32 2, i32 0, i32 7, i32 4>, i32 20)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 8, i32 1, i32 6, i32 2, i32 1, i32 7, i32 8, i32 0>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 3, i32 5, i32 6, i32 1, i32 6, i32 8, i32 8>, <8 x i32> <i32 8, i32 2, i32 3, i32 4, i32 2, i32 1, i32 0, i32 8>, <8 x i32> <i32 5, i32 8, i32 1, i32 1, i32 2, i32 0, i32 7, i32 4>, i32 20)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm21() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm21(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 4, i64 9, i64 3, i64 3, i64 7, i64 3, i64 3>, <8 x i64> <i64 0, i64 3, i64 2, i64 1, i64 6, i64 6, i64 9, i64 4>, <8 x i64> <i64 6, i64 2, i64 0, i64 5, i64 4, i64 8, i64 1, i64 1>, i32 21)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -7, i64 -3, i64 -1, i64 -6, i64 -7, i64 -15, i64 -2, i64 -2>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 4, i64 9, i64 3, i64 3, i64 7, i64 3, i64 3>, <8 x i64> <i64 0, i64 3, i64 2, i64 1, i64 6, i64 6, i64 9, i64 4>, <8 x i64> <i64 6, i64 2, i64 0, i64 5, i64 4, i64 8, i64 1, i64 1>, i32 21)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm22() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm22(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 9, i32 4, i32 2>, <4 x i32> <i32 8, i32 8, i32 6, i32 5>, <4 x i32> <i32 0, i32 1, i32 1, i32 9>, i32 22)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 11, i32 0, i32 3, i32 14>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 9, i32 4, i32 2>, <4 x i32> <i32 8, i32 8, i32 6, i32 5>, <4 x i32> <i32 0, i32 1, i32 1, i32 9>, i32 22)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm23() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm23(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 5, i64 6, i64 9>, <4 x i64> <i64 8, i64 8, i64 7, i64 3>, <4 x i64> <i64 6, i64 7, i64 0, i64 2>, i32 23)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -5, i64 -6, i64 -7, i64 -4>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 5, i64 6, i64 9>, <4 x i64> <i64 8, i64 8, i64 7, i64 3>, <4 x i64> <i64 6, i64 7, i64 0, i64 2>, i32 23)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm24() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm24(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 0, i32 9, i32 5, i32 6, i32 1, i32 4, i32 9, i32 5, i32 1, i32 0, i32 1, i32 5, i32 5, i32 9, i32 7>, <16 x i32> <i32 7, i32 6, i32 3, i32 6, i32 6, i32 9, i32 6, i32 6, i32 6, i32 6, i32 6, i32 7, i32 1, i32 1, i32 9, i32 7>, <16 x i32> <i32 5, i32 4, i32 4, i32 0, i32 6, i32 2, i32 6, i32 5, i32 1, i32 5, i32 1, i32 0, i32 4, i32 3, i32 5, i32 3>, i32 24)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 4, i32 8, i32 1, i32 0, i32 0, i32 2, i32 12, i32 0, i32 4, i32 0, i32 0, i32 0, i32 4, i32 0, i32 0>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 0, i32 9, i32 5, i32 6, i32 1, i32 4, i32 9, i32 5, i32 1, i32 0, i32 1, i32 5, i32 5, i32 9, i32 7>, <16 x i32> <i32 7, i32 6, i32 3, i32 6, i32 6, i32 9, i32 6, i32 6, i32 6, i32 6, i32 6, i32 7, i32 1, i32 1, i32 9, i32 7>, <16 x i32> <i32 5, i32 4, i32 4, i32 0, i32 6, i32 2, i32 6, i32 5, i32 1, i32 5, i32 1, i32 0, i32 4, i32 3, i32 5, i32 3>, i32 24)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm25() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm25(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 3>, <2 x i64> <i64 2, i64 5>, <2 x i64> <i64 4, i64 3>, i32 25)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -7, i64 -8>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 3>, <2 x i64> <i64 2, i64 5>, <2 x i64> <i64 4, i64 3>, i32 25)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm26() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm26(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 4, i32 2, i32 9, i32 7, i32 6, i32 3, i32 3>, <8 x i32> <i32 3, i32 7, i32 2, i32 3, i32 9, i32 3, i32 6, i32 9>, <8 x i32> <i32 4, i32 1, i32 3, i32 3, i32 9, i32 6, i32 5, i32 0>, i32 26)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 1, i32 1, i32 10, i32 14, i32 0, i32 4, i32 2>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 4, i32 2, i32 9, i32 7, i32 6, i32 3, i32 3>, <8 x i32> <i32 3, i32 7, i32 2, i32 3, i32 9, i32 3, i32 6, i32 9>, <8 x i32> <i32 4, i32 1, i32 3, i32 3, i32 9, i32 6, i32 5, i32 0>, i32 26)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm27() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm27(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 6, i64 8, i64 0, i64 1, i64 3, i64 9, i64 4>, <8 x i64> <i64 6, i64 6, i64 3, i64 7, i64 8, i64 1, i64 4, i64 2>, <8 x i64> <i64 6, i64 2, i64 8, i64 6, i64 0, i64 8, i64 9, i64 9>, i32 27)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -7, i64 -7, i64 -12, i64 -2, i64 -9, i64 -2, i64 -14, i64 -3>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 6, i64 8, i64 0, i64 1, i64 3, i64 9, i64 4>, <8 x i64> <i64 6, i64 6, i64 3, i64 7, i64 8, i64 1, i64 4, i64 2>, <8 x i64> <i64 6, i64 2, i64 8, i64 6, i64 0, i64 8, i64 9, i64 9>, i32 27)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm28() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm28(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 9, i32 7, i32 3>, <4 x i32> <i32 9, i32 6, i32 6, i32 0>, <4 x i32> <i32 0, i32 6, i32 8, i32 5>, i32 28)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 10, i32 15, i32 1, i32 2>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 9, i32 7, i32 3>, <4 x i32> <i32 9, i32 6, i32 6, i32 0>, <4 x i32> <i32 0, i32 6, i32 8, i32 5>, i32 28)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm29() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm29(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 2, i64 9, i64 3>, <4 x i64> <i64 1, i64 7, i64 8, i64 5>, <4 x i64> <i64 6, i64 1, i64 8, i64 7>, i32 29)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -3, i64 -9, i64 -4>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 2, i64 9, i64 3>, <4 x i64> <i64 1, i64 7, i64 8, i64 5>, <4 x i64> <i64 6, i64 1, i64 8, i64 7>, i32 29)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm30() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm30(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 7, i32 0, i32 1, i32 1, i32 4, i32 6, i32 5, i32 1, i32 8, i32 3, i32 4, i32 2, i32 1, i32 8, i32 3>, <16 x i32> <i32 3, i32 7, i32 8, i32 9, i32 6, i32 5, i32 4, i32 7, i32 6, i32 8, i32 9, i32 0, i32 7, i32 6, i32 0, i32 0>, <16 x i32> <i32 5, i32 4, i32 6, i32 2, i32 4, i32 6, i32 1, i32 1, i32 8, i32 8, i32 7, i32 3, i32 2, i32 3, i32 2, i32 9>, i32 30)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 15, i32 0, i32 14, i32 10, i32 7, i32 3, i32 3, i32 2, i32 15, i32 0, i32 12, i32 7, i32 5, i32 6, i32 10, i32 10>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 7, i32 0, i32 1, i32 1, i32 4, i32 6, i32 5, i32 1, i32 8, i32 3, i32 4, i32 2, i32 1, i32 8, i32 3>, <16 x i32> <i32 3, i32 7, i32 8, i32 9, i32 6, i32 5, i32 4, i32 7, i32 6, i32 8, i32 9, i32 0, i32 7, i32 6, i32 0, i32 0>, <16 x i32> <i32 5, i32 4, i32 6, i32 2, i32 4, i32 6, i32 1, i32 1, i32 8, i32 8, i32 7, i32 3, i32 2, i32 3, i32 2, i32 9>, i32 30)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm31() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm31(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 5>, <2 x i64> <i64 2, i64 1>, <2 x i64> <i64 7, i64 4>, i32 31)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -8, i64 -6>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 5>, <2 x i64> <i64 2, i64 1>, <2 x i64> <i64 7, i64 4>, i32 31)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm32() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm32(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 0, i32 0, i32 4, i32 5, i32 7, i32 8, i32 9>, <8 x i32> <i32 6, i32 6, i32 0, i32 0, i32 1, i32 9, i32 3, i32 4>, <8 x i32> <i32 5, i32 9, i32 4, i32 0, i32 6, i32 5, i32 9, i32 6>, i32 32)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 4, i32 4, i32 8, i32 0>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 0, i32 0, i32 4, i32 5, i32 7, i32 8, i32 9>, <8 x i32> <i32 6, i32 6, i32 0, i32 0, i32 1, i32 9, i32 3, i32 4>, <8 x i32> <i32 5, i32 9, i32 4, i32 0, i32 6, i32 5, i32 9, i32 6>, i32 32)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm33() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm33(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 4, i64 8, i64 4, i64 7, i64 1, i64 0, i64 4, i64 1>, <8 x i64> <i64 0, i64 6, i64 0, i64 2, i64 3, i64 4, i64 4, i64 2>, <8 x i64> <i64 6, i64 0, i64 9, i64 6, i64 4, i64 8, i64 0, i64 3>, i32 33)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -3, i64 -15, i64 -14, i64 -4, i64 -8, i64 -13, i64 -5, i64 -3>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 4, i64 8, i64 4, i64 7, i64 1, i64 0, i64 4, i64 1>, <8 x i64> <i64 0, i64 6, i64 0, i64 2, i64 3, i64 4, i64 4, i64 2>, <8 x i64> <i64 6, i64 0, i64 9, i64 6, i64 4, i64 8, i64 0, i64 3>, i32 33)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm34() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm34(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 5, i32 5, i32 8>, <4 x i32> <i32 7, i32 9, i32 7, i32 1>, <4 x i32> <i32 2, i32 1, i32 6, i32 5>, i32 34)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 0, i32 0, i32 4>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 5, i32 5, i32 8>, <4 x i32> <i32 7, i32 9, i32 7, i32 1>, <4 x i32> <i32 2, i32 1, i32 6, i32 5>, i32 34)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm35() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm35(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 1, i64 4, i64 3>, <4 x i64> <i64 6, i64 8, i64 9, i64 0>, <4 x i64> <i64 5, i64 0, i64 6, i64 7>, i32 35)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -10, i64 -10, i64 -1>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 1, i64 4, i64 3>, <4 x i64> <i64 6, i64 8, i64 9, i64 0>, <4 x i64> <i64 5, i64 0, i64 6, i64 7>, i32 35)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm36() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm36(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 5, i32 0, i32 2, i32 3, i32 9, i32 2, i32 0, i32 3, i32 6, i32 8, i32 4, i32 6, i32 8, i32 0, i32 6>, <16 x i32> <i32 8, i32 0, i32 9, i32 3, i32 6, i32 6, i32 8, i32 8, i32 0, i32 5, i32 8, i32 7, i32 6, i32 6, i32 1, i32 2>, <16 x i32> <i32 1, i32 1, i32 2, i32 7, i32 8, i32 7, i32 8, i32 2, i32 0, i32 5, i32 6, i32 3, i32 0, i32 1, i32 6, i32 2>, i32 36)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 9, i32 1, i32 9, i32 0, i32 4, i32 1, i32 0, i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i32 0>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 5, i32 0, i32 2, i32 3, i32 9, i32 2, i32 0, i32 3, i32 6, i32 8, i32 4, i32 6, i32 8, i32 0, i32 6>, <16 x i32> <i32 8, i32 0, i32 9, i32 3, i32 6, i32 6, i32 8, i32 8, i32 0, i32 5, i32 8, i32 7, i32 6, i32 6, i32 1, i32 2>, <16 x i32> <i32 1, i32 1, i32 2, i32 7, i32 8, i32 7, i32 8, i32 2, i32 0, i32 5, i32 6, i32 3, i32 0, i32 1, i32 6, i32 2>, i32 36)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm37() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm37(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 2>, <2 x i64> <i64 1, i64 5>, <2 x i64> <i64 4, i64 7>, i32 37)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -13, i64 -6>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 2>, <2 x i64> <i64 1, i64 5>, <2 x i64> <i64 4, i64 7>, i32 37)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm38() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm38(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 0, i32 9, i32 0, i32 6, i32 7, i32 7, i32 7, i32 8>, <8 x i32> <i32 2, i32 7, i32 9, i32 8, i32 4, i32 1, i32 9, i32 0>, <8 x i32> <i32 4, i32 7, i32 5, i32 5, i32 3, i32 4, i32 6, i32 5>, i32 38)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 0, i32 12, i32 13, i32 3, i32 4, i32 14, i32 5>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 0, i32 9, i32 0, i32 6, i32 7, i32 7, i32 7, i32 8>, <8 x i32> <i32 2, i32 7, i32 9, i32 8, i32 4, i32 1, i32 9, i32 0>, <8 x i32> <i32 4, i32 7, i32 5, i32 5, i32 3, i32 4, i32 6, i32 5>, i32 38)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm39() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm39(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 4, i64 5, i64 3, i64 6, i64 4, i64 1, i64 6>, <8 x i64> <i64 2, i64 6, i64 9, i64 6, i64 7, i64 2, i64 9, i64 3>, <8 x i64> <i64 1, i64 7, i64 6, i64 2, i64 3, i64 9, i64 7, i64 0>, i32 39)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -3, i64 -7, i64 -2, i64 -4, i64 -8, i64 -5, i64 -2, i64 -7>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 4, i64 5, i64 3, i64 6, i64 4, i64 1, i64 6>, <8 x i64> <i64 2, i64 6, i64 9, i64 6, i64 7, i64 2, i64 9, i64 3>, <8 x i64> <i64 1, i64 7, i64 6, i64 2, i64 3, i64 9, i64 7, i64 0>, i32 39)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm40() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm40(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 5, i32 3, i32 2, i32 7>, <4 x i32> <i32 5, i32 4, i32 2, i32 4>, <4 x i32> <i32 2, i32 4, i32 0, i32 2>, i32 40)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 4, i32 0, i32 2>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 5, i32 3, i32 2, i32 7>, <4 x i32> <i32 5, i32 4, i32 2, i32 4>, <4 x i32> <i32 2, i32 4, i32 0, i32 2>, i32 40)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm41() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm41(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 5, i64 5, i64 3>, <4 x i64> <i64 4, i64 3, i64 7, i64 5>, <4 x i64> <i64 6, i64 3, i64 6, i64 9>, i32 41)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -6, i64 -6, i64 -16>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 5, i64 5, i64 3>, <4 x i64> <i64 4, i64 3, i64 7, i64 5>, <4 x i64> <i64 6, i64 3, i64 6, i64 9>, i32 41)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm42() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm42(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 0, i32 2, i32 8, i32 9, i32 5, i32 0, i32 8, i32 6, i32 6, i32 0, i32 2, i32 9, i32 8, i32 7, i32 3, i32 8>, <16 x i32> <i32 7, i32 2, i32 2, i32 3, i32 8, i32 7, i32 5, i32 4, i32 6, i32 1, i32 5, i32 5, i32 3, i32 3, i32 6, i32 0>, <16 x i32> <i32 5, i32 5, i32 5, i32 6, i32 2, i32 7, i32 5, i32 5, i32 9, i32 2, i32 2, i32 8, i32 8, i32 7, i32 5, i32 6>, i32 42)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 5, i32 5, i32 5, i32 6, i32 2, i32 7, i32 5, i32 1, i32 9, i32 2, i32 2, i32 8, i32 8, i32 4, i32 5, i32 6>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 0, i32 2, i32 8, i32 9, i32 5, i32 0, i32 8, i32 6, i32 6, i32 0, i32 2, i32 9, i32 8, i32 7, i32 3, i32 8>, <16 x i32> <i32 7, i32 2, i32 2, i32 3, i32 8, i32 7, i32 5, i32 4, i32 6, i32 1, i32 5, i32 5, i32 3, i32 3, i32 6, i32 0>, <16 x i32> <i32 5, i32 5, i32 5, i32 6, i32 2, i32 7, i32 5, i32 5, i32 9, i32 2, i32 2, i32 8, i32 8, i32 7, i32 5, i32 6>, i32 42)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm43() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm43(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 3>, <2 x i64> <i64 8, i64 3>, <2 x i64> <i64 4, i64 9>, i32 43)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -12, i64 -4>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 3>, <2 x i64> <i64 8, i64 3>, <2 x i64> <i64 4, i64 9>, i32 43)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm44() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm44(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 0, i32 1, i32 7, i32 4, i32 5, i32 3, i32 8, i32 5>, <8 x i32> <i32 0, i32 5, i32 4, i32 1, i32 9, i32 6, i32 9, i32 6>, <8 x i32> <i32 3, i32 7, i32 1, i32 9, i32 3, i32 0, i32 9, i32 6>, i32 44)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 4, i32 1, i32 1, i32 8, i32 4, i32 1, i32 2>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 0, i32 1, i32 7, i32 4, i32 5, i32 3, i32 8, i32 5>, <8 x i32> <i32 0, i32 5, i32 4, i32 1, i32 9, i32 6, i32 9, i32 6>, <8 x i32> <i32 3, i32 7, i32 1, i32 9, i32 3, i32 0, i32 9, i32 6>, i32 44)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm45() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm45(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 5, i64 4, i64 9, i64 5, i64 4, i64 4, i64 3>, <8 x i64> <i64 9, i64 6, i64 3, i64 1, i64 9, i64 6, i64 0, i64 1>, <8 x i64> <i64 0, i64 5, i64 8, i64 2, i64 2, i64 2, i64 2, i64 3>, i32 45)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -7, i64 -5, i64 -13, i64 -12, i64 -8, i64 -5, i64 -7, i64 -2>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 5, i64 4, i64 9, i64 5, i64 4, i64 4, i64 3>, <8 x i64> <i64 9, i64 6, i64 3, i64 1, i64 9, i64 6, i64 0, i64 1>, <8 x i64> <i64 0, i64 5, i64 8, i64 2, i64 2, i64 2, i64 2, i64 3>, i32 45)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm46() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm46(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 2, i32 3, i32 9>, <4 x i32> <i32 1, i32 1, i32 7, i32 1>, <4 x i32> <i32 9, i32 7, i32 4, i32 6>, i32 46)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 9, i32 7, i32 4, i32 6>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 2, i32 3, i32 9>, <4 x i32> <i32 1, i32 1, i32 7, i32 1>, <4 x i32> <i32 9, i32 7, i32 4, i32 6>, i32 46)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm47() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm47(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 4, i64 4, i64 1>, <4 x i64> <i64 8, i64 0, i64 9, i64 0>, <4 x i64> <i64 3, i64 1, i64 4, i64 3>, i32 47)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -5, i64 -1, i64 -1>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 4, i64 4, i64 1>, <4 x i64> <i64 8, i64 0, i64 9, i64 0>, <4 x i64> <i64 3, i64 1, i64 4, i64 3>, i32 47)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm48() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm48(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 7, i32 9, i32 9, i32 7, i32 5, i32 9, i32 3, i32 3, i32 5, i32 3, i32 2, i32 5, i32 8, i32 9, i32 4>, <16 x i32> <i32 7, i32 7, i32 1, i32 3, i32 9, i32 5, i32 8, i32 8, i32 1, i32 4, i32 0, i32 1, i32 3, i32 2, i32 2, i32 6>, <16 x i32> <i32 5, i32 0, i32 7, i32 5, i32 5, i32 0, i32 3, i32 9, i32 6, i32 6, i32 9, i32 4, i32 6, i32 7, i32 6, i32 1>, i32 48)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 0, i32 8, i32 8, i32 6, i32 0, i32 1, i32 3, i32 2, i32 1, i32 3, i32 2, i32 4, i32 8, i32 9, i32 0>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 7, i32 9, i32 9, i32 7, i32 5, i32 9, i32 3, i32 3, i32 5, i32 3, i32 2, i32 5, i32 8, i32 9, i32 4>, <16 x i32> <i32 7, i32 7, i32 1, i32 3, i32 9, i32 5, i32 8, i32 8, i32 1, i32 4, i32 0, i32 1, i32 3, i32 2, i32 2, i32 6>, <16 x i32> <i32 5, i32 0, i32 7, i32 5, i32 5, i32 0, i32 3, i32 9, i32 6, i32 6, i32 9, i32 4, i32 6, i32 7, i32 6, i32 1>, i32 48)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm49() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm49(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 2>, <2 x i64> <i64 3, i64 4>, <2 x i64> <i64 8, i64 9>, i32 49)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -12, i64 -14>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 2>, <2 x i64> <i64 3, i64 4>, <2 x i64> <i64 8, i64 9>, i32 49)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm50() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm50(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 9, i32 3, i32 6, i32 4, i32 4, i32 1, i32 1>, <8 x i32> <i32 1, i32 0, i32 6, i32 2, i32 1, i32 9, i32 7, i32 5>, <8 x i32> <i32 4, i32 3, i32 4, i32 3, i32 1, i32 6, i32 7, i32 4>, i32 50)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 4, i32 11, i32 1, i32 5, i32 4, i32 6, i32 0, i32 0>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 9, i32 3, i32 6, i32 4, i32 4, i32 1, i32 1>, <8 x i32> <i32 1, i32 0, i32 6, i32 2, i32 1, i32 9, i32 7, i32 5>, <8 x i32> <i32 4, i32 3, i32 4, i32 3, i32 1, i32 6, i32 7, i32 4>, i32 50)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm51() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm51(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 0, i64 4, i64 1, i64 3, i64 3, i64 5, i64 0>, <8 x i64> <i64 1, i64 2, i64 3, i64 1, i64 5, i64 0, i64 1, i64 7>, <8 x i64> <i64 7, i64 6, i64 7, i64 8, i64 3, i64 7, i64 7, i64 8>, i32 51)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -2, i64 -3, i64 -4, i64 -2, i64 -6, i64 -1, i64 -2, i64 -8>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 0, i64 4, i64 1, i64 3, i64 3, i64 5, i64 0>, <8 x i64> <i64 1, i64 2, i64 3, i64 1, i64 5, i64 0, i64 1, i64 7>, <8 x i64> <i64 7, i64 6, i64 7, i64 8, i64 3, i64 7, i64 7, i64 8>, i32 51)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm52() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm52(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 1, i32 4, i32 7>, <4 x i32> <i32 3, i32 7, i32 2, i32 2>, <4 x i32> <i32 2, i32 7, i32 8, i32 1>, i32 52)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 9, i32 0, i32 6, i32 5>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 1, i32 4, i32 7>, <4 x i32> <i32 3, i32 7, i32 2, i32 2>, <4 x i32> <i32 2, i32 7, i32 8, i32 1>, i32 52)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm53() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm53(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 1, i64 3, i64 0, i64 9>, <4 x i64> <i64 7, i64 1, i64 2, i64 9>, <4 x i64> <i64 5, i64 8, i64 3, i64 5>, i32 53)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -6, i64 -10, i64 -4, i64 -14>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 1, i64 3, i64 0, i64 9>, <4 x i64> <i64 7, i64 1, i64 2, i64 9>, <4 x i64> <i64 5, i64 8, i64 3, i64 5>, i32 53)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm54() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm54(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 0, i32 5, i32 2, i32 3, i32 4, i32 4, i32 6, i32 7, i32 0, i32 9, i32 9, i32 0, i32 2, i32 1, i32 9>, <16 x i32> <i32 3, i32 6, i32 2, i32 3, i32 7, i32 6, i32 4, i32 3, i32 9, i32 9, i32 0, i32 7, i32 3, i32 3, i32 8, i32 8>, <16 x i32> <i32 4, i32 3, i32 1, i32 0, i32 8, i32 2, i32 8, i32 3, i32 8, i32 0, i32 4, i32 0, i32 1, i32 6, i32 6, i32 9>, i32 54)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 5, i32 7, i32 1, i32 12, i32 0, i32 8, i32 4, i32 6, i32 9, i32 13, i32 14, i32 2, i32 5, i32 15, i32 1>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 0, i32 5, i32 2, i32 3, i32 4, i32 4, i32 6, i32 7, i32 0, i32 9, i32 9, i32 0, i32 2, i32 1, i32 9>, <16 x i32> <i32 3, i32 6, i32 2, i32 3, i32 7, i32 6, i32 4, i32 3, i32 9, i32 9, i32 0, i32 7, i32 3, i32 3, i32 8, i32 8>, <16 x i32> <i32 4, i32 3, i32 1, i32 0, i32 8, i32 2, i32 8, i32 3, i32 8, i32 0, i32 4, i32 0, i32 1, i32 6, i32 6, i32 9>, i32 54)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm55() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm55(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 6, i64 0>, <2 x i64> <i64 4, i64 6>, <2 x i64> <i64 4, i64 2>, i32 55)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -5, i64 -3>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 6, i64 0>, <2 x i64> <i64 4, i64 6>, <2 x i64> <i64 4, i64 2>, i32 55)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm56() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm56(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 5, i32 1, i32 4, i32 1, i32 9, i32 0, i32 4>, <8 x i32> <i32 9, i32 0, i32 9, i32 5, i32 6, i32 0, i32 3, i32 5>, <8 x i32> <i32 7, i32 5, i32 4, i32 1, i32 7, i32 7, i32 5, i32 6>, i32 56)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 5, i32 0, i32 1, i32 7, i32 9, i32 1, i32 0>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 5, i32 1, i32 4, i32 1, i32 9, i32 0, i32 4>, <8 x i32> <i32 9, i32 0, i32 9, i32 5, i32 6, i32 0, i32 3, i32 5>, <8 x i32> <i32 7, i32 5, i32 4, i32 1, i32 7, i32 7, i32 5, i32 6>, i32 56)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm57() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm57(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 0, i64 6, i64 6, i64 8, i64 7, i64 9, i64 8>, <8 x i64> <i64 9, i64 4, i64 5, i64 9, i64 0, i64 6, i64 6, i64 0>, <8 x i64> <i64 0, i64 0, i64 4, i64 1, i64 3, i64 6, i64 2, i64 4>, i32 57)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -5, i64 -6, i64 -9, i64 -4, i64 -7, i64 -5, i64 -5>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 0, i64 6, i64 6, i64 8, i64 7, i64 9, i64 8>, <8 x i64> <i64 9, i64 4, i64 5, i64 9, i64 0, i64 6, i64 6, i64 0>, <8 x i64> <i64 0, i64 0, i64 4, i64 1, i64 3, i64 6, i64 2, i64 4>, i32 57)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm58() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm58(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 5, i32 7, i32 7>, <4 x i32> <i32 9, i32 6, i32 0, i32 1>, <4 x i32> <i32 2, i32 1, i32 9, i32 7>, i32 58)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 2, i32 1, i32 15, i32 6>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 5, i32 7, i32 7>, <4 x i32> <i32 9, i32 6, i32 0, i32 1>, <4 x i32> <i32 2, i32 1, i32 9, i32 7>, i32 58)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm59() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm59(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 2, i64 6, i64 6>, <4 x i64> <i64 8, i64 8, i64 7, i64 9>, <4 x i64> <i64 4, i64 5, i64 5, i64 6>, i32 59)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -9, i64 -9, i64 -7, i64 -10>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 2, i64 6, i64 6>, <4 x i64> <i64 8, i64 8, i64 7, i64 9>, <4 x i64> <i64 4, i64 5, i64 5, i64 6>, i32 59)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm60() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm60(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 7, i32 5, i32 7, i32 6, i32 5, i32 6, i32 7, i32 3, i32 9, i32 7, i32 6, i32 0, i32 3, i32 5, i32 8>, <16 x i32> <i32 5, i32 3, i32 8, i32 7, i32 8, i32 5, i32 4, i32 7, i32 7, i32 9, i32 6, i32 5, i32 2, i32 8, i32 7, i32 7>, <16 x i32> <i32 2, i32 1, i32 2, i32 1, i32 7, i32 3, i32 6, i32 3, i32 5, i32 1, i32 9, i32 4, i32 4, i32 1, i32 1, i32 8>, i32 60)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 4, i32 13, i32 0, i32 14, i32 0, i32 2, i32 0, i32 4, i32 0, i32 1, i32 3, i32 2, i32 11, i32 2, i32 15>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 7, i32 5, i32 7, i32 6, i32 5, i32 6, i32 7, i32 3, i32 9, i32 7, i32 6, i32 0, i32 3, i32 5, i32 8>, <16 x i32> <i32 5, i32 3, i32 8, i32 7, i32 8, i32 5, i32 4, i32 7, i32 7, i32 9, i32 6, i32 5, i32 2, i32 8, i32 7, i32 7>, <16 x i32> <i32 2, i32 1, i32 2, i32 1, i32 7, i32 3, i32 6, i32 3, i32 5, i32 1, i32 9, i32 4, i32 4, i32 1, i32 1, i32 8>, i32 60)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm61() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm61(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 9>, <2 x i64> <i64 1, i64 0>, <2 x i64> <i64 5, i64 4>, i32 61)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -5, i64 -5>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 9>, <2 x i64> <i64 1, i64 0>, <2 x i64> <i64 5, i64 4>, i32 61)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm62() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm62(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 6, i32 0, i32 8, i32 2, i32 1, i32 3, i32 6>, <8 x i32> <i32 3, i32 4, i32 8, i32 0, i32 6, i32 3, i32 7, i32 9>, <8 x i32> <i32 0, i32 9, i32 7, i32 5, i32 6, i32 8, i32 2, i32 0>, i32 62)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 2, i32 11, i32 15, i32 13, i32 4, i32 10, i32 4, i32 15>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 6, i32 0, i32 8, i32 2, i32 1, i32 3, i32 6>, <8 x i32> <i32 3, i32 4, i32 8, i32 0, i32 6, i32 3, i32 7, i32 9>, <8 x i32> <i32 0, i32 9, i32 7, i32 5, i32 6, i32 8, i32 2, i32 0>, i32 62)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm63() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm63(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 4, i64 6, i64 0, i64 9, i64 8, i64 3, i64 3>, <8 x i64> <i64 4, i64 0, i64 8, i64 5, i64 9, i64 4, i64 1, i64 7>, <8 x i64> <i64 2, i64 7, i64 4, i64 5, i64 5, i64 6, i64 6, i64 4>, i32 63)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -10, i64 -1, i64 -2, i64 -4>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 4, i64 6, i64 0, i64 9, i64 8, i64 3, i64 3>, <8 x i64> <i64 4, i64 0, i64 8, i64 5, i64 9, i64 4, i64 1, i64 7>, <8 x i64> <i64 2, i64 7, i64 4, i64 5, i64 5, i64 6, i64 6, i64 4>, i32 63)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm64() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm64(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 7, i32 3, i32 3, i32 4>, <4 x i32> <i32 6, i32 4, i32 7, i32 6>, <4 x i32> <i32 5, i32 5, i32 9, i32 4>, i32 64)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 2, i32 0, i32 2, i32 0>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 7, i32 3, i32 3, i32 4>, <4 x i32> <i32 6, i32 4, i32 7, i32 6>, <4 x i32> <i32 5, i32 5, i32 9, i32 4>, i32 64)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm65() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm65(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 7, i64 0, i64 4, i64 9>, <4 x i64> <i64 1, i64 9, i64 7, i64 2>, <4 x i64> <i64 8, i64 6, i64 1, i64 3>, i32 65)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -15, i64 -16, i64 -4, i64 -12>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 7, i64 0, i64 4, i64 9>, <4 x i64> <i64 1, i64 9, i64 7, i64 2>, <4 x i64> <i64 8, i64 6, i64 1, i64 3>, i32 65)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm66() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm66(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 8, i32 8, i32 0, i32 0, i32 8, i32 6, i32 6, i32 5, i32 4, i32 9, i32 6, i32 1, i32 3, i32 5, i32 3>, <16 x i32> <i32 4, i32 1, i32 8, i32 3, i32 8, i32 3, i32 2, i32 1, i32 4, i32 0, i32 8, i32 7, i32 1, i32 0, i32 6, i32 1>, <16 x i32> <i32 0, i32 8, i32 1, i32 5, i32 6, i32 8, i32 0, i32 9, i32 7, i32 1, i32 3, i32 7, i32 8, i32 2, i32 0, i32 4>, i32 66)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 0, i32 9, i32 4, i32 6, i32 0, i32 2, i32 8, i32 2, i32 1, i32 10, i32 0, i32 9, i32 0, i32 4, i32 5>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 8, i32 8, i32 0, i32 0, i32 8, i32 6, i32 6, i32 5, i32 4, i32 9, i32 6, i32 1, i32 3, i32 5, i32 3>, <16 x i32> <i32 4, i32 1, i32 8, i32 3, i32 8, i32 3, i32 2, i32 1, i32 4, i32 0, i32 8, i32 7, i32 1, i32 0, i32 6, i32 1>, <16 x i32> <i32 0, i32 8, i32 1, i32 5, i32 6, i32 8, i32 0, i32 9, i32 7, i32 1, i32 3, i32 7, i32 8, i32 2, i32 0, i32 4>, i32 66)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm67() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm67(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 5>, <2 x i64> <i64 5, i64 0>, <2 x i64> <i64 5, i64 1>, i32 67)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -8, i64 -6>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 5>, <2 x i64> <i64 5, i64 0>, <2 x i64> <i64 5, i64 1>, i32 67)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm68() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm68(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 1, i32 4, i32 1, i32 4, i32 6, i32 6, i32 2>, <8 x i32> <i32 2, i32 1, i32 1, i32 2, i32 1, i32 7, i32 9, i32 2>, <8 x i32> <i32 3, i32 5, i32 4, i32 3, i32 7, i32 3, i32 7, i32 5>, i32 68)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 0, i32 1, i32 0, i32 0, i32 4, i32 8, i32 2>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 1, i32 4, i32 1, i32 4, i32 6, i32 6, i32 2>, <8 x i32> <i32 2, i32 1, i32 1, i32 2, i32 1, i32 7, i32 9, i32 2>, <8 x i32> <i32 3, i32 5, i32 4, i32 3, i32 7, i32 3, i32 7, i32 5>, i32 68)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm69() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm69(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 0, i64 2, i64 7, i64 3, i64 8, i64 8, i64 4>, <8 x i64> <i64 0, i64 5, i64 6, i64 0, i64 2, i64 7, i64 7, i64 1>, <8 x i64> <i64 9, i64 0, i64 4, i64 2, i64 8, i64 9, i64 5, i64 9>, i32 69)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -1, i64 -5, i64 -8, i64 -10, i64 -10, i64 -14, i64 -14>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 0, i64 2, i64 7, i64 3, i64 8, i64 8, i64 4>, <8 x i64> <i64 0, i64 5, i64 6, i64 0, i64 2, i64 7, i64 7, i64 1>, <8 x i64> <i64 9, i64 0, i64 4, i64 2, i64 8, i64 9, i64 5, i64 9>, i32 69)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm70() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm70(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 2, i32 1, i32 9, i32 2>, <4 x i32> <i32 6, i32 2, i32 5, i32 3>, <4 x i32> <i32 2, i32 9, i32 1, i32 7>, i32 70)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 4, i32 10, i32 4, i32 4>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 2, i32 1, i32 9, i32 2>, <4 x i32> <i32 6, i32 2, i32 5, i32 3>, <4 x i32> <i32 2, i32 9, i32 1, i32 7>, i32 70)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm71() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm71(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 8, i64 6, i64 0>, <4 x i64> <i64 0, i64 4, i64 8, i64 8>, <4 x i64> <i64 1, i64 1, i64 1, i64 6>, i32 71)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -6, i64 -9, i64 -7, i64 -1>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 8, i64 6, i64 0>, <4 x i64> <i64 0, i64 4, i64 8, i64 8>, <4 x i64> <i64 1, i64 1, i64 1, i64 6>, i32 71)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm72() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm72(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 8, i32 8, i32 1, i32 1, i32 1, i32 1, i32 4, i32 1, i32 7, i32 8, i32 5, i32 8, i32 8, i32 1, i32 2>, <16 x i32> <i32 2, i32 4, i32 2, i32 8, i32 9, i32 6, i32 1, i32 8, i32 5, i32 6, i32 4, i32 2, i32 0, i32 8, i32 0, i32 0>, <16 x i32> <i32 3, i32 5, i32 4, i32 9, i32 1, i32 5, i32 1, i32 3, i32 4, i32 5, i32 5, i32 1, i32 7, i32 7, i32 1, i32 8>, i32 72)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 2, i32 4, i32 0, i32 8, i32 0, i32 4, i32 0, i32 0, i32 5, i32 2, i32 4, i32 0, i32 0, i32 8, i32 0, i32 0>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 8, i32 8, i32 1, i32 1, i32 1, i32 1, i32 4, i32 1, i32 7, i32 8, i32 5, i32 8, i32 8, i32 1, i32 2>, <16 x i32> <i32 2, i32 4, i32 2, i32 8, i32 9, i32 6, i32 1, i32 8, i32 5, i32 6, i32 4, i32 2, i32 0, i32 8, i32 0, i32 0>, <16 x i32> <i32 3, i32 5, i32 4, i32 9, i32 1, i32 5, i32 1, i32 3, i32 4, i32 5, i32 5, i32 1, i32 7, i32 7, i32 1, i32 8>, i32 72)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm73() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm73(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 2>, <2 x i64> <i64 3, i64 1>, <2 x i64> <i64 7, i64 7>, i32 73)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -8, i64 -7>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 2>, <2 x i64> <i64 3, i64 1>, <2 x i64> <i64 7, i64 7>, i32 73)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm74() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm74(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 4, i32 5, i32 3, i32 4, i32 0, i32 0, i32 5>, <8 x i32> <i32 2, i32 6, i32 5, i32 8, i32 4, i32 5, i32 0, i32 5>, <8 x i32> <i32 2, i32 7, i32 4, i32 4, i32 0, i32 8, i32 6, i32 3>, i32 74)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 2, i32 3, i32 1, i32 4, i32 4, i32 8, i32 6, i32 6>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 4, i32 5, i32 3, i32 4, i32 0, i32 0, i32 5>, <8 x i32> <i32 2, i32 6, i32 5, i32 8, i32 4, i32 5, i32 0, i32 5>, <8 x i32> <i32 2, i32 7, i32 4, i32 4, i32 0, i32 8, i32 6, i32 3>, i32 74)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm75() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm75(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 1, i64 1, i64 9, i64 6, i64 7, i64 3, i64 0>, <8 x i64> <i64 0, i64 6, i64 1, i64 1, i64 2, i64 6, i64 2, i64 4>, <8 x i64> <i64 1, i64 8, i64 4, i64 8, i64 2, i64 4, i64 7, i64 5>, i32 75)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -7, i64 -8, i64 -1, i64 -9, i64 -7, i64 -6, i64 -4, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 1, i64 1, i64 9, i64 6, i64 7, i64 3, i64 0>, <8 x i64> <i64 0, i64 6, i64 1, i64 1, i64 2, i64 6, i64 2, i64 4>, <8 x i64> <i64 1, i64 8, i64 4, i64 8, i64 2, i64 4, i64 7, i64 5>, i32 75)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm76() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm76(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 0, i32 0, i32 3>, <4 x i32> <i32 7, i32 1, i32 2, i32 2>, <4 x i32> <i32 6, i32 7, i32 8, i32 4>, i32 76)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 1, i32 1, i32 2, i32 2>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 0, i32 0, i32 3>, <4 x i32> <i32 7, i32 1, i32 2, i32 2>, <4 x i32> <i32 6, i32 7, i32 8, i32 4>, i32 76)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm77() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm77(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 4, i64 6, i64 5>, <4 x i64> <i64 5, i64 5, i64 7, i64 8>, <4 x i64> <i64 8, i64 2, i64 1, i64 1>, i32 77)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -9, i64 -3, i64 -1, i64 -6>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 4, i64 6, i64 5>, <4 x i64> <i64 5, i64 5, i64 7, i64 8>, <4 x i64> <i64 8, i64 2, i64 1, i64 1>, i32 77)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm78() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm78(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 3, i32 3, i32 5, i32 2, i32 6, i32 8, i32 2, i32 9, i32 5, i32 2, i32 1, i32 5, i32 7, i32 0, i32 3>, <16 x i32> <i32 0, i32 2, i32 4, i32 2, i32 2, i32 9, i32 8, i32 7, i32 8, i32 2, i32 7, i32 3, i32 4, i32 0, i32 5, i32 7>, <16 x i32> <i32 2, i32 0, i32 4, i32 3, i32 8, i32 2, i32 6, i32 9, i32 7, i32 4, i32 2, i32 7, i32 0, i32 8, i32 6, i32 4>, i32 78)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 2, i32 4, i32 2, i32 10, i32 9, i32 14, i32 15, i32 14, i32 2, i32 5, i32 6, i32 4, i32 8, i32 7, i32 7>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 3, i32 3, i32 5, i32 2, i32 6, i32 8, i32 2, i32 9, i32 5, i32 2, i32 1, i32 5, i32 7, i32 0, i32 3>, <16 x i32> <i32 0, i32 2, i32 4, i32 2, i32 2, i32 9, i32 8, i32 7, i32 8, i32 2, i32 7, i32 3, i32 4, i32 0, i32 5, i32 7>, <16 x i32> <i32 2, i32 0, i32 4, i32 3, i32 8, i32 2, i32 6, i32 9, i32 7, i32 4, i32 2, i32 7, i32 0, i32 8, i32 6, i32 4>, i32 78)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm79() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm79(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 8>, <2 x i64> <i64 6, i64 2>, <2 x i64> <i64 1, i64 2>, i32 79)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -2, i64 -9>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 8>, <2 x i64> <i64 6, i64 2>, <2 x i64> <i64 1, i64 2>, i32 79)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm80() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm80(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 9, i32 9, i32 3, i32 5, i32 9, i32 7, i32 1>, <8 x i32> <i32 3, i32 1, i32 8, i32 2, i32 1, i32 6, i32 0, i32 1>, <8 x i32> <i32 7, i32 7, i32 3, i32 5, i32 9, i32 7, i32 3, i32 7>, i32 80)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 8, i32 8, i32 2, i32 4, i32 8, i32 4, i32 0>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 9, i32 9, i32 3, i32 5, i32 9, i32 7, i32 1>, <8 x i32> <i32 3, i32 1, i32 8, i32 2, i32 1, i32 6, i32 0, i32 1>, <8 x i32> <i32 7, i32 7, i32 3, i32 5, i32 9, i32 7, i32 3, i32 7>, i32 80)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm81() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm81(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 0, i64 1, i64 6, i64 7, i64 8, i64 0, i64 2>, <8 x i64> <i64 5, i64 8, i64 6, i64 1, i64 1, i64 4, i64 2, i64 7>, <8 x i64> <i64 7, i64 4, i64 9, i64 6, i64 4, i64 3, i64 4, i64 6>, i32 81)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -8, i64 -13, i64 -16, i64 -8, i64 -5, i64 -8, i64 -7, i64 -8>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 0, i64 1, i64 6, i64 7, i64 8, i64 0, i64 2>, <8 x i64> <i64 5, i64 8, i64 6, i64 1, i64 1, i64 4, i64 2, i64 7>, <8 x i64> <i64 7, i64 4, i64 9, i64 6, i64 4, i64 3, i64 4, i64 6>, i32 81)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm82() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm82(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 1, i32 2, i32 7, i32 6>, <4 x i32> <i32 9, i32 4, i32 1, i32 4>, <4 x i32> <i32 2, i32 7, i32 4, i32 1>, i32 82)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 3, i32 1, i32 3, i32 7>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 1, i32 2, i32 7, i32 6>, <4 x i32> <i32 9, i32 4, i32 1, i32 4>, <4 x i32> <i32 2, i32 7, i32 4, i32 1>, i32 82)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm83() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm83(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 0, i64 0, i64 0, i64 4>, <4 x i64> <i64 4, i64 3, i64 3, i64 8>, <4 x i64> <i64 1, i64 6, i64 5, i64 6>, i32 83)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -5, i64 -4, i64 -4, i64 -13>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 0, i64 0, i64 0, i64 4>, <4 x i64> <i64 4, i64 3, i64 3, i64 8>, <4 x i64> <i64 1, i64 6, i64 5, i64 6>, i32 83)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm84() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm84(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 9, i32 0, i32 4, i32 1, i32 6, i32 4, i32 5, i32 7, i32 4, i32 4, i32 4, i32 9, i32 3, i32 0, i32 0>, <16 x i32> <i32 1, i32 1, i32 2, i32 4, i32 3, i32 8, i32 7, i32 3, i32 8, i32 5, i32 4, i32 7, i32 0, i32 9, i32 1, i32 3>, <16 x i32> <i32 5, i32 1, i32 0, i32 5, i32 3, i32 8, i32 4, i32 5, i32 5, i32 6, i32 3, i32 4, i32 5, i32 8, i32 2, i32 8>, i32 84)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 8, i32 2, i32 0, i32 0, i32 6, i32 3, i32 2, i32 10, i32 1, i32 4, i32 3, i32 8, i32 3, i32 1, i32 3>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 9, i32 0, i32 4, i32 1, i32 6, i32 4, i32 5, i32 7, i32 4, i32 4, i32 4, i32 9, i32 3, i32 0, i32 0>, <16 x i32> <i32 1, i32 1, i32 2, i32 4, i32 3, i32 8, i32 7, i32 3, i32 8, i32 5, i32 4, i32 7, i32 0, i32 9, i32 1, i32 3>, <16 x i32> <i32 5, i32 1, i32 0, i32 5, i32 3, i32 8, i32 4, i32 5, i32 5, i32 6, i32 3, i32 4, i32 5, i32 8, i32 2, i32 8>, i32 84)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm85() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm85(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 8>, <2 x i64> <i64 0, i64 9>, <2 x i64> <i64 9, i64 6>, i32 85)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -10, i64 -7>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 8>, <2 x i64> <i64 0, i64 9>, <2 x i64> <i64 9, i64 6>, i32 85)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm86() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm86(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 5, i32 8, i32 5, i32 6, i32 1, i32 6, i32 1>, <8 x i32> <i32 0, i32 3, i32 7, i32 5, i32 5, i32 5, i32 6, i32 6>, <8 x i32> <i32 9, i32 0, i32 2, i32 9, i32 0, i32 4, i32 0, i32 0>, i32 86)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 13, i32 7, i32 13, i32 12, i32 7, i32 1, i32 6, i32 7>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 5, i32 8, i32 5, i32 6, i32 1, i32 6, i32 1>, <8 x i32> <i32 0, i32 3, i32 7, i32 5, i32 5, i32 5, i32 6, i32 6>, <8 x i32> <i32 9, i32 0, i32 2, i32 9, i32 0, i32 4, i32 0, i32 0>, i32 86)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm87() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm87(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 3, i64 5, i64 6, i64 7, i64 8, i64 0, i64 7>, <8 x i64> <i64 0, i64 6, i64 0, i64 0, i64 1, i64 3, i64 4, i64 6>, <8 x i64> <i64 8, i64 9, i64 8, i64 7, i64 4, i64 5, i64 4, i64 4>, i32 87)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -2, i64 -1, i64 -7, i64 -5, i64 -2, i64 -5, i64 -5>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 3, i64 5, i64 6, i64 7, i64 8, i64 0, i64 7>, <8 x i64> <i64 0, i64 6, i64 0, i64 0, i64 1, i64 3, i64 4, i64 6>, <8 x i64> <i64 8, i64 9, i64 8, i64 7, i64 4, i64 5, i64 4, i64 4>, i32 87)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm88() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm88(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 2, i32 0, i32 8>, <4 x i32> <i32 0, i32 8, i32 3, i32 4>, <4 x i32> <i32 5, i32 5, i32 3, i32 5>, i32 88)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 8, i32 2, i32 3, i32 12>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 2, i32 0, i32 8>, <4 x i32> <i32 0, i32 8, i32 3, i32 4>, <4 x i32> <i32 5, i32 5, i32 3, i32 5>, i32 88)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm89() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm89(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 1, i64 4, i64 0, i64 0>, <4 x i64> <i64 5, i64 5, i64 2, i64 6>, <4 x i64> <i64 4, i64 3, i64 5, i64 5>, i32 89)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -3, i64 -8, i64 -4>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 1, i64 4, i64 0, i64 0>, <4 x i64> <i64 5, i64 5, i64 2, i64 6>, <4 x i64> <i64 4, i64 3, i64 5, i64 5>, i32 89)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm90() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm90(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 0, i32 8, i32 9, i32 2, i32 1, i32 2, i32 5, i32 6, i32 5, i32 3, i32 9, i32 4, i32 8, i32 5, i32 5>, <16 x i32> <i32 2, i32 9, i32 6, i32 8, i32 3, i32 3, i32 4, i32 0, i32 2, i32 7, i32 7, i32 2, i32 6, i32 8, i32 2, i32 8>, <16 x i32> <i32 2, i32 3, i32 5, i32 0, i32 9, i32 0, i32 1, i32 7, i32 9, i32 2, i32 2, i32 5, i32 9, i32 1, i32 9, i32 9>, i32 90)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 7, i32 3, i32 13, i32 9, i32 11, i32 1, i32 3, i32 2, i32 15, i32 7, i32 1, i32 12, i32 13, i32 9, i32 12, i32 12>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 0, i32 8, i32 9, i32 2, i32 1, i32 2, i32 5, i32 6, i32 5, i32 3, i32 9, i32 4, i32 8, i32 5, i32 5>, <16 x i32> <i32 2, i32 9, i32 6, i32 8, i32 3, i32 3, i32 4, i32 0, i32 2, i32 7, i32 7, i32 2, i32 6, i32 8, i32 2, i32 8>, <16 x i32> <i32 2, i32 3, i32 5, i32 0, i32 9, i32 0, i32 1, i32 7, i32 9, i32 2, i32 2, i32 5, i32 9, i32 1, i32 9, i32 9>, i32 90)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm91() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm91(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 5>, <2 x i64> <i64 0, i64 2>, <2 x i64> <i64 4, i64 2>, i32 91)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -1>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 5>, <2 x i64> <i64 0, i64 2>, <2 x i64> <i64 4, i64 2>, i32 91)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm92() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm92(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 8, i32 1, i32 8, i32 7, i32 4, i32 9, i32 9>, <8 x i32> <i32 5, i32 5, i32 4, i32 3, i32 6, i32 9, i32 5, i32 4>, <8 x i32> <i32 2, i32 1, i32 7, i32 3, i32 8, i32 7, i32 1, i32 9>, i32 92)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 5, i32 13, i32 4, i32 11, i32 7, i32 9, i32 12, i32 4>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 8, i32 1, i32 8, i32 7, i32 4, i32 9, i32 9>, <8 x i32> <i32 5, i32 5, i32 4, i32 3, i32 6, i32 9, i32 5, i32 4>, <8 x i32> <i32 2, i32 1, i32 7, i32 3, i32 8, i32 7, i32 1, i32 9>, i32 92)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm93() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm93(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 2, i64 4, i64 9, i64 9, i64 0, i64 9, i64 3>, <8 x i64> <i64 3, i64 5, i64 8, i64 9, i64 1, i64 5, i64 5, i64 6>, <8 x i64> <i64 7, i64 8, i64 7, i64 4, i64 5, i64 4, i64 4, i64 6>, i32 93)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -5, i64 -9, i64 -8, i64 -5, i64 -6, i64 -1, i64 -1, i64 -3>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 2, i64 4, i64 9, i64 9, i64 0, i64 9, i64 3>, <8 x i64> <i64 3, i64 5, i64 8, i64 9, i64 1, i64 5, i64 5, i64 6>, <8 x i64> <i64 7, i64 8, i64 7, i64 4, i64 5, i64 4, i64 4, i64 6>, i32 93)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm94() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm94(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 4, i32 4, i32 0>, <4 x i32> <i32 8, i32 9, i32 4, i32 5>, <4 x i32> <i32 1, i32 1, i32 8, i32 2>, i32 94)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 15, i32 13, i32 12, i32 7>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 4, i32 4, i32 0>, <4 x i32> <i32 8, i32 9, i32 4, i32 5>, <4 x i32> <i32 1, i32 1, i32 8, i32 2>, i32 94)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm95() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm95(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 5, i64 7, i64 4>, <4 x i64> <i64 5, i64 6, i64 1, i64 1>, <4 x i64> <i64 1, i64 8, i64 4, i64 8>, i32 95)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -1, i64 -5, i64 -1>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 5, i64 7, i64 4>, <4 x i64> <i64 5, i64 6, i64 1, i64 1>, <4 x i64> <i64 1, i64 8, i64 4, i64 8>, i32 95)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm96() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm96(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 6, i32 4, i32 6, i32 9, i32 0, i32 3, i32 8, i32 9, i32 5, i32 2, i32 0, i32 0, i32 2, i32 4, i32 9>, <16 x i32> <i32 5, i32 4, i32 5, i32 2, i32 9, i32 3, i32 2, i32 7, i32 6, i32 0, i32 2, i32 4, i32 8, i32 5, i32 5, i32 8>, <16 x i32> <i32 5, i32 0, i32 8, i32 8, i32 4, i32 5, i32 8, i32 2, i32 4, i32 4, i32 5, i32 5, i32 3, i32 1, i32 6, i32 5>, i32 96)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 4, i32 4, i32 2, i32 9, i32 0, i32 2, i32 0, i32 0, i32 4, i32 2, i32 0, i32 0, i32 0, i32 0, i32 9>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 6, i32 4, i32 6, i32 9, i32 0, i32 3, i32 8, i32 9, i32 5, i32 2, i32 0, i32 0, i32 2, i32 4, i32 9>, <16 x i32> <i32 5, i32 4, i32 5, i32 2, i32 9, i32 3, i32 2, i32 7, i32 6, i32 0, i32 2, i32 4, i32 8, i32 5, i32 5, i32 8>, <16 x i32> <i32 5, i32 0, i32 8, i32 8, i32 4, i32 5, i32 8, i32 2, i32 4, i32 4, i32 5, i32 5, i32 3, i32 1, i32 6, i32 5>, i32 96)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm97() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm97(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 3>, <2 x i64> <i64 8, i64 6>, <2 x i64> <i64 6, i64 8>, i32 97)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -14, i64 -14>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 3>, <2 x i64> <i64 8, i64 6>, <2 x i64> <i64 6, i64 8>, i32 97)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm98() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm98(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 4, i32 2, i32 9, i32 9, i32 6, i32 5, i32 0>, <8 x i32> <i32 1, i32 4, i32 5, i32 1, i32 8, i32 5, i32 4, i32 6>, <8 x i32> <i32 6, i32 0, i32 6, i32 9, i32 6, i32 2, i32 4, i32 8>, i32 98)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 7, i32 4, i32 2, i32 8, i32 14, i32 6, i32 0, i32 8>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 4, i32 2, i32 9, i32 9, i32 6, i32 5, i32 0>, <8 x i32> <i32 1, i32 4, i32 5, i32 1, i32 8, i32 5, i32 4, i32 6>, <8 x i32> <i32 6, i32 0, i32 6, i32 9, i32 6, i32 2, i32 4, i32 8>, i32 98)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm99() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm99(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 9, i64 5, i64 0, i64 8, i64 0, i64 2, i64 0>, <8 x i64> <i64 9, i64 6, i64 0, i64 2, i64 5, i64 3, i64 9, i64 1>, <8 x i64> <i64 3, i64 2, i64 1, i64 0, i64 9, i64 7, i64 7, i64 8>, i32 99)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -16, i64 -5, i64 -3, i64 -6, i64 -4, i64 -10, i64 -2>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 9, i64 5, i64 0, i64 8, i64 0, i64 2, i64 0>, <8 x i64> <i64 9, i64 6, i64 0, i64 2, i64 5, i64 3, i64 9, i64 1>, <8 x i64> <i64 3, i64 2, i64 1, i64 0, i64 9, i64 7, i64 7, i64 8>, i32 99)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm100() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm100(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 2, i32 3, i32 5>, <4 x i32> <i32 9, i32 2, i32 2, i32 7>, <4 x i32> <i32 4, i32 7, i32 1, i32 9>, i32 100)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 9, i32 0, i32 3, i32 6>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 2, i32 3, i32 5>, <4 x i32> <i32 9, i32 2, i32 2, i32 7>, <4 x i32> <i32 4, i32 7, i32 1, i32 9>, i32 100)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm101() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm101(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 6, i64 2, i64 6>, <4 x i64> <i64 4, i64 0, i64 4, i64 1>, <4 x i64> <i64 9, i64 5, i64 5, i64 1>, i32 101)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -12, i64 -4, i64 -8, i64 -8>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 6, i64 2, i64 6>, <4 x i64> <i64 4, i64 0, i64 4, i64 1>, <4 x i64> <i64 9, i64 5, i64 5, i64 1>, i32 101)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm102() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm102(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 6, i32 3, i32 9, i32 4, i32 9, i32 8, i32 8, i32 3, i32 3, i32 8, i32 3, i32 4, i32 9, i32 2, i32 6, i32 5>, <16 x i32> <i32 2, i32 7, i32 7, i32 0, i32 1, i32 4, i32 2, i32 7, i32 7, i32 1, i32 1, i32 6, i32 4, i32 0, i32 1, i32 3>, <16 x i32> <i32 4, i32 2, i32 6, i32 3, i32 5, i32 1, i32 9, i32 8, i32 5, i32 3, i32 7, i32 6, i32 1, i32 2, i32 6, i32 7>, i32 102)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 6, i32 5, i32 1, i32 3, i32 4, i32 5, i32 11, i32 15, i32 2, i32 2, i32 6, i32 0, i32 5, i32 2, i32 7, i32 4>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 6, i32 3, i32 9, i32 4, i32 9, i32 8, i32 8, i32 3, i32 3, i32 8, i32 3, i32 4, i32 9, i32 2, i32 6, i32 5>, <16 x i32> <i32 2, i32 7, i32 7, i32 0, i32 1, i32 4, i32 2, i32 7, i32 7, i32 1, i32 1, i32 6, i32 4, i32 0, i32 1, i32 3>, <16 x i32> <i32 4, i32 2, i32 6, i32 3, i32 5, i32 1, i32 9, i32 8, i32 5, i32 3, i32 7, i32 6, i32 1, i32 2, i32 6, i32 7>, i32 102)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm103() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm103(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 2>, <2 x i64> <i64 2, i64 2>, <2 x i64> <i64 5, i64 1>, i32 103)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -1>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 2>, <2 x i64> <i64 2, i64 2>, <2 x i64> <i64 5, i64 1>, i32 103)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm104() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm104(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 3, i32 6, i32 5, i32 8, i32 1, i32 5, i32 5>, <8 x i32> <i32 6, i32 7, i32 8, i32 8, i32 6, i32 9, i32 3, i32 7>, <8 x i32> <i32 8, i32 2, i32 4, i32 0, i32 2, i32 4, i32 9, i32 8>, i32 104)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 1, i32 4, i32 0, i32 2, i32 1, i32 0, i32 5>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 3, i32 6, i32 5, i32 8, i32 1, i32 5, i32 5>, <8 x i32> <i32 6, i32 7, i32 8, i32 8, i32 6, i32 9, i32 3, i32 7>, <8 x i32> <i32 8, i32 2, i32 4, i32 0, i32 2, i32 4, i32 9, i32 8>, i32 104)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm105() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm105(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 1, i64 5, i64 6, i64 1, i64 4, i64 1, i64 2>, <8 x i64> <i64 8, i64 7, i64 7, i64 5, i64 1, i64 2, i64 0, i64 5>, <8 x i64> <i64 7, i64 7, i64 8, i64 8, i64 2, i64 4, i64 4, i64 0>, i32 105)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -15, i64 -2, i64 -11, i64 -12, i64 -3, i64 -3, i64 -6, i64 -8>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 1, i64 5, i64 6, i64 1, i64 4, i64 1, i64 2>, <8 x i64> <i64 8, i64 7, i64 7, i64 5, i64 1, i64 2, i64 0, i64 5>, <8 x i64> <i64 7, i64 7, i64 8, i64 8, i64 2, i64 4, i64 4, i64 0>, i32 105)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm106() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm106(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 7, i32 9, i32 4>, <4 x i32> <i32 7, i32 1, i32 4, i32 6>, <4 x i32> <i32 4, i32 5, i32 3, i32 4>, i32 106)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 5, i32 4, i32 3, i32 0>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 7, i32 9, i32 4>, <4 x i32> <i32 7, i32 1, i32 4, i32 6>, <4 x i32> <i32 4, i32 5, i32 3, i32 4>, i32 106)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm107() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm107(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 4, i64 0, i64 1>, <4 x i64> <i64 9, i64 0, i64 4, i64 4>, <4 x i64> <i64 6, i64 1, i64 8, i64 8>, i32 107)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -10, i64 -5, i64 -5, i64 -6>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 4, i64 0, i64 1>, <4 x i64> <i64 9, i64 0, i64 4, i64 4>, <4 x i64> <i64 6, i64 1, i64 8, i64 8>, i32 107)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm108() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm108(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 7, i32 3, i32 0, i32 0, i32 6, i32 6, i32 2, i32 2, i32 5, i32 0, i32 2, i32 3, i32 4, i32 6, i32 5>, <16 x i32> <i32 9, i32 1, i32 9, i32 3, i32 8, i32 9, i32 5, i32 0, i32 5, i32 0, i32 8, i32 4, i32 9, i32 4, i32 7, i32 0>, <16 x i32> <i32 8, i32 2, i32 0, i32 4, i32 7, i32 6, i32 5, i32 2, i32 4, i32 5, i32 7, i32 8, i32 7, i32 9, i32 6, i32 8>, i32 108)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 9, i32 3, i32 9, i32 3, i32 8, i32 15, i32 1, i32 2, i32 5, i32 5, i32 8, i32 4, i32 10, i32 4, i32 1, i32 0>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 7, i32 3, i32 0, i32 0, i32 6, i32 6, i32 2, i32 2, i32 5, i32 0, i32 2, i32 3, i32 4, i32 6, i32 5>, <16 x i32> <i32 9, i32 1, i32 9, i32 3, i32 8, i32 9, i32 5, i32 0, i32 5, i32 0, i32 8, i32 4, i32 9, i32 4, i32 7, i32 0>, <16 x i32> <i32 8, i32 2, i32 0, i32 4, i32 7, i32 6, i32 5, i32 2, i32 4, i32 5, i32 7, i32 8, i32 7, i32 9, i32 6, i32 8>, i32 108)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm109() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm109(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 5, i64 7>, <2 x i64> <i64 8, i64 2>, <2 x i64> <i64 7, i64 2>, i32 109)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -3, i64 -8>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 5, i64 7>, <2 x i64> <i64 8, i64 2>, <2 x i64> <i64 7, i64 2>, i32 109)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm110() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm110(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 0, i32 9, i32 1, i32 4, i32 5, i32 8, i32 6>, <8 x i32> <i32 7, i32 1, i32 4, i32 1, i32 5, i32 1, i32 1, i32 7>, <8 x i32> <i32 0, i32 4, i32 7, i32 1, i32 3, i32 0, i32 2, i32 4>, i32 110)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 7, i32 5, i32 7, i32 0, i32 7, i32 1, i32 3, i32 3>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 0, i32 9, i32 1, i32 4, i32 5, i32 8, i32 6>, <8 x i32> <i32 7, i32 1, i32 4, i32 1, i32 5, i32 1, i32 1, i32 7>, <8 x i32> <i32 0, i32 4, i32 7, i32 1, i32 3, i32 0, i32 2, i32 4>, i32 110)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm111() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm111(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 8, i64 6, i64 9, i64 7, i64 9, i64 4, i64 2>, <8 x i64> <i64 6, i64 9, i64 5, i64 0, i64 1, i64 9, i64 8, i64 0>, <8 x i64> <i64 6, i64 1, i64 8, i64 3, i64 3, i64 2, i64 8, i64 6>, i32 111)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -4, i64 -1, i64 -3, i64 -9, i64 -6, i64 -1, i64 -5, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 8, i64 6, i64 9, i64 7, i64 9, i64 4, i64 2>, <8 x i64> <i64 6, i64 9, i64 5, i64 0, i64 1, i64 9, i64 8, i64 0>, <8 x i64> <i64 6, i64 1, i64 8, i64 3, i64 3, i64 2, i64 8, i64 6>, i32 111)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm112() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm112(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 8, i32 5, i32 1>, <4 x i32> <i32 7, i32 5, i32 6, i32 0>, <4 x i32> <i32 0, i32 4, i32 0, i32 0>, i32 112)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 8, i32 8, i32 5, i32 1>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 8, i32 5, i32 1>, <4 x i32> <i32 7, i32 5, i32 6, i32 0>, <4 x i32> <i32 0, i32 4, i32 0, i32 0>, i32 112)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm113() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm113(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 6, i64 1, i64 6>, <4 x i64> <i64 7, i64 2, i64 0, i64 7>, <4 x i64> <i64 6, i64 4, i64 6, i64 0>, i32 113)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -8, i64 -1, i64 -7, i64 -2>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 6, i64 1, i64 6>, <4 x i64> <i64 7, i64 2, i64 0, i64 7>, <4 x i64> <i64 6, i64 4, i64 6, i64 0>, i32 113)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm114() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm114(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 9, i32 3, i32 9, i32 8, i32 2, i32 9, i32 4, i32 7, i32 2, i32 2, i32 5, i32 7, i32 5, i32 3, i32 6>, <16 x i32> <i32 0, i32 1, i32 9, i32 7, i32 9, i32 2, i32 3, i32 7, i32 0, i32 1, i32 4, i32 4, i32 9, i32 2, i32 2, i32 3>, <16 x i32> <i32 2, i32 0, i32 0, i32 4, i32 7, i32 3, i32 2, i32 1, i32 7, i32 7, i32 7, i32 7, i32 3, i32 8, i32 9, i32 3>, i32 114)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 7, i32 9, i32 3, i32 9, i32 14, i32 1, i32 9, i32 4, i32 7, i32 6, i32 3, i32 3, i32 6, i32 13, i32 11, i32 4>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 9, i32 3, i32 9, i32 8, i32 2, i32 9, i32 4, i32 7, i32 2, i32 2, i32 5, i32 7, i32 5, i32 3, i32 6>, <16 x i32> <i32 0, i32 1, i32 9, i32 7, i32 9, i32 2, i32 3, i32 7, i32 0, i32 1, i32 4, i32 4, i32 9, i32 2, i32 2, i32 3>, <16 x i32> <i32 2, i32 0, i32 0, i32 4, i32 7, i32 3, i32 2, i32 1, i32 7, i32 7, i32 7, i32 7, i32 3, i32 8, i32 9, i32 3>, i32 114)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm115() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm115(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 0>, <2 x i64> <i64 4, i64 3>, <2 x i64> <i64 3, i64 7>, i32 115)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -5, i64 -4>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 0>, <2 x i64> <i64 4, i64 3>, <2 x i64> <i64 3, i64 7>, i32 115)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm116() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm116(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 9, i32 3, i32 2, i32 9, i32 0, i32 6, i32 5>, <8 x i32> <i32 1, i32 5, i32 8, i32 0, i32 6, i32 9, i32 8, i32 8>, <8 x i32> <i32 9, i32 8, i32 9, i32 1, i32 6, i32 0, i32 4, i32 7>, i32 116)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 2, i32 13, i32 3, i32 2, i32 9, i32 9, i32 14, i32 13>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 9, i32 3, i32 2, i32 9, i32 0, i32 6, i32 5>, <8 x i32> <i32 1, i32 5, i32 8, i32 0, i32 6, i32 9, i32 8, i32 8>, <8 x i32> <i32 9, i32 8, i32 9, i32 1, i32 6, i32 0, i32 4, i32 7>, i32 116)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm117() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm117(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 5, i64 9, i64 7, i64 2, i64 8, i64 7, i64 8>, <8 x i64> <i64 2, i64 1, i64 1, i64 2, i64 0, i64 5, i64 1, i64 9>, <8 x i64> <i64 7, i64 5, i64 2, i64 4, i64 9, i64 3, i64 8, i64 3>, i32 117)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -8, i64 -2, i64 -3, i64 -1, i64 -10, i64 -4, i64 -9, i64 -4>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 5, i64 9, i64 7, i64 2, i64 8, i64 7, i64 8>, <8 x i64> <i64 2, i64 1, i64 1, i64 2, i64 0, i64 5, i64 1, i64 9>, <8 x i64> <i64 7, i64 5, i64 2, i64 4, i64 9, i64 3, i64 8, i64 3>, i32 117)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm118() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm118(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 5, i32 3, i32 0, i32 4>, <4 x i32> <i32 5, i32 1, i32 7, i32 2>, <4 x i32> <i32 1, i32 7, i32 6, i32 8>, i32 118)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 4, i32 6, i32 1, i32 14>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 5, i32 3, i32 0, i32 4>, <4 x i32> <i32 5, i32 1, i32 7, i32 2>, <4 x i32> <i32 1, i32 7, i32 6, i32 8>, i32 118)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm119() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm119(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 5, i64 6, i64 3>, <4 x i64> <i64 9, i64 9, i64 3, i64 0>, <4 x i64> <i64 2, i64 0, i64 3, i64 5>, i32 119)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -1, i64 -4, i64 -1>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 5, i64 6, i64 3>, <4 x i64> <i64 9, i64 9, i64 3, i64 0>, <4 x i64> <i64 2, i64 0, i64 3, i64 5>, i32 119)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm120() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm120(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 1, i32 9, i32 8, i32 0, i32 4, i32 8, i32 5, i32 0, i32 2, i32 5, i32 7, i32 2, i32 2, i32 3, i32 1>, <16 x i32> <i32 2, i32 5, i32 7, i32 2, i32 5, i32 0, i32 3, i32 0, i32 5, i32 1, i32 4, i32 1, i32 7, i32 3, i32 6, i32 6>, <16 x i32> <i32 4, i32 8, i32 0, i32 2, i32 8, i32 1, i32 4, i32 7, i32 1, i32 3, i32 0, i32 9, i32 5, i32 1, i32 5, i32 2>, i32 120)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 1, i32 9, i32 10, i32 0, i32 4, i32 8, i32 5, i32 1, i32 3, i32 5, i32 6, i32 7, i32 3, i32 7, i32 3>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 1, i32 9, i32 8, i32 0, i32 4, i32 8, i32 5, i32 0, i32 2, i32 5, i32 7, i32 2, i32 2, i32 3, i32 1>, <16 x i32> <i32 2, i32 5, i32 7, i32 2, i32 5, i32 0, i32 3, i32 0, i32 5, i32 1, i32 4, i32 1, i32 7, i32 3, i32 6, i32 6>, <16 x i32> <i32 4, i32 8, i32 0, i32 2, i32 8, i32 1, i32 4, i32 7, i32 1, i32 3, i32 0, i32 9, i32 5, i32 1, i32 5, i32 2>, i32 120)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm121() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm121(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 6>, <2 x i64> <i64 1, i64 0>, <2 x i64> <i64 1, i64 4>, i32 121)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -2, i64 -1>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 6>, <2 x i64> <i64 1, i64 0>, <2 x i64> <i64 1, i64 4>, i32 121)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm122() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm122(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 7, i32 9, i32 1, i32 6, i32 9, i32 8, i32 7>, <8 x i32> <i32 0, i32 5, i32 1, i32 2, i32 5, i32 7, i32 7, i32 5>, <8 x i32> <i32 9, i32 8, i32 1, i32 7, i32 8, i32 0, i32 7, i32 9>, i32 122)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 9, i32 15, i32 8, i32 7, i32 14, i32 9, i32 15, i32 14>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 7, i32 9, i32 1, i32 6, i32 9, i32 8, i32 7>, <8 x i32> <i32 0, i32 5, i32 1, i32 2, i32 5, i32 7, i32 7, i32 5>, <8 x i32> <i32 9, i32 8, i32 1, i32 7, i32 8, i32 0, i32 7, i32 9>, i32 122)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm123() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm123(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 9, i64 5, i64 4, i64 4, i64 8, i64 2, i64 4, i64 0>, <8 x i64> <i64 8, i64 0, i64 1, i64 0, i64 0, i64 0, i64 9, i64 8>, <8 x i64> <i64 4, i64 0, i64 6, i64 2, i64 4, i64 2, i64 2, i64 0>, i32 123)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -1, i64 -2, i64 -1, i64 -1, i64 -1, i64 -10, i64 -9>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 9, i64 5, i64 4, i64 4, i64 8, i64 2, i64 4, i64 0>, <8 x i64> <i64 8, i64 0, i64 1, i64 0, i64 0, i64 0, i64 9, i64 8>, <8 x i64> <i64 4, i64 0, i64 6, i64 2, i64 4, i64 2, i64 2, i64 0>, i32 123)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm124() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm124(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 2, i32 4, i32 4>, <4 x i32> <i32 3, i32 1, i32 8, i32 6>, <4 x i32> <i32 5, i32 6, i32 1, i32 1>, i32 124)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 3, i32 12, i32 6>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 2, i32 4, i32 4>, <4 x i32> <i32 3, i32 1, i32 8, i32 6>, <4 x i32> <i32 5, i32 6, i32 1, i32 1>, i32 124)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm125() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm125(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 7, i64 0, i64 1, i64 3>, <4 x i64> <i64 5, i64 3, i64 1, i64 1>, <4 x i64> <i64 1, i64 0, i64 8, i64 3>, i32 125)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -2, i64 -1, i64 -9, i64 -2>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 7, i64 0, i64 1, i64 3>, <4 x i64> <i64 5, i64 3, i64 1, i64 1>, <4 x i64> <i64 1, i64 0, i64 8, i64 3>, i32 125)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm126() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm126(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 2, i32 5, i32 6, i32 8, i32 3, i32 7, i32 2, i32 0, i32 4, i32 7, i32 5, i32 5, i32 9, i32 5, i32 0>, <16 x i32> <i32 1, i32 6, i32 4, i32 9, i32 9, i32 0, i32 0, i32 1, i32 8, i32 1, i32 5, i32 5, i32 1, i32 6, i32 7, i32 1>, <16 x i32> <i32 7, i32 6, i32 3, i32 8, i32 1, i32 2, i32 8, i32 7, i32 6, i32 8, i32 7, i32 1, i32 8, i32 9, i32 6, i32 2>, i32 126)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 6, i32 4, i32 7, i32 15, i32 9, i32 3, i32 15, i32 7, i32 14, i32 13, i32 2, i32 4, i32 13, i32 15, i32 3, i32 3>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 2, i32 5, i32 6, i32 8, i32 3, i32 7, i32 2, i32 0, i32 4, i32 7, i32 5, i32 5, i32 9, i32 5, i32 0>, <16 x i32> <i32 1, i32 6, i32 4, i32 9, i32 9, i32 0, i32 0, i32 1, i32 8, i32 1, i32 5, i32 5, i32 1, i32 6, i32 7, i32 1>, <16 x i32> <i32 7, i32 6, i32 3, i32 8, i32 1, i32 2, i32 8, i32 7, i32 6, i32 8, i32 7, i32 1, i32 8, i32 9, i32 6, i32 2>, i32 126)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm127() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm127(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 0>, <2 x i64> <i64 1, i64 3>, <2 x i64> <i64 0, i64 7>, i32 127)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -1>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 0>, <2 x i64> <i64 1, i64 3>, <2 x i64> <i64 0, i64 7>, i32 127)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm128() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm128(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 0, i32 5, i32 2, i32 7, i32 1, i32 0, i32 6>, <8 x i32> <i32 6, i32 7, i32 2, i32 1, i32 7, i32 0, i32 3, i32 8>, <8 x i32> <i32 8, i32 6, i32 2, i32 2, i32 9, i32 3, i32 1, i32 2>, i32 128)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 0, i32 5, i32 2, i32 7, i32 1, i32 0, i32 6>, <8 x i32> <i32 6, i32 7, i32 2, i32 1, i32 7, i32 0, i32 3, i32 8>, <8 x i32> <i32 8, i32 6, i32 2, i32 2, i32 9, i32 3, i32 1, i32 2>, i32 128)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm129() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm129(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 0, i64 2, i64 2, i64 6, i64 2, i64 5, i64 2>, <8 x i64> <i64 5, i64 2, i64 2, i64 5, i64 3, i64 4, i64 4, i64 5>, <8 x i64> <i64 0, i64 2, i64 7, i64 9, i64 6, i64 0, i64 6, i64 4>, i32 129)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -8, i64 -3, i64 -6, i64 -16, i64 -6, i64 -7, i64 -4, i64 -8>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 0, i64 2, i64 2, i64 6, i64 2, i64 5, i64 2>, <8 x i64> <i64 5, i64 2, i64 2, i64 5, i64 3, i64 4, i64 4, i64 5>, <8 x i64> <i64 0, i64 2, i64 7, i64 9, i64 6, i64 0, i64 6, i64 4>, i32 129)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm130() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm130(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 6, i32 4, i32 6>, <4 x i32> <i32 3, i32 3, i32 9, i32 5>, <4 x i32> <i32 6, i32 7, i32 6, i32 1>, i32 130)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 4, i32 2, i32 2, i32 0>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 6, i32 4, i32 6>, <4 x i32> <i32 3, i32 3, i32 9, i32 5>, <4 x i32> <i32 6, i32 7, i32 6, i32 1>, i32 130)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm131() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm131(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 7, i64 5, i64 2>, <4 x i64> <i64 7, i64 1, i64 2, i64 4>, <4 x i64> <i64 2, i64 9, i64 9, i64 7>, i32 131)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -6, i64 -7, i64 -8, i64 -7>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 7, i64 5, i64 2>, <4 x i64> <i64 7, i64 1, i64 2, i64 4>, <4 x i64> <i64 2, i64 9, i64 9, i64 7>, i32 131)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm132() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm132(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 7, i32 3, i32 0, i32 5, i32 3, i32 9, i32 0, i32 0, i32 6, i32 6, i32 6, i32 1, i32 5, i32 6, i32 6>, <16 x i32> <i32 4, i32 4, i32 0, i32 0, i32 6, i32 6, i32 8, i32 6, i32 5, i32 2, i32 8, i32 7, i32 7, i32 3, i32 5, i32 8>, <16 x i32> <i32 4, i32 1, i32 0, i32 4, i32 5, i32 3, i32 6, i32 0, i32 4, i32 1, i32 9, i32 0, i32 8, i32 5, i32 2, i32 4>, i32 132)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 0, i32 0, i32 0, i32 6, i32 6, i32 0, i32 6, i32 1, i32 0, i32 0, i32 1, i32 6, i32 3, i32 1, i32 8>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 7, i32 3, i32 0, i32 5, i32 3, i32 9, i32 0, i32 0, i32 6, i32 6, i32 6, i32 1, i32 5, i32 6, i32 6>, <16 x i32> <i32 4, i32 4, i32 0, i32 0, i32 6, i32 6, i32 8, i32 6, i32 5, i32 2, i32 8, i32 7, i32 7, i32 3, i32 5, i32 8>, <16 x i32> <i32 4, i32 1, i32 0, i32 4, i32 5, i32 3, i32 6, i32 0, i32 4, i32 1, i32 9, i32 0, i32 8, i32 5, i32 2, i32 4>, i32 132)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm133() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm133(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 8>, <2 x i64> <i64 2, i64 8>, <2 x i64> <i64 5, i64 5>, i32 133)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -14, i64 -14>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 8>, <2 x i64> <i64 2, i64 8>, <2 x i64> <i64 5, i64 5>, i32 133)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm134() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm134(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 4, i32 7, i32 5, i32 2, i32 5, i32 4, i32 1>, <8 x i32> <i32 8, i32 0, i32 0, i32 2, i32 2, i32 7, i32 1, i32 6>, <8 x i32> <i32 5, i32 7, i32 9, i32 0, i32 0, i32 9, i32 9, i32 2>, i32 134)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 12, i32 3, i32 8, i32 2, i32 0, i32 11, i32 8, i32 4>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 4, i32 7, i32 5, i32 2, i32 5, i32 4, i32 1>, <8 x i32> <i32 8, i32 0, i32 0, i32 2, i32 2, i32 7, i32 1, i32 6>, <8 x i32> <i32 5, i32 7, i32 9, i32 0, i32 0, i32 9, i32 9, i32 2>, i32 134)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm135() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm135(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 4, i64 8, i64 6, i64 7, i64 5, i64 4, i64 4, i64 7>, <8 x i64> <i64 5, i64 2, i64 4, i64 4, i64 0, i64 0, i64 4, i64 3>, <8 x i64> <i64 3, i64 7, i64 6, i64 7, i64 0, i64 9, i64 0, i64 3>, i32 135)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -6, i64 -11, i64 -3, i64 -4, i64 -6, i64 -5, i64 -5, i64 -5>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 4, i64 8, i64 6, i64 7, i64 5, i64 4, i64 4, i64 7>, <8 x i64> <i64 5, i64 2, i64 4, i64 4, i64 0, i64 0, i64 4, i64 3>, <8 x i64> <i64 3, i64 7, i64 6, i64 7, i64 0, i64 9, i64 0, i64 3>, i32 135)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm136() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm136(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 2, i32 9, i32 2>, <4 x i32> <i32 2, i32 4, i32 1, i32 1>, <4 x i32> <i32 4, i32 6, i32 4, i32 6>, i32 136)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 4, i32 0, i32 0>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 2, i32 9, i32 2>, <4 x i32> <i32 2, i32 4, i32 1, i32 1>, <4 x i32> <i32 4, i32 6, i32 4, i32 6>, i32 136)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm137() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm137(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 1, i64 1, i64 4>, <4 x i64> <i64 8, i64 3, i64 0, i64 4>, <4 x i64> <i64 8, i64 3, i64 5, i64 5>, i32 137)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -3, i64 -1, i64 -6, i64 -2>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 1, i64 1, i64 4>, <4 x i64> <i64 8, i64 3, i64 0, i64 4>, <4 x i64> <i64 8, i64 3, i64 5, i64 5>, i32 137)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm138() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm138(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 8, i32 5, i32 5, i32 9, i32 5, i32 3, i32 0, i32 8, i32 9, i32 4, i32 9, i32 8, i32 5, i32 0, i32 3>, <16 x i32> <i32 0, i32 2, i32 0, i32 8, i32 7, i32 4, i32 5, i32 5, i32 8, i32 8, i32 6, i32 4, i32 0, i32 7, i32 1, i32 1>, <16 x i32> <i32 6, i32 2, i32 6, i32 2, i32 1, i32 2, i32 2, i32 4, i32 6, i32 8, i32 3, i32 2, i32 1, i32 7, i32 5, i32 7>, i32 138)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 1, i32 2, i32 0, i32 4, i32 6, i32 8, i32 3, i32 2, i32 1, i32 7, i32 5, i32 5>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 8, i32 5, i32 5, i32 9, i32 5, i32 3, i32 0, i32 8, i32 9, i32 4, i32 9, i32 8, i32 5, i32 0, i32 3>, <16 x i32> <i32 0, i32 2, i32 0, i32 8, i32 7, i32 4, i32 5, i32 5, i32 8, i32 8, i32 6, i32 4, i32 0, i32 7, i32 1, i32 1>, <16 x i32> <i32 6, i32 2, i32 6, i32 2, i32 1, i32 2, i32 2, i32 4, i32 6, i32 8, i32 3, i32 2, i32 1, i32 7, i32 5, i32 7>, i32 138)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm139() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm139(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 5, i64 4>, <2 x i64> <i64 1, i64 1>, <2 x i64> <i64 7, i64 6>, i32 139)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -5, i64 -6>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 5, i64 4>, <2 x i64> <i64 1, i64 1>, <2 x i64> <i64 7, i64 6>, i32 139)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm140() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm140(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 5, i32 7, i32 7, i32 2, i32 1, i32 1, i32 4>, <8 x i32> <i32 6, i32 7, i32 9, i32 4, i32 3, i32 5, i32 8, i32 6>, <8 x i32> <i32 7, i32 7, i32 8, i32 7, i32 4, i32 7, i32 2, i32 1>, i32 140)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 7, i32 8, i32 4, i32 1, i32 5, i32 8, i32 2>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 5, i32 7, i32 7, i32 2, i32 1, i32 1, i32 4>, <8 x i32> <i32 6, i32 7, i32 9, i32 4, i32 3, i32 5, i32 8, i32 6>, <8 x i32> <i32 7, i32 7, i32 8, i32 7, i32 4, i32 7, i32 2, i32 1>, i32 140)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm141() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm141(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 5, i64 7, i64 6, i64 4, i64 9, i64 5, i64 5>, <8 x i64> <i64 0, i64 5, i64 1, i64 2, i64 3, i64 3, i64 7, i64 1>, <8 x i64> <i64 4, i64 6, i64 9, i64 5, i64 5, i64 3, i64 5, i64 3>, i32 141)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -6, i64 -4, i64 -15, i64 -8, i64 -5, i64 -9, i64 -1, i64 -7>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 5, i64 7, i64 6, i64 4, i64 9, i64 5, i64 5>, <8 x i64> <i64 0, i64 5, i64 1, i64 2, i64 3, i64 3, i64 7, i64 1>, <8 x i64> <i64 4, i64 6, i64 9, i64 5, i64 5, i64 3, i64 5, i64 3>, i32 141)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm142() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm142(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 2, i32 1, i32 9, i32 7>, <4 x i32> <i32 7, i32 4, i32 5, i32 2>, <4 x i32> <i32 2, i32 5, i32 1, i32 0>, i32 142)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 4, i32 5, i32 0>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 2, i32 1, i32 9, i32 7>, <4 x i32> <i32 7, i32 4, i32 5, i32 2>, <4 x i32> <i32 2, i32 5, i32 1, i32 0>, i32 142)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm143() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm143(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 8, i64 8, i64 3>, <4 x i64> <i64 2, i64 5, i64 8, i64 0>, <4 x i64> <i64 2, i64 3, i64 0, i64 9>, i32 143)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -2, i64 -9, i64 -9, i64 -4>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 8, i64 8, i64 3>, <4 x i64> <i64 2, i64 5, i64 8, i64 0>, <4 x i64> <i64 2, i64 3, i64 0, i64 9>, i32 143)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm144() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm144(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 6, i32 9, i32 2, i32 2, i32 9, i32 5, i32 0, i32 7, i32 2, i32 0, i32 6, i32 7, i32 3, i32 3, i32 5, i32 6>, <16 x i32> <i32 8, i32 8, i32 1, i32 5, i32 3, i32 5, i32 9, i32 6, i32 8, i32 3, i32 6, i32 6, i32 7, i32 4, i32 9, i32 5>, <16 x i32> <i32 4, i32 7, i32 1, i32 5, i32 8, i32 8, i32 2, i32 7, i32 8, i32 0, i32 7, i32 9, i32 4, i32 0, i32 0, i32 2>, i32 144)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 2, i32 0, i32 2, i32 2, i32 0, i32 0, i32 0, i32 6, i32 2, i32 0, i32 6, i32 0, i32 0, i32 3, i32 4, i32 0>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 6, i32 9, i32 2, i32 2, i32 9, i32 5, i32 0, i32 7, i32 2, i32 0, i32 6, i32 7, i32 3, i32 3, i32 5, i32 6>, <16 x i32> <i32 8, i32 8, i32 1, i32 5, i32 3, i32 5, i32 9, i32 6, i32 8, i32 3, i32 6, i32 6, i32 7, i32 4, i32 9, i32 5>, <16 x i32> <i32 4, i32 7, i32 1, i32 5, i32 8, i32 8, i32 2, i32 7, i32 8, i32 0, i32 7, i32 9, i32 4, i32 0, i32 0, i32 2>, i32 144)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm145() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm145(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 2>, <2 x i64> <i64 9, i64 3>, <2 x i64> <i64 7, i64 0>, i32 145)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -15, i64 -4>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 2>, <2 x i64> <i64 9, i64 3>, <2 x i64> <i64 7, i64 0>, i32 145)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm146() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm146(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 8, i32 4, i32 3, i32 4, i32 9, i32 8, i32 3>, <8 x i32> <i32 8, i32 5, i32 5, i32 1, i32 2, i32 5, i32 5, i32 7>, <8 x i32> <i32 6, i32 6, i32 3, i32 1, i32 0, i32 0, i32 3, i32 4>, i32 146)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 2, i32 10, i32 2, i32 3, i32 4, i32 8, i32 10, i32 0>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 8, i32 4, i32 3, i32 4, i32 9, i32 8, i32 3>, <8 x i32> <i32 8, i32 5, i32 5, i32 1, i32 2, i32 5, i32 5, i32 7>, <8 x i32> <i32 6, i32 6, i32 3, i32 1, i32 0, i32 0, i32 3, i32 4>, i32 146)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm147() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm147(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 1, i64 2, i64 1, i64 8, i64 1, i64 4, i64 6>, <8 x i64> <i64 3, i64 1, i64 0, i64 6, i64 1, i64 5, i64 9, i64 0>, <8 x i64> <i64 6, i64 6, i64 7, i64 5, i64 8, i64 3, i64 0, i64 0>, i32 147)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -4, i64 -2, i64 -3, i64 -8, i64 -10, i64 -5, i64 -10, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 1, i64 2, i64 1, i64 8, i64 1, i64 4, i64 6>, <8 x i64> <i64 3, i64 1, i64 0, i64 6, i64 1, i64 5, i64 9, i64 0>, <8 x i64> <i64 6, i64 6, i64 7, i64 5, i64 8, i64 3, i64 0, i64 0>, i32 147)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm148() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm148(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 1, i32 3, i32 1, i32 7>, <4 x i32> <i32 2, i32 4, i32 9, i32 0>, <4 x i32> <i32 7, i32 0, i32 6, i32 2>, i32 148)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 7, i32 8, i32 5>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 1, i32 3, i32 1, i32 7>, <4 x i32> <i32 2, i32 4, i32 9, i32 0>, <4 x i32> <i32 7, i32 0, i32 6, i32 2>, i32 148)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm149() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm149(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 8, i64 6, i64 1>, <4 x i64> <i64 8, i64 8, i64 3, i64 9>, <4 x i64> <i64 0, i64 1, i64 2, i64 5>, i32 149)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -10, i64 -1, i64 -5>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 8, i64 6, i64 1>, <4 x i64> <i64 8, i64 8, i64 3, i64 9>, <4 x i64> <i64 0, i64 1, i64 2, i64 5>, i32 149)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm150() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm150(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 5, i32 7, i32 7, i32 0, i32 7, i32 0, i32 8, i32 6, i32 1, i32 6, i32 6, i32 7, i32 1, i32 0, i32 9>, <16 x i32> <i32 2, i32 8, i32 0, i32 8, i32 3, i32 0, i32 0, i32 0, i32 0, i32 6, i32 5, i32 6, i32 1, i32 9, i32 6, i32 0>, <16 x i32> <i32 2, i32 8, i32 5, i32 4, i32 1, i32 7, i32 8, i32 9, i32 4, i32 0, i32 3, i32 3, i32 3, i32 6, i32 0, i32 0>, i32 150)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 9, i32 5, i32 2, i32 11, i32 2, i32 0, i32 8, i32 1, i32 2, i32 7, i32 0, i32 3, i32 5, i32 14, i32 6, i32 9>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 5, i32 7, i32 7, i32 0, i32 7, i32 0, i32 8, i32 6, i32 1, i32 6, i32 6, i32 7, i32 1, i32 0, i32 9>, <16 x i32> <i32 2, i32 8, i32 0, i32 8, i32 3, i32 0, i32 0, i32 0, i32 0, i32 6, i32 5, i32 6, i32 1, i32 9, i32 6, i32 0>, <16 x i32> <i32 2, i32 8, i32 5, i32 4, i32 1, i32 7, i32 8, i32 9, i32 4, i32 0, i32 3, i32 3, i32 3, i32 6, i32 0, i32 0>, i32 150)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm151() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm151(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 0>, <2 x i64> <i64 3, i64 0>, <2 x i64> <i64 2, i64 2>, i32 151)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -3, i64 -1>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 0>, <2 x i64> <i64 3, i64 0>, <2 x i64> <i64 2, i64 2>, i32 151)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm152() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm152(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 7, i32 8, i32 6, i32 8, i32 4, i32 1, i32 8>, <8 x i32> <i32 5, i32 9, i32 5, i32 6, i32 3, i32 8, i32 7, i32 3>, <8 x i32> <i32 6, i32 5, i32 6, i32 2, i32 0, i32 0, i32 3, i32 9>, i32 152)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 4, i32 3, i32 12, i32 2, i32 8, i32 4, i32 3, i32 1>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 7, i32 8, i32 6, i32 8, i32 4, i32 1, i32 8>, <8 x i32> <i32 5, i32 9, i32 5, i32 6, i32 3, i32 8, i32 7, i32 3>, <8 x i32> <i32 6, i32 5, i32 6, i32 2, i32 0, i32 0, i32 3, i32 9>, i32 152)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm153() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm153(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 4, i64 8, i64 4, i64 0, i64 0, i64 1, i64 4>, <8 x i64> <i64 3, i64 3, i64 6, i64 5, i64 3, i64 9, i64 3, i64 2>, <8 x i64> <i64 2, i64 0, i64 7, i64 0, i64 8, i64 7, i64 6, i64 7>, i32 153)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -2, i64 -4, i64 -2, i64 -6, i64 -12, i64 -15, i64 -6, i64 -6>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 4, i64 8, i64 4, i64 0, i64 0, i64 1, i64 4>, <8 x i64> <i64 3, i64 3, i64 6, i64 5, i64 3, i64 9, i64 3, i64 2>, <8 x i64> <i64 2, i64 0, i64 7, i64 0, i64 8, i64 7, i64 6, i64 7>, i32 153)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm154() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm154(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 0, i32 2, i32 8>, <4 x i32> <i32 9, i32 6, i32 3, i32 9>, <4 x i32> <i32 0, i32 9, i32 3, i32 6>, i32 154)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 9, i32 3, i32 6>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 0, i32 2, i32 8>, <4 x i32> <i32 9, i32 6, i32 3, i32 9>, <4 x i32> <i32 0, i32 9, i32 3, i32 6>, i32 154)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm155() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm155(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 9, i64 1, i64 9>, <4 x i64> <i64 9, i64 5, i64 3, i64 6>, <4 x i64> <i64 1, i64 6, i64 8, i64 2>, i32 155)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -9, i64 -2, i64 -4, i64 -5>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 9, i64 1, i64 9>, <4 x i64> <i64 9, i64 5, i64 3, i64 6>, <4 x i64> <i64 1, i64 6, i64 8, i64 2>, i32 155)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm156() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm156(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 6, i32 1, i32 1, i32 0, i32 1, i32 4, i32 4, i32 9, i32 7, i32 7, i32 7, i32 8, i32 8, i32 1, i32 9>, <16 x i32> <i32 9, i32 7, i32 8, i32 8, i32 1, i32 5, i32 9, i32 3, i32 5, i32 7, i32 6, i32 7, i32 6, i32 9, i32 8, i32 0>, <16 x i32> <i32 3, i32 0, i32 1, i32 0, i32 3, i32 1, i32 7, i32 6, i32 6, i32 9, i32 8, i32 5, i32 4, i32 8, i32 7, i32 2>, i32 156)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 1, i32 1, i32 8, i32 9, i32 1, i32 5, i32 9, i32 3, i32 12, i32 1, i32 1, i32 5, i32 14, i32 9, i32 8, i32 9>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 6, i32 1, i32 1, i32 0, i32 1, i32 4, i32 4, i32 9, i32 7, i32 7, i32 7, i32 8, i32 8, i32 1, i32 9>, <16 x i32> <i32 9, i32 7, i32 8, i32 8, i32 1, i32 5, i32 9, i32 3, i32 5, i32 7, i32 6, i32 7, i32 6, i32 9, i32 8, i32 0>, <16 x i32> <i32 3, i32 0, i32 1, i32 0, i32 3, i32 1, i32 7, i32 6, i32 6, i32 9, i32 8, i32 5, i32 4, i32 8, i32 7, i32 2>, i32 156)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm157() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm157(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 1>, <2 x i64> <i64 3, i64 7>, <2 x i64> <i64 3, i64 3>, i32 157)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -1>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 1>, <2 x i64> <i64 3, i64 7>, <2 x i64> <i64 3, i64 3>, i32 157)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm158() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm158(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 5, i32 6, i32 3, i32 7, i32 7, i32 5, i32 2>, <8 x i32> <i32 3, i32 6, i32 4, i32 5, i32 8, i32 4, i32 3, i32 6>, <8 x i32> <i32 5, i32 1, i32 5, i32 7, i32 2, i32 9, i32 9, i32 6>, i32 158)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 1, i32 2, i32 7, i32 5, i32 13, i32 10, i32 15, i32 6>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 5, i32 6, i32 3, i32 7, i32 7, i32 5, i32 2>, <8 x i32> <i32 3, i32 6, i32 4, i32 5, i32 8, i32 4, i32 3, i32 6>, <8 x i32> <i32 5, i32 1, i32 5, i32 7, i32 2, i32 9, i32 9, i32 6>, i32 158)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm159() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm159(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 6, i64 7, i64 2, i64 7, i64 7, i64 7, i64 1>, <8 x i64> <i64 3, i64 7, i64 3, i64 4, i64 6, i64 1, i64 9, i64 8>, <8 x i64> <i64 3, i64 3, i64 9, i64 9, i64 9, i64 0, i64 6, i64 8>, i32 159)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -5, i64 -3, i64 -1, i64 -8, i64 -2, i64 -8, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 6, i64 7, i64 2, i64 7, i64 7, i64 7, i64 1>, <8 x i64> <i64 3, i64 7, i64 3, i64 4, i64 6, i64 1, i64 9, i64 8>, <8 x i64> <i64 3, i64 3, i64 9, i64 9, i64 9, i64 0, i64 6, i64 8>, i32 159)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm160() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm160(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 1, i32 0, i32 4>, <4 x i32> <i32 7, i32 0, i32 0, i32 1>, <4 x i32> <i32 7, i32 3, i32 1, i32 5>, i32 160)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 1, i32 0, i32 4>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 1, i32 0, i32 4>, <4 x i32> <i32 7, i32 0, i32 0, i32 1>, <4 x i32> <i32 7, i32 3, i32 1, i32 5>, i32 160)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm161() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm161(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 1, i64 4, i64 2, i64 3>, <4 x i64> <i64 0, i64 2, i64 1, i64 2>, <4 x i64> <i64 6, i64 7, i64 7, i64 6>, i32 161)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -8, i64 -4, i64 -6, i64 -6>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 1, i64 4, i64 2, i64 3>, <4 x i64> <i64 0, i64 2, i64 1, i64 2>, <4 x i64> <i64 6, i64 7, i64 7, i64 6>, i32 161)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm162() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm162(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 5, i32 0, i32 5, i32 8, i32 5, i32 3, i32 6, i32 6, i32 9, i32 8, i32 7, i32 1, i32 2, i32 8, i32 3>, <16 x i32> <i32 2, i32 5, i32 9, i32 1, i32 5, i32 7, i32 3, i32 5, i32 8, i32 3, i32 8, i32 1, i32 3, i32 5, i32 0, i32 8>, <16 x i32> <i32 8, i32 4, i32 7, i32 4, i32 5, i32 9, i32 2, i32 5, i32 9, i32 2, i32 9, i32 3, i32 4, i32 5, i32 7, i32 0>, i32 162)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 8, i32 4, i32 6, i32 4, i32 0, i32 9, i32 2, i32 4, i32 1, i32 0, i32 9, i32 3, i32 4, i32 0, i32 7, i32 0>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 5, i32 0, i32 5, i32 8, i32 5, i32 3, i32 6, i32 6, i32 9, i32 8, i32 7, i32 1, i32 2, i32 8, i32 3>, <16 x i32> <i32 2, i32 5, i32 9, i32 1, i32 5, i32 7, i32 3, i32 5, i32 8, i32 3, i32 8, i32 1, i32 3, i32 5, i32 0, i32 8>, <16 x i32> <i32 8, i32 4, i32 7, i32 4, i32 5, i32 9, i32 2, i32 5, i32 9, i32 2, i32 9, i32 3, i32 4, i32 5, i32 7, i32 0>, i32 162)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm163() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm163(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 3>, <2 x i64> <i64 7, i64 2>, <2 x i64> <i64 7, i64 5>, i32 163)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -6, i64 -3>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 3>, <2 x i64> <i64 7, i64 2>, <2 x i64> <i64 7, i64 5>, i32 163)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm164() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm164(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 1, i32 8, i32 9, i32 6, i32 4, i32 6, i32 2>, <8 x i32> <i32 2, i32 8, i32 0, i32 9, i32 1, i32 0, i32 6, i32 6>, <8 x i32> <i32 5, i32 9, i32 8, i32 2, i32 6, i32 0, i32 6, i32 6>, i32 164)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 5, i32 1, i32 8, i32 0, i32 7, i32 0, i32 6, i32 2>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 1, i32 8, i32 9, i32 6, i32 4, i32 6, i32 2>, <8 x i32> <i32 2, i32 8, i32 0, i32 9, i32 1, i32 0, i32 6, i32 6>, <8 x i32> <i32 5, i32 9, i32 8, i32 2, i32 6, i32 0, i32 6, i32 6>, i32 164)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm165() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm165(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 6, i64 4, i64 5, i64 0, i64 3, i64 5, i64 6>, <8 x i64> <i64 6, i64 7, i64 2, i64 8, i64 6, i64 2, i64 5, i64 8>, <8 x i64> <i64 6, i64 5, i64 1, i64 9, i64 6, i64 0, i64 1, i64 2>, i32 165)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -2, i64 -4, i64 -6, i64 -13, i64 -7, i64 -4, i64 -5, i64 -5>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 6, i64 4, i64 5, i64 0, i64 3, i64 5, i64 6>, <8 x i64> <i64 6, i64 7, i64 2, i64 8, i64 6, i64 2, i64 5, i64 8>, <8 x i64> <i64 6, i64 5, i64 1, i64 9, i64 6, i64 0, i64 1, i64 2>, i32 165)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm166() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm166(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 0, i32 4, i32 6>, <4 x i32> <i32 5, i32 0, i32 7, i32 7>, <4 x i32> <i32 6, i32 5, i32 1, i32 4>, i32 166)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 2, i32 5, i32 2, i32 5>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 0, i32 4, i32 6>, <4 x i32> <i32 5, i32 0, i32 7, i32 7>, <4 x i32> <i32 6, i32 5, i32 1, i32 4>, i32 166)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm167() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm167(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 1, i64 6, i64 2>, <4 x i64> <i64 0, i64 4, i64 0, i64 2>, <4 x i64> <i64 6, i64 6, i64 1, i64 1>, i32 167)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -2, i64 -6, i64 -7, i64 -3>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 1, i64 6, i64 2>, <4 x i64> <i64 0, i64 4, i64 0, i64 2>, <4 x i64> <i64 6, i64 6, i64 1, i64 1>, i32 167)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm168() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm168(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 8, i32 9, i32 5, i32 6, i32 0, i32 4, i32 6, i32 6, i32 3, i32 3, i32 5, i32 7, i32 4, i32 4, i32 7>, <16 x i32> <i32 9, i32 8, i32 0, i32 1, i32 6, i32 9, i32 4, i32 8, i32 4, i32 5, i32 0, i32 7, i32 3, i32 9, i32 2, i32 4>, <16 x i32> <i32 2, i32 4, i32 8, i32 3, i32 6, i32 0, i32 3, i32 6, i32 1, i32 9, i32 1, i32 8, i32 2, i32 1, i32 0, i32 5>, i32 168)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 0, i32 8, i32 1, i32 6, i32 0, i32 0, i32 6, i32 0, i32 1, i32 1, i32 0, i32 2, i32 1, i32 0, i32 5>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 8, i32 9, i32 5, i32 6, i32 0, i32 4, i32 6, i32 6, i32 3, i32 3, i32 5, i32 7, i32 4, i32 4, i32 7>, <16 x i32> <i32 9, i32 8, i32 0, i32 1, i32 6, i32 9, i32 4, i32 8, i32 4, i32 5, i32 0, i32 7, i32 3, i32 9, i32 2, i32 4>, <16 x i32> <i32 2, i32 4, i32 8, i32 3, i32 6, i32 0, i32 3, i32 6, i32 1, i32 9, i32 1, i32 8, i32 2, i32 1, i32 0, i32 5>, i32 168)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm169() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm169(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 7>, <2 x i64> <i64 5, i64 7>, <2 x i64> <i64 3, i64 7>, i32 169)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -5, i64 -1>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 7>, <2 x i64> <i64 5, i64 7>, <2 x i64> <i64 3, i64 7>, i32 169)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm170() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm170(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 5, i32 8, i32 4, i32 3, i32 2, i32 4, i32 0>, <8 x i32> <i32 9, i32 0, i32 2, i32 6, i32 5, i32 8, i32 5, i32 3>, <8 x i32> <i32 5, i32 4, i32 1, i32 5, i32 6, i32 6, i32 5, i32 2>, i32 170)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 5, i32 4, i32 1, i32 5, i32 6, i32 6, i32 5, i32 2>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 5, i32 8, i32 4, i32 3, i32 2, i32 4, i32 0>, <8 x i32> <i32 9, i32 0, i32 2, i32 6, i32 5, i32 8, i32 5, i32 3>, <8 x i32> <i32 5, i32 4, i32 1, i32 5, i32 6, i32 6, i32 5, i32 2>, i32 170)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm171() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm171(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 8, i64 5, i64 0, i64 6, i64 5, i64 6, i64 5>, <8 x i64> <i64 9, i64 4, i64 1, i64 0, i64 6, i64 5, i64 3, i64 9>, <8 x i64> <i64 9, i64 6, i64 5, i64 2, i64 4, i64 8, i64 6, i64 8>, i32 171)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -3, i64 -9, i64 -1, i64 -1, i64 -3, i64 -6, i64 -2, i64 -6>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 8, i64 5, i64 0, i64 6, i64 5, i64 6, i64 5>, <8 x i64> <i64 9, i64 4, i64 1, i64 0, i64 6, i64 5, i64 3, i64 9>, <8 x i64> <i64 9, i64 6, i64 5, i64 2, i64 4, i64 8, i64 6, i64 8>, i32 171)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm172() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm172(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 6, i32 3, i32 7>, <4 x i32> <i32 4, i32 4, i32 9, i32 8>, <4 x i32> <i32 3, i32 3, i32 3, i32 5>, i32 172)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 2, i32 11, i32 13>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 6, i32 3, i32 7>, <4 x i32> <i32 4, i32 4, i32 9, i32 8>, <4 x i32> <i32 3, i32 3, i32 3, i32 5>, i32 172)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm173() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm173(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 0, i64 1, i64 1, i64 3>, <4 x i64> <i64 5, i64 2, i64 0, i64 4>, <4 x i64> <i64 0, i64 8, i64 2, i64 9>, i32 173)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -10, i64 -4, i64 -11>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 0, i64 1, i64 1, i64 3>, <4 x i64> <i64 5, i64 2, i64 0, i64 4>, <4 x i64> <i64 0, i64 8, i64 2, i64 9>, i32 173)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm174() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm174(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 6, i32 9, i32 6, i32 5, i32 9, i32 4, i32 3, i32 6, i32 5, i32 3, i32 7, i32 8, i32 7, i32 7, i32 5>, <16 x i32> <i32 0, i32 5, i32 7, i32 6, i32 4, i32 4, i32 3, i32 7, i32 0, i32 2, i32 9, i32 1, i32 7, i32 5, i32 4, i32 8>, <16 x i32> <i32 3, i32 9, i32 6, i32 5, i32 6, i32 9, i32 9, i32 4, i32 9, i32 0, i32 9, i32 4, i32 5, i32 1, i32 3, i32 0>, i32 174)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 3, i32 9, i32 6, i32 5, i32 6, i32 13, i32 11, i32 4, i32 9, i32 2, i32 9, i32 4, i32 7, i32 1, i32 3, i32 8>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 6, i32 9, i32 6, i32 5, i32 9, i32 4, i32 3, i32 6, i32 5, i32 3, i32 7, i32 8, i32 7, i32 7, i32 5>, <16 x i32> <i32 0, i32 5, i32 7, i32 6, i32 4, i32 4, i32 3, i32 7, i32 0, i32 2, i32 9, i32 1, i32 7, i32 5, i32 4, i32 8>, <16 x i32> <i32 3, i32 9, i32 6, i32 5, i32 6, i32 9, i32 9, i32 4, i32 9, i32 0, i32 9, i32 4, i32 5, i32 1, i32 3, i32 0>, i32 174)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm175() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm175(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 6, i64 6>, <2 x i64> <i64 2, i64 1>, <2 x i64> <i64 8, i64 3>, i32 175)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -7, i64 -5>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 6, i64 6>, <2 x i64> <i64 2, i64 1>, <2 x i64> <i64 8, i64 3>, i32 175)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm176() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm176(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 0, i32 7, i32 3, i32 1, i32 4, i32 4, i32 3>, <8 x i32> <i32 6, i32 4, i32 1, i32 4, i32 8, i32 1, i32 8, i32 3>, <8 x i32> <i32 0, i32 1, i32 0, i32 7, i32 8, i32 5, i32 0, i32 1>, i32 176)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 0, i32 6, i32 3, i32 1, i32 4, i32 4, i32 1>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 0, i32 7, i32 3, i32 1, i32 4, i32 4, i32 3>, <8 x i32> <i32 6, i32 4, i32 1, i32 4, i32 8, i32 1, i32 8, i32 3>, <8 x i32> <i32 0, i32 1, i32 0, i32 7, i32 8, i32 5, i32 0, i32 1>, i32 176)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm177() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm177(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 5, i64 0, i64 7, i64 8, i64 4, i64 8, i64 7>, <8 x i64> <i64 1, i64 9, i64 9, i64 1, i64 4, i64 3, i64 5, i64 0>, <8 x i64> <i64 8, i64 7, i64 2, i64 2, i64 5, i64 2, i64 7, i64 9>, i32 177)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -11, i64 -12, i64 -2, i64 -6, i64 -4, i64 -8, i64 -9>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 5, i64 0, i64 7, i64 8, i64 4, i64 8, i64 7>, <8 x i64> <i64 1, i64 9, i64 9, i64 1, i64 4, i64 3, i64 5, i64 0>, <8 x i64> <i64 8, i64 7, i64 2, i64 2, i64 5, i64 2, i64 7, i64 9>, i32 177)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm178() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm178(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 7, i32 9, i32 2, i32 1>, <4 x i32> <i32 1, i32 1, i32 5, i32 3>, <4 x i32> <i32 9, i32 1, i32 5, i32 6>, i32 178)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 15, i32 9, i32 2, i32 4>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 7, i32 9, i32 2, i32 1>, <4 x i32> <i32 1, i32 1, i32 5, i32 3>, <4 x i32> <i32 9, i32 1, i32 5, i32 6>, i32 178)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm179() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm179(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 9, i64 9, i64 4>, <4 x i64> <i64 6, i64 8, i64 9, i64 1>, <4 x i64> <i64 1, i64 9, i64 5, i64 8>, i32 179)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -1, i64 -9, i64 -2>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 9, i64 9, i64 4>, <4 x i64> <i64 6, i64 8, i64 9, i64 1>, <4 x i64> <i64 1, i64 9, i64 5, i64 8>, i32 179)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm180() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm180(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 9, i32 7, i32 2, i32 6, i32 5, i32 2, i32 2, i32 5, i32 8, i32 4, i32 8, i32 8, i32 0, i32 7, i32 2>, <16 x i32> <i32 7, i32 9, i32 6, i32 8, i32 6, i32 0, i32 6, i32 5, i32 1, i32 0, i32 9, i32 1, i32 7, i32 8, i32 7, i32 1>, <16 x i32> <i32 8, i32 8, i32 7, i32 0, i32 0, i32 9, i32 6, i32 4, i32 4, i32 6, i32 7, i32 4, i32 6, i32 0, i32 6, i32 7>, i32 180)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 8, i32 7, i32 10, i32 0, i32 5, i32 2, i32 3, i32 4, i32 8, i32 12, i32 9, i32 9, i32 8, i32 6, i32 2>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 9, i32 7, i32 2, i32 6, i32 5, i32 2, i32 2, i32 5, i32 8, i32 4, i32 8, i32 8, i32 0, i32 7, i32 2>, <16 x i32> <i32 7, i32 9, i32 6, i32 8, i32 6, i32 0, i32 6, i32 5, i32 1, i32 0, i32 9, i32 1, i32 7, i32 8, i32 7, i32 1>, <16 x i32> <i32 8, i32 8, i32 7, i32 0, i32 0, i32 9, i32 6, i32 4, i32 4, i32 6, i32 7, i32 4, i32 6, i32 0, i32 6, i32 7>, i32 180)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm181() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm181(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 2>, <2 x i64> <i64 4, i64 3>, <2 x i64> <i64 1, i64 9>, i32 181)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -2, i64 -12>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 2>, <2 x i64> <i64 4, i64 3>, <2 x i64> <i64 1, i64 9>, i32 181)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm182() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm182(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 3, i32 8, i32 9, i32 0, i32 5, i32 5, i32 6>, <8 x i32> <i32 1, i32 2, i32 7, i32 3, i32 1, i32 1, i32 7, i32 8>, <8 x i32> <i32 8, i32 8, i32 3, i32 8, i32 4, i32 9, i32 4, i32 6>, i32 182)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 13, i32 9, i32 12, i32 10, i32 5, i32 13, i32 6, i32 14>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 3, i32 8, i32 9, i32 0, i32 5, i32 5, i32 6>, <8 x i32> <i32 1, i32 2, i32 7, i32 3, i32 1, i32 1, i32 7, i32 8>, <8 x i32> <i32 8, i32 8, i32 3, i32 8, i32 4, i32 9, i32 4, i32 6>, i32 182)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm183() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm183(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 2, i64 5, i64 2, i64 5, i64 8, i64 0, i64 7>, <8 x i64> <i64 9, i64 3, i64 3, i64 7, i64 3, i64 3, i64 1, i64 5>, <8 x i64> <i64 2, i64 1, i64 0, i64 9, i64 6, i64 0, i64 6, i64 9>, i32 183)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -2, i64 -4, i64 -2, i64 -4, i64 -4, i64 -1, i64 -1, i64 -5>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 2, i64 5, i64 2, i64 5, i64 8, i64 0, i64 7>, <8 x i64> <i64 9, i64 3, i64 3, i64 7, i64 3, i64 3, i64 1, i64 5>, <8 x i64> <i64 2, i64 1, i64 0, i64 9, i64 6, i64 0, i64 6, i64 9>, i32 183)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm184() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm184(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 2, i32 8, i32 2>, <4 x i32> <i32 6, i32 7, i32 8, i32 6>, <4 x i32> <i32 4, i32 5, i32 0, i32 1>, i32 184)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 5, i32 5, i32 0, i32 0>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 2, i32 8, i32 2>, <4 x i32> <i32 6, i32 7, i32 8, i32 6>, <4 x i32> <i32 4, i32 5, i32 0, i32 1>, i32 184)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm185() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm185(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 3, i64 7, i64 0>, <4 x i64> <i64 9, i64 1, i64 2, i64 1>, <4 x i64> <i64 7, i64 8, i64 6, i64 3>, i32 185)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -15, i64 -10, i64 -1, i64 -3>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 3, i64 7, i64 0>, <4 x i64> <i64 9, i64 1, i64 2, i64 1>, <4 x i64> <i64 7, i64 8, i64 6, i64 3>, i32 185)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm186() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm186(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 6, i32 7, i32 2, i32 8, i32 0, i32 6, i32 0, i32 3, i32 4, i32 3, i32 9, i32 7, i32 2, i32 5, i32 0>, <16 x i32> <i32 5, i32 0, i32 2, i32 3, i32 2, i32 7, i32 8, i32 6, i32 9, i32 7, i32 5, i32 0, i32 9, i32 4, i32 7, i32 7>, <16 x i32> <i32 8, i32 7, i32 0, i32 2, i32 9, i32 4, i32 4, i32 2, i32 3, i32 0, i32 1, i32 8, i32 1, i32 7, i32 5, i32 9>, i32 186)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 8, i32 7, i32 5, i32 2, i32 9, i32 4, i32 6, i32 2, i32 3, i32 0, i32 3, i32 9, i32 7, i32 7, i32 5, i32 9>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 6, i32 7, i32 2, i32 8, i32 0, i32 6, i32 0, i32 3, i32 4, i32 3, i32 9, i32 7, i32 2, i32 5, i32 0>, <16 x i32> <i32 5, i32 0, i32 2, i32 3, i32 2, i32 7, i32 8, i32 6, i32 9, i32 7, i32 5, i32 0, i32 9, i32 4, i32 7, i32 7>, <16 x i32> <i32 8, i32 7, i32 0, i32 2, i32 9, i32 4, i32 4, i32 2, i32 3, i32 0, i32 1, i32 8, i32 1, i32 7, i32 5, i32 9>, i32 186)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm187() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm187(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 0>, <2 x i64> <i64 1, i64 3>, <2 x i64> <i64 2, i64 4>, i32 187)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -2, i64 -4>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 0>, <2 x i64> <i64 1, i64 3>, <2 x i64> <i64 2, i64 4>, i32 187)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm188() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm188(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 2, i32 7, i32 1, i32 4, i32 3, i32 7, i32 9>, <8 x i32> <i32 7, i32 6, i32 4, i32 7, i32 5, i32 6, i32 1, i32 3>, <8 x i32> <i32 8, i32 2, i32 6, i32 5, i32 2, i32 8, i32 0, i32 9>, i32 188)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 6, i32 7, i32 7, i32 1, i32 5, i32 6, i32 11>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 2, i32 7, i32 1, i32 4, i32 3, i32 7, i32 9>, <8 x i32> <i32 7, i32 6, i32 4, i32 7, i32 5, i32 6, i32 1, i32 3>, <8 x i32> <i32 8, i32 2, i32 6, i32 5, i32 2, i32 8, i32 0, i32 9>, i32 188)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm189() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm189(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 4, i64 7, i64 6, i64 1, i64 8, i64 9, i64 0>, <8 x i64> <i64 7, i64 6, i64 9, i64 7, i64 5, i64 4, i64 5, i64 6>, <8 x i64> <i64 9, i64 7, i64 4, i64 7, i64 1, i64 6, i64 8, i64 1>, i32 189)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -9, i64 -2, i64 -2, i64 -1, i64 -1, i64 -3, i64 -2, i64 -2>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 4, i64 7, i64 6, i64 1, i64 8, i64 9, i64 0>, <8 x i64> <i64 7, i64 6, i64 9, i64 7, i64 5, i64 4, i64 5, i64 6>, <8 x i64> <i64 9, i64 7, i64 4, i64 7, i64 1, i64 6, i64 8, i64 1>, i32 189)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm190() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm190(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 4, i32 9, i32 9, i32 3>, <4 x i32> <i32 2, i32 1, i32 5, i32 4>, <4 x i32> <i32 5, i32 0, i32 5, i32 6>, i32 190)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 8, i32 13, i32 7>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 4, i32 9, i32 9, i32 3>, <4 x i32> <i32 2, i32 1, i32 5, i32 4>, <4 x i32> <i32 5, i32 0, i32 5, i32 6>, i32 190)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm191() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm191(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 0, i64 6, i64 0>, <4 x i64> <i64 9, i64 8, i64 4, i64 0>, <4 x i64> <i64 3, i64 9, i64 7, i64 2>, i32 191)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 0, i64 6, i64 0>, <4 x i64> <i64 9, i64 8, i64 4, i64 0>, <4 x i64> <i64 3, i64 9, i64 7, i64 2>, i32 191)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm192() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm192(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 2, i32 2, i32 0, i32 4, i32 7, i32 4, i32 8, i32 5, i32 1, i32 4, i32 2, i32 0, i32 9, i32 6, i32 8>, <16 x i32> <i32 9, i32 3, i32 3, i32 8, i32 7, i32 5, i32 1, i32 8, i32 9, i32 2, i32 4, i32 8, i32 0, i32 6, i32 4, i32 5>, <16 x i32> <i32 0, i32 1, i32 3, i32 8, i32 9, i32 8, i32 0, i32 3, i32 2, i32 1, i32 6, i32 9, i32 9, i32 6, i32 1, i32 5>, i32 192)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 1, i32 2, i32 2, i32 0, i32 4, i32 5, i32 0, i32 8, i32 1, i32 0, i32 4, i32 0, i32 0, i32 0, i32 4, i32 0>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 2, i32 2, i32 0, i32 4, i32 7, i32 4, i32 8, i32 5, i32 1, i32 4, i32 2, i32 0, i32 9, i32 6, i32 8>, <16 x i32> <i32 9, i32 3, i32 3, i32 8, i32 7, i32 5, i32 1, i32 8, i32 9, i32 2, i32 4, i32 8, i32 0, i32 6, i32 4, i32 5>, <16 x i32> <i32 0, i32 1, i32 3, i32 8, i32 9, i32 8, i32 0, i32 3, i32 2, i32 1, i32 6, i32 9, i32 9, i32 6, i32 1, i32 5>, i32 192)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm193() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm193(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 4>, <2 x i64> <i64 5, i64 1>, <2 x i64> <i64 6, i64 1>, i32 193)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -15, i64 -6>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 4>, <2 x i64> <i64 5, i64 1>, <2 x i64> <i64 6, i64 1>, i32 193)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm194() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm194(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 6, i32 7, i32 8, i32 4, i32 3, i32 3, i32 5>, <8 x i32> <i32 2, i32 5, i32 5, i32 1, i32 5, i32 4, i32 4, i32 9>, <8 x i32> <i32 4, i32 4, i32 5, i32 1, i32 3, i32 8, i32 0, i32 1>, i32 194)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 4, i32 4, i32 5, i32 0, i32 6, i32 8, i32 0, i32 1>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 6, i32 7, i32 8, i32 4, i32 3, i32 3, i32 5>, <8 x i32> <i32 2, i32 5, i32 5, i32 1, i32 5, i32 4, i32 4, i32 9>, <8 x i32> <i32 4, i32 4, i32 5, i32 1, i32 3, i32 8, i32 0, i32 1>, i32 194)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm195() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm195(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 5, i64 1, i64 5, i64 4, i64 4, i64 2, i64 5>, <8 x i64> <i64 5, i64 1, i64 1, i64 1, i64 4, i64 0, i64 0, i64 5>, <8 x i64> <i64 1, i64 4, i64 0, i64 5, i64 5, i64 3, i64 1, i64 5>, i32 195)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -4, i64 -5, i64 -1, i64 -5, i64 -1, i64 -5, i64 -3, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 5, i64 1, i64 5, i64 4, i64 4, i64 2, i64 5>, <8 x i64> <i64 5, i64 1, i64 1, i64 1, i64 4, i64 0, i64 0, i64 5>, <8 x i64> <i64 1, i64 4, i64 0, i64 5, i64 5, i64 3, i64 1, i64 5>, i32 195)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm196() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm196(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 6, i32 6, i32 6>, <4 x i32> <i32 1, i32 3, i32 9, i32 5>, <4 x i32> <i32 5, i32 4, i32 1, i32 5>, i32 196)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 1, i32 3, i32 8, i32 4>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 6, i32 6, i32 6>, <4 x i32> <i32 1, i32 3, i32 9, i32 5>, <4 x i32> <i32 5, i32 4, i32 1, i32 5>, i32 196)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm197() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm197(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 2, i64 8, i64 9>, <4 x i64> <i64 8, i64 7, i64 7, i64 8>, <4 x i64> <i64 7, i64 1, i64 1, i64 7>, i32 197)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -8, i64 -2, i64 -10, i64 -8>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 2, i64 8, i64 9>, <4 x i64> <i64 8, i64 7, i64 7, i64 8>, <4 x i64> <i64 7, i64 1, i64 1, i64 7>, i32 197)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm198() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm198(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 2, i32 6, i32 7, i32 1, i32 3, i32 5, i32 0, i32 0, i32 7, i32 3, i32 5, i32 7, i32 7, i32 8, i32 9>, <16 x i32> <i32 5, i32 9, i32 6, i32 0, i32 5, i32 8, i32 8, i32 2, i32 7, i32 6, i32 7, i32 4, i32 7, i32 1, i32 5, i32 1>, <16 x i32> <i32 3, i32 5, i32 3, i32 1, i32 6, i32 2, i32 4, i32 4, i32 3, i32 0, i32 0, i32 3, i32 5, i32 1, i32 5, i32 9>, i32 198)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 7, i32 12, i32 7, i32 0, i32 3, i32 8, i32 8, i32 6, i32 4, i32 6, i32 7, i32 6, i32 7, i32 1, i32 0, i32 1>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 2, i32 6, i32 7, i32 1, i32 3, i32 5, i32 0, i32 0, i32 7, i32 3, i32 5, i32 7, i32 7, i32 8, i32 9>, <16 x i32> <i32 5, i32 9, i32 6, i32 0, i32 5, i32 8, i32 8, i32 2, i32 7, i32 6, i32 7, i32 4, i32 7, i32 1, i32 5, i32 1>, <16 x i32> <i32 3, i32 5, i32 3, i32 1, i32 6, i32 2, i32 4, i32 4, i32 3, i32 0, i32 0, i32 3, i32 5, i32 1, i32 5, i32 9>, i32 198)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm199() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm199(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 6>, <2 x i64> <i64 2, i64 3>, <2 x i64> <i64 4, i64 0>, i32 199)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -9, i64 -5>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 6>, <2 x i64> <i64 2, i64 3>, <2 x i64> <i64 4, i64 0>, i32 199)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm200() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm200(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 7, i32 4, i32 2, i32 8, i32 7, i32 1, i32 3>, <8 x i32> <i32 3, i32 5, i32 1, i32 5, i32 5, i32 5, i32 1, i32 9>, <8 x i32> <i32 8, i32 8, i32 4, i32 3, i32 9, i32 9, i32 9, i32 9>, i32 200)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 5, i32 0, i32 1, i32 1, i32 5, i32 1, i32 9>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 7, i32 4, i32 2, i32 8, i32 7, i32 1, i32 3>, <8 x i32> <i32 3, i32 5, i32 1, i32 5, i32 5, i32 5, i32 1, i32 9>, <8 x i32> <i32 8, i32 8, i32 4, i32 3, i32 9, i32 9, i32 9, i32 9>, i32 200)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm201() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm201(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 2, i64 8, i64 1, i64 9, i64 0, i64 2, i64 3>, <8 x i64> <i64 5, i64 0, i64 5, i64 7, i64 8, i64 8, i64 8, i64 4>, <8 x i64> <i64 0, i64 7, i64 1, i64 6, i64 1, i64 8, i64 6, i64 4>, i32 201)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -5, i64 -8, i64 -13, i64 -1, i64 -2, i64 -1, i64 -15, i64 -4>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 2, i64 8, i64 1, i64 9, i64 0, i64 2, i64 3>, <8 x i64> <i64 5, i64 0, i64 5, i64 7, i64 8, i64 8, i64 8, i64 4>, <8 x i64> <i64 0, i64 7, i64 1, i64 6, i64 1, i64 8, i64 6, i64 4>, i32 201)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm202() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm202(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 1, i32 8, i32 6, i32 2>, <4 x i32> <i32 7, i32 8, i32 8, i32 3>, <4 x i32> <i32 0, i32 8, i32 8, i32 2>, i32 202)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 1, i32 8, i32 8, i32 2>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 1, i32 8, i32 6, i32 2>, <4 x i32> <i32 7, i32 8, i32 8, i32 3>, <4 x i32> <i32 0, i32 8, i32 8, i32 2>, i32 202)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm203() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm203(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 0, i64 6, i64 6, i64 6>, <4 x i64> <i64 3, i64 9, i64 4, i64 9>, <4 x i64> <i64 6, i64 8, i64 0, i64 7>, i32 203)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -2, i64 -8, i64 -3, i64 -15>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 0, i64 6, i64 6, i64 6>, <4 x i64> <i64 3, i64 9, i64 4, i64 9>, <4 x i64> <i64 6, i64 8, i64 0, i64 7>, i32 203)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm204() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm204(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 0, i32 3, i32 7, i32 8, i32 9, i32 0, i32 5, i32 0, i32 5, i32 4, i32 8, i32 6, i32 3, i32 4, i32 5>, <16 x i32> <i32 9, i32 7, i32 8, i32 1, i32 3, i32 8, i32 0, i32 8, i32 1, i32 5, i32 1, i32 2, i32 0, i32 4, i32 3, i32 7>, <16 x i32> <i32 3, i32 8, i32 5, i32 5, i32 4, i32 9, i32 4, i32 1, i32 1, i32 4, i32 7, i32 4, i32 6, i32 7, i32 1, i32 1>, i32 204)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 9, i32 7, i32 8, i32 1, i32 3, i32 8, i32 0, i32 8, i32 1, i32 5, i32 1, i32 2, i32 0, i32 4, i32 3, i32 7>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 0, i32 3, i32 7, i32 8, i32 9, i32 0, i32 5, i32 0, i32 5, i32 4, i32 8, i32 6, i32 3, i32 4, i32 5>, <16 x i32> <i32 9, i32 7, i32 8, i32 1, i32 3, i32 8, i32 0, i32 8, i32 1, i32 5, i32 1, i32 2, i32 0, i32 4, i32 3, i32 7>, <16 x i32> <i32 3, i32 8, i32 5, i32 5, i32 4, i32 9, i32 4, i32 1, i32 1, i32 4, i32 7, i32 4, i32 6, i32 7, i32 1, i32 1>, i32 204)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm205() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm205(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 3>, <2 x i64> <i64 5, i64 0>, <2 x i64> <i64 4, i64 4>, i32 205)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -9, i64 -8>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 3>, <2 x i64> <i64 5, i64 0>, <2 x i64> <i64 4, i64 4>, i32 205)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm206() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm206(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 6, i32 9, i32 7, i32 2, i32 3, i32 0, i32 3>, <8 x i32> <i32 6, i32 7, i32 6, i32 9, i32 8, i32 1, i32 9, i32 9>, <8 x i32> <i32 2, i32 3, i32 3, i32 7, i32 7, i32 0, i32 4, i32 6>, i32 206)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 7, i32 6, i32 9, i32 13, i32 1, i32 13, i32 13>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 6, i32 9, i32 7, i32 2, i32 3, i32 0, i32 3>, <8 x i32> <i32 6, i32 7, i32 6, i32 9, i32 8, i32 1, i32 9, i32 9>, <8 x i32> <i32 2, i32 3, i32 3, i32 7, i32 7, i32 0, i32 4, i32 6>, i32 206)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm207() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm207(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 4, i64 7, i64 4, i64 9, i64 3, i64 3, i64 0, i64 5>, <8 x i64> <i64 4, i64 0, i64 4, i64 7, i64 6, i64 7, i64 5, i64 4>, <8 x i64> <i64 8, i64 4, i64 7, i64 5, i64 9, i64 6, i64 6, i64 0>, i32 207)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -8, i64 -1, i64 -9, i64 -2, i64 -1, i64 -1, i64 -2>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 4, i64 7, i64 4, i64 9, i64 3, i64 3, i64 0, i64 5>, <8 x i64> <i64 4, i64 0, i64 4, i64 7, i64 6, i64 7, i64 5, i64 4>, <8 x i64> <i64 8, i64 4, i64 7, i64 5, i64 9, i64 6, i64 6, i64 0>, i32 207)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm208() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm208(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 6, i32 7, i32 9>, <4 x i32> <i32 3, i32 7, i32 7, i32 5>, <4 x i32> <i32 2, i32 4, i32 0, i32 5>, i32 208)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 3, i32 6, i32 7, i32 9>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 6, i32 7, i32 9>, <4 x i32> <i32 3, i32 7, i32 7, i32 5>, <4 x i32> <i32 2, i32 4, i32 0, i32 5>, i32 208)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm209() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm209(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 4, i64 5, i64 1>, <4 x i64> <i64 3, i64 2, i64 1, i64 2>, <4 x i64> <i64 7, i64 8, i64 6, i64 3>, i32 209)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -6, i64 -11, i64 -7, i64 -4>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 4, i64 5, i64 1>, <4 x i64> <i64 3, i64 2, i64 1, i64 2>, <4 x i64> <i64 7, i64 8, i64 6, i64 3>, i32 209)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm210() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm210(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 5, i32 0, i32 3, i32 2, i32 1, i32 1, i32 4, i32 9, i32 5, i32 8, i32 5, i32 8, i32 8, i32 4, i32 5>, <16 x i32> <i32 0, i32 4, i32 5, i32 6, i32 2, i32 1, i32 4, i32 5, i32 3, i32 9, i32 8, i32 9, i32 6, i32 4, i32 2, i32 4>, <16 x i32> <i32 4, i32 7, i32 1, i32 5, i32 5, i32 8, i32 4, i32 5, i32 4, i32 5, i32 1, i32 0, i32 7, i32 0, i32 0, i32 1>, i32 210)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 13, i32 6, i32 0, i32 2, i32 7, i32 9, i32 1, i32 4, i32 13, i32 1, i32 9, i32 5, i32 9, i32 8, i32 4, i32 4>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 5, i32 0, i32 3, i32 2, i32 1, i32 1, i32 4, i32 9, i32 5, i32 8, i32 5, i32 8, i32 8, i32 4, i32 5>, <16 x i32> <i32 0, i32 4, i32 5, i32 6, i32 2, i32 1, i32 4, i32 5, i32 3, i32 9, i32 8, i32 9, i32 6, i32 4, i32 2, i32 4>, <16 x i32> <i32 4, i32 7, i32 1, i32 5, i32 5, i32 8, i32 4, i32 5, i32 4, i32 5, i32 1, i32 0, i32 7, i32 0, i32 0, i32 1>, i32 210)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm211() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm211(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 8>, <2 x i64> <i64 0, i64 4>, <2 x i64> <i64 2, i64 9>, i32 211)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -13>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 8>, <2 x i64> <i64 0, i64 4>, <2 x i64> <i64 2, i64 9>, i32 211)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm212() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm212(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 8, i32 6, i32 4, i32 8, i32 9, i32 9, i32 3>, <8 x i32> <i32 2, i32 7, i32 5, i32 5, i32 3, i32 2, i32 1, i32 6>, <8 x i32> <i32 4, i32 8, i32 3, i32 1, i32 7, i32 6, i32 4, i32 7>, i32 212)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 11, i32 7, i32 4, i32 4, i32 8, i32 9, i32 9, i32 2>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 8, i32 6, i32 4, i32 8, i32 9, i32 9, i32 3>, <8 x i32> <i32 2, i32 7, i32 5, i32 5, i32 3, i32 2, i32 1, i32 6>, <8 x i32> <i32 4, i32 8, i32 3, i32 1, i32 7, i32 6, i32 4, i32 7>, i32 212)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm213() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm213(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 0, i64 8, i64 8, i64 2, i64 8, i64 1, i64 8>, <8 x i64> <i64 8, i64 7, i64 1, i64 5, i64 0, i64 6, i64 2, i64 1>, <8 x i64> <i64 8, i64 7, i64 7, i64 0, i64 3, i64 8, i64 0, i64 1>, i32 213)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -9, i64 -8, i64 -8, i64 -1, i64 -4, i64 -9, i64 -1, i64 -2>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 0, i64 8, i64 8, i64 2, i64 8, i64 1, i64 8>, <8 x i64> <i64 8, i64 7, i64 1, i64 5, i64 0, i64 6, i64 2, i64 1>, <8 x i64> <i64 8, i64 7, i64 7, i64 0, i64 3, i64 8, i64 0, i64 1>, i32 213)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm214() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm214(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 6, i32 7, i32 7>, <4 x i32> <i32 3, i32 1, i32 1, i32 0>, <4 x i32> <i32 6, i32 8, i32 1, i32 6>, i32 214)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 3, i32 15, i32 7, i32 1>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 6, i32 7, i32 7>, <4 x i32> <i32 3, i32 1, i32 1, i32 0>, <4 x i32> <i32 6, i32 8, i32 1, i32 6>, i32 214)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm215() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm215(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 4, i64 3, i64 2>, <4 x i64> <i64 3, i64 5, i64 5, i64 8>, <4 x i64> <i64 2, i64 5, i64 8, i64 6>, i32 215)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -2, i64 -1, i64 -3>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 4, i64 3, i64 2>, <4 x i64> <i64 3, i64 5, i64 5, i64 8>, <4 x i64> <i64 2, i64 5, i64 8, i64 6>, i32 215)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm216() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm216(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 9, i32 9, i32 1, i32 4, i32 8, i32 8, i32 8, i32 8, i32 2, i32 0, i32 9, i32 6, i32 9, i32 1, i32 1>, <16 x i32> <i32 4, i32 8, i32 8, i32 0, i32 0, i32 0, i32 9, i32 4, i32 0, i32 1, i32 1, i32 5, i32 5, i32 8, i32 9, i32 0>, <16 x i32> <i32 6, i32 2, i32 2, i32 2, i32 6, i32 3, i32 4, i32 3, i32 6, i32 6, i32 2, i32 5, i32 6, i32 6, i32 4, i32 1>, i32 216)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 9, i32 9, i32 1, i32 0, i32 8, i32 8, i32 8, i32 8, i32 0, i32 0, i32 13, i32 4, i32 9, i32 1, i32 0>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 9, i32 9, i32 1, i32 4, i32 8, i32 8, i32 8, i32 8, i32 2, i32 0, i32 9, i32 6, i32 9, i32 1, i32 1>, <16 x i32> <i32 4, i32 8, i32 8, i32 0, i32 0, i32 0, i32 9, i32 4, i32 0, i32 1, i32 1, i32 5, i32 5, i32 8, i32 9, i32 0>, <16 x i32> <i32 6, i32 2, i32 2, i32 2, i32 6, i32 3, i32 4, i32 3, i32 6, i32 6, i32 2, i32 5, i32 6, i32 6, i32 4, i32 1>, i32 216)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm217() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm217(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 7>, <2 x i64> <i64 0, i64 6>, <2 x i64> <i64 0, i64 8>, i32 217)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -9>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 7>, <2 x i64> <i64 0, i64 6>, <2 x i64> <i64 0, i64 8>, i32 217)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm218() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm218(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 0, i32 7, i32 1, i32 5, i32 0, i32 4, i32 3>, <8 x i32> <i32 0, i32 6, i32 5, i32 7, i32 6, i32 9, i32 1, i32 0>, <8 x i32> <i32 0, i32 6, i32 1, i32 8, i32 8, i32 4, i32 0, i32 7>, i32 218)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 6, i32 7, i32 9, i32 13, i32 4, i32 4, i32 4>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 0, i32 7, i32 1, i32 5, i32 0, i32 4, i32 3>, <8 x i32> <i32 0, i32 6, i32 5, i32 7, i32 6, i32 9, i32 1, i32 0>, <8 x i32> <i32 0, i32 6, i32 1, i32 8, i32 8, i32 4, i32 0, i32 7>, i32 218)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm219() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm219(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 2, i64 0, i64 6, i64 7, i64 1, i64 4, i64 4>, <8 x i64> <i64 7, i64 7, i64 1, i64 1, i64 1, i64 6, i64 6, i64 1>, <8 x i64> <i64 4, i64 2, i64 3, i64 1, i64 7, i64 7, i64 3, i64 9>, i32 219)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -3, i64 -6, i64 -1, i64 -1, i64 -7, i64 -2, i64 -1, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 2, i64 0, i64 6, i64 7, i64 1, i64 4, i64 4>, <8 x i64> <i64 7, i64 7, i64 1, i64 1, i64 1, i64 6, i64 6, i64 1>, <8 x i64> <i64 4, i64 2, i64 3, i64 1, i64 7, i64 7, i64 3, i64 9>, i32 219)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm220() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm220(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 2, i32 4, i32 3, i32 6>, <4 x i32> <i32 0, i32 4, i32 8, i32 4>, <4 x i32> <i32 5, i32 9, i32 9, i32 8>, i32 220)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 2, i32 4, i32 10, i32 6>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 2, i32 4, i32 3, i32 6>, <4 x i32> <i32 0, i32 4, i32 8, i32 4>, <4 x i32> <i32 5, i32 9, i32 9, i32 8>, i32 220)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm221() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm221(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 7, i64 2, i64 2>, <4 x i64> <i64 5, i64 3, i64 8, i64 2>, <4 x i64> <i64 9, i64 5, i64 5, i64 8>, i32 221)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -9, i64 -5, i64 -6, i64 -9>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 7, i64 2, i64 2>, <4 x i64> <i64 5, i64 3, i64 8, i64 2>, <4 x i64> <i64 9, i64 5, i64 5, i64 8>, i32 221)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm222() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm222(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 2, i32 3, i32 7, i32 2, i32 5, i32 2, i32 9, i32 0, i32 7, i32 7, i32 1, i32 7, i32 9, i32 0, i32 6, i32 6>, <16 x i32> <i32 0, i32 6, i32 8, i32 7, i32 2, i32 6, i32 6, i32 2, i32 9, i32 6, i32 6, i32 2, i32 7, i32 3, i32 1, i32 5>, <16 x i32> <i32 3, i32 9, i32 0, i32 0, i32 7, i32 3, i32 5, i32 1, i32 4, i32 1, i32 7, i32 9, i32 4, i32 4, i32 0, i32 7>, i32 222)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 1, i32 14, i32 15, i32 7, i32 2, i32 7, i32 14, i32 3, i32 11, i32 6, i32 6, i32 14, i32 15, i32 7, i32 7, i32 5>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 2, i32 3, i32 7, i32 2, i32 5, i32 2, i32 9, i32 0, i32 7, i32 7, i32 1, i32 7, i32 9, i32 0, i32 6, i32 6>, <16 x i32> <i32 0, i32 6, i32 8, i32 7, i32 2, i32 6, i32 6, i32 2, i32 9, i32 6, i32 6, i32 2, i32 7, i32 3, i32 1, i32 5>, <16 x i32> <i32 3, i32 9, i32 0, i32 0, i32 7, i32 3, i32 5, i32 1, i32 4, i32 1, i32 7, i32 9, i32 4, i32 4, i32 0, i32 7>, i32 222)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm223() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm223(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 4, i64 3>, <2 x i64> <i64 7, i64 9>, <2 x i64> <i64 5, i64 0>, i32 223)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -1>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 4, i64 3>, <2 x i64> <i64 7, i64 9>, <2 x i64> <i64 5, i64 0>, i32 223)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm224() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm224(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 7, i32 7, i32 8, i32 0, i32 7, i32 9, i32 1>, <8 x i32> <i32 8, i32 9, i32 8, i32 0, i32 8, i32 1, i32 5, i32 7>, <8 x i32> <i32 2, i32 8, i32 9, i32 2, i32 8, i32 5, i32 3, i32 0>, i32 224)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 8, i32 1, i32 1, i32 0, i32 0, i32 5, i32 1, i32 1>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 7, i32 7, i32 8, i32 0, i32 7, i32 9, i32 1>, <8 x i32> <i32 8, i32 9, i32 8, i32 0, i32 8, i32 1, i32 5, i32 7>, <8 x i32> <i32 2, i32 8, i32 9, i32 2, i32 8, i32 5, i32 3, i32 0>, i32 224)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm225() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm225(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 1, i64 1, i64 7, i64 4, i64 7, i64 1, i64 0>, <8 x i64> <i64 0, i64 8, i64 8, i64 8, i64 8, i64 7, i64 1, i64 2>, <8 x i64> <i64 6, i64 1, i64 2, i64 2, i64 5, i64 8, i64 6, i64 3>, i32 225)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -6, i64 -9, i64 -12, i64 -14, i64 -10, i64 -9, i64 -7, i64 -4>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 1, i64 1, i64 7, i64 4, i64 7, i64 1, i64 0>, <8 x i64> <i64 0, i64 8, i64 8, i64 8, i64 8, i64 7, i64 1, i64 2>, <8 x i64> <i64 6, i64 1, i64 2, i64 2, i64 5, i64 8, i64 6, i64 3>, i32 225)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm226() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm226(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 2, i32 3, i32 7>, <4 x i32> <i32 8, i32 6, i32 4, i32 9>, <4 x i32> <i32 9, i32 4, i32 2, i32 1>, i32 226)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 1, i32 2, i32 2, i32 1>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 2, i32 3, i32 7>, <4 x i32> <i32 8, i32 6, i32 4, i32 9>, <4 x i32> <i32 9, i32 4, i32 2, i32 1>, i32 226)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm227() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm227(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 6, i64 3, i64 2>, <4 x i64> <i64 2, i64 7, i64 7, i64 5>, <4 x i64> <i64 1, i64 0, i64 4, i64 2>, i32 227)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -2, i64 -5, i64 -6>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 6, i64 3, i64 2>, <4 x i64> <i64 2, i64 7, i64 7, i64 5>, <4 x i64> <i64 1, i64 0, i64 4, i64 2>, i32 227)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm228() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm228(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 6, i32 2, i32 9, i32 0, i32 2, i32 8, i32 6, i32 1, i32 2, i32 2, i32 8, i32 0, i32 0, i32 2, i32 0>, <16 x i32> <i32 5, i32 7, i32 0, i32 5, i32 4, i32 3, i32 7, i32 3, i32 5, i32 1, i32 3, i32 2, i32 3, i32 9, i32 4, i32 3>, <16 x i32> <i32 4, i32 3, i32 8, i32 3, i32 7, i32 4, i32 3, i32 0, i32 2, i32 7, i32 5, i32 5, i32 1, i32 4, i32 7, i32 6>, i32 228)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 1, i32 6, i32 0, i32 5, i32 0, i32 3, i32 4, i32 3, i32 5, i32 2, i32 2, i32 2, i32 2, i32 9, i32 2, i32 1>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 6, i32 2, i32 9, i32 0, i32 2, i32 8, i32 6, i32 1, i32 2, i32 2, i32 8, i32 0, i32 0, i32 2, i32 0>, <16 x i32> <i32 5, i32 7, i32 0, i32 5, i32 4, i32 3, i32 7, i32 3, i32 5, i32 1, i32 3, i32 2, i32 3, i32 9, i32 4, i32 3>, <16 x i32> <i32 4, i32 3, i32 8, i32 3, i32 7, i32 4, i32 3, i32 0, i32 2, i32 7, i32 5, i32 5, i32 1, i32 4, i32 7, i32 6>, i32 228)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm229() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm229(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 2>, <2 x i64> <i64 9, i64 4>, <2 x i64> zeroinitializer, i32 229)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -3>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 2>, <2 x i64> <i64 9, i64 4>, <2 x i64> <i64 0, i64 0>, i32 229)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm230() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm230(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 6, i32 1, i32 3, i32 7, i32 6, i32 9, i32 6>, <8 x i32> <i32 9, i32 7, i32 0, i32 4, i32 7, i32 0, i32 0, i32 8>, <8 x i32> <i32 6, i32 1, i32 1, i32 7, i32 5, i32 1, i32 3, i32 9>, i32 230)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 15, i32 6, i32 1, i32 3, i32 7, i32 1, i32 3, i32 1>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 6, i32 1, i32 3, i32 7, i32 6, i32 9, i32 6>, <8 x i32> <i32 9, i32 7, i32 0, i32 4, i32 7, i32 0, i32 0, i32 8>, <8 x i32> <i32 6, i32 1, i32 1, i32 7, i32 5, i32 1, i32 3, i32 9>, i32 230)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm231() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm231(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 9, i64 3, i64 9, i64 0, i64 3, i64 9, i64 6, i64 1>, <8 x i64> <i64 9, i64 5, i64 3, i64 3, i64 2, i64 3, i64 4, i64 7>, <8 x i64> <i64 7, i64 5, i64 0, i64 1, i64 6, i64 3, i64 7, i64 1>, i32 231)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -7, i64 -9, i64 -2, i64 -2, i64 -11, i64 -1, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 9, i64 3, i64 9, i64 0, i64 3, i64 9, i64 6, i64 1>, <8 x i64> <i64 9, i64 5, i64 3, i64 3, i64 2, i64 3, i64 4, i64 7>, <8 x i64> <i64 7, i64 5, i64 0, i64 1, i64 6, i64 3, i64 7, i64 1>, i32 231)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm232() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm232(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 7, i32 7, i32 7>, <4 x i32> <i32 9, i32 8, i32 0, i32 6>, <4 x i32> <i32 4, i32 2, i32 3, i32 5>, i32 232)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 2, i32 3, i32 7>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 7, i32 7, i32 7>, <4 x i32> <i32 9, i32 8, i32 0, i32 6>, <4 x i32> <i32 4, i32 2, i32 3, i32 5>, i32 232)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm233() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm233(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 4, i64 1, i64 5>, <4 x i64> <i64 2, i64 3, i64 0, i64 5>, <4 x i64> <i64 0, i64 9, i64 6, i64 9>, i32 233)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -2, i64 -15, i64 -8, i64 -9>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 4, i64 1, i64 5>, <4 x i64> <i64 2, i64 3, i64 0, i64 5>, <4 x i64> <i64 0, i64 9, i64 6, i64 9>, i32 233)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm234() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm234(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 4, i32 2, i32 3, i32 9, i32 4, i32 8, i32 1, i32 1, i32 4, i32 7, i32 7, i32 9, i32 3, i32 4, i32 8>, <16 x i32> <i32 9, i32 4, i32 2, i32 9, i32 8, i32 0, i32 3, i32 9, i32 5, i32 8, i32 9, i32 0, i32 8, i32 7, i32 7, i32 9>, <16 x i32> <i32 5, i32 1, i32 9, i32 9, i32 8, i32 4, i32 9, i32 3, i32 5, i32 9, i32 9, i32 4, i32 7, i32 1, i32 5, i32 7>, i32 234)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 5, i32 5, i32 11, i32 9, i32 8, i32 4, i32 9, i32 3, i32 5, i32 9, i32 9, i32 4, i32 15, i32 3, i32 5, i32 15>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 4, i32 2, i32 3, i32 9, i32 4, i32 8, i32 1, i32 1, i32 4, i32 7, i32 7, i32 9, i32 3, i32 4, i32 8>, <16 x i32> <i32 9, i32 4, i32 2, i32 9, i32 8, i32 0, i32 3, i32 9, i32 5, i32 8, i32 9, i32 0, i32 8, i32 7, i32 7, i32 9>, <16 x i32> <i32 5, i32 1, i32 9, i32 9, i32 8, i32 4, i32 9, i32 3, i32 5, i32 9, i32 9, i32 4, i32 7, i32 1, i32 5, i32 7>, i32 234)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm235() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm235(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 5>, <2 x i64> <i64 2, i64 8>, <2 x i64> <i64 8, i64 2>, i32 235)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -14>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 5>, <2 x i64> <i64 2, i64 8>, <2 x i64> <i64 8, i64 2>, i32 235)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm236() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm236(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 4, i32 9, i32 5, i32 9, i32 3, i32 9, i32 0>, <8 x i32> <i32 9, i32 5, i32 6, i32 5, i32 9, i32 5, i32 4, i32 3>, <8 x i32> <i32 5, i32 5, i32 1, i32 7, i32 5, i32 8, i32 4, i32 2>, i32 236)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 9, i32 5, i32 7, i32 5, i32 9, i32 5, i32 4, i32 3>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 4, i32 9, i32 5, i32 9, i32 3, i32 9, i32 0>, <8 x i32> <i32 9, i32 5, i32 6, i32 5, i32 9, i32 5, i32 4, i32 3>, <8 x i32> <i32 5, i32 5, i32 1, i32 7, i32 5, i32 8, i32 4, i32 2>, i32 236)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm237() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm237(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 3, i64 5, i64 9, i64 0, i64 0, i64 8, i64 5>, <8 x i64> <i64 6, i64 3, i64 7, i64 6, i64 8, i64 8, i64 7, i64 7>, <8 x i64> <i64 2, i64 9, i64 4, i64 5, i64 1, i64 7, i64 2, i64 1>, i32 237)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -2, i64 -9, i64 -1, i64 -9, i64 -2, i64 -8, i64 -9, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 3, i64 5, i64 9, i64 0, i64 0, i64 8, i64 5>, <8 x i64> <i64 6, i64 3, i64 7, i64 6, i64 8, i64 8, i64 7, i64 7>, <8 x i64> <i64 2, i64 9, i64 4, i64 5, i64 1, i64 7, i64 2, i64 1>, i32 237)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm238() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm238(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 9, i32 1, i32 4>, <4 x i32> <i32 7, i32 1, i32 7, i32 3>, <4 x i32> <i32 5, i32 4, i32 8, i32 9>, i32 238)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 5, i32 15, i32 11>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 9, i32 1, i32 4>, <4 x i32> <i32 7, i32 1, i32 7, i32 3>, <4 x i32> <i32 5, i32 4, i32 8, i32 9>, i32 238)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm239() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm239(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 4, i64 5, i64 8>, <4 x i64> <i64 1, i64 0, i64 9, i64 6>, <4 x i64> <i64 8, i64 0, i64 5, i64 4>, i32 239)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -5, i64 -1, i64 -9>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 4, i64 5, i64 8>, <4 x i64> <i64 1, i64 0, i64 9, i64 6>, <4 x i64> <i64 8, i64 0, i64 5, i64 4>, i32 239)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm240() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm240(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 8, i32 5, i32 3, i32 1, i32 4, i32 7, i32 7, i32 8, i32 7, i32 7, i32 7, i32 2, i32 0, i32 9, i32 8>, <16 x i32> <i32 8, i32 0, i32 7, i32 3, i32 9, i32 2, i32 3, i32 4, i32 7, i32 5, i32 8, i32 3, i32 8, i32 1, i32 8, i32 6>, <16 x i32> <i32 0, i32 8, i32 4, i32 1, i32 1, i32 6, i32 2, i32 7, i32 8, i32 9, i32 0, i32 0, i32 9, i32 5, i32 1, i32 3>, i32 240)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 3, i32 8, i32 5, i32 3, i32 1, i32 4, i32 7, i32 7, i32 8, i32 7, i32 7, i32 7, i32 2, i32 0, i32 9, i32 8>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 8, i32 5, i32 3, i32 1, i32 4, i32 7, i32 7, i32 8, i32 7, i32 7, i32 7, i32 2, i32 0, i32 9, i32 8>, <16 x i32> <i32 8, i32 0, i32 7, i32 3, i32 9, i32 2, i32 3, i32 4, i32 7, i32 5, i32 8, i32 3, i32 8, i32 1, i32 8, i32 6>, <16 x i32> <i32 0, i32 8, i32 4, i32 1, i32 1, i32 6, i32 2, i32 7, i32 8, i32 9, i32 0, i32 0, i32 9, i32 5, i32 1, i32 3>, i32 240)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm241() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm241(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 6>, <2 x i64> <i64 8, i64 7>, <2 x i64> <i64 1, i64 4>, i32 241)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -9, i64 -2>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 6>, <2 x i64> <i64 8, i64 7>, <2 x i64> <i64 1, i64 4>, i32 241)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm242() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm242(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 6, i32 0, i32 0, i32 9, i32 1, i32 9, i32 5>, <8 x i32> <i32 1, i32 3, i32 3, i32 9, i32 8, i32 3, i32 4, i32 4>, <8 x i32> <i32 5, i32 3, i32 5, i32 6, i32 7, i32 9, i32 7, i32 0>, i32 242)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 7, i32 6, i32 4, i32 6, i32 15, i32 9, i32 11, i32 5>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 6, i32 0, i32 0, i32 9, i32 1, i32 9, i32 5>, <8 x i32> <i32 1, i32 3, i32 3, i32 9, i32 8, i32 3, i32 4, i32 4>, <8 x i32> <i32 5, i32 3, i32 5, i32 6, i32 7, i32 9, i32 7, i32 0>, i32 242)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm243() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm243(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 3, i64 6, i64 6, i64 7, i64 0>, <8 x i64> <i64 9, i64 5, i64 5, i64 4, i64 3, i64 2, i64 5, i64 9>, <8 x i64> <i64 0, i64 7, i64 0, i64 1, i64 4, i64 5, i64 5, i64 6>, i32 243)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -5, i64 -6, i64 -5, i64 -2, i64 -1, i64 -1, i64 -10>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 3, i64 6, i64 6, i64 7, i64 0>, <8 x i64> <i64 9, i64 5, i64 5, i64 4, i64 3, i64 2, i64 5, i64 9>, <8 x i64> <i64 0, i64 7, i64 0, i64 1, i64 4, i64 5, i64 5, i64 6>, i32 243)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm244() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm244(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 7, i32 5, i32 8, i32 7>, <4 x i32> <i32 3, i32 1, i32 1, i32 2>, <4 x i32> <i32 9, i32 3, i32 0, i32 3>, i32 244)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 5, i32 9, i32 7>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 7, i32 5, i32 8, i32 7>, <4 x i32> <i32 3, i32 1, i32 1, i32 2>, <4 x i32> <i32 9, i32 3, i32 0, i32 3>, i32 244)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm245() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm245(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 9, i64 3, i64 9, i64 6>, <4 x i64> <i64 3, i64 6, i64 1, i64 7>, <4 x i64> <i64 7, i64 3, i64 4, i64 9>, i32 245)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -1, i64 -5, i64 -10>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 9, i64 3, i64 9, i64 6>, <4 x i64> <i64 3, i64 6, i64 1, i64 7>, <4 x i64> <i64 7, i64 3, i64 4, i64 9>, i32 245)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm246() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm246(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 1, i32 9, i32 2, i32 5, i32 6, i32 6, i32 4, i32 9, i32 5, i32 8, i32 4, i32 0, i32 5, i32 3, i32 6>, <16 x i32> <i32 6, i32 5, i32 6, i32 4, i32 6, i32 2, i32 2, i32 7, i32 3, i32 6, i32 3, i32 0, i32 2, i32 8, i32 7, i32 9>, <16 x i32> <i32 7, i32 7, i32 1, i32 5, i32 4, i32 5, i32 4, i32 6, i32 2, i32 1, i32 6, i32 0, i32 7, i32 1, i32 6, i32 4>, i32 246)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 7, i32 3, i32 15, i32 3, i32 7, i32 7, i32 6, i32 5, i32 9, i32 7, i32 13, i32 4, i32 5, i32 13, i32 3, i32 15>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 1, i32 9, i32 2, i32 5, i32 6, i32 6, i32 4, i32 9, i32 5, i32 8, i32 4, i32 0, i32 5, i32 3, i32 6>, <16 x i32> <i32 6, i32 5, i32 6, i32 4, i32 6, i32 2, i32 2, i32 7, i32 3, i32 6, i32 3, i32 0, i32 2, i32 8, i32 7, i32 9>, <16 x i32> <i32 7, i32 7, i32 1, i32 5, i32 4, i32 5, i32 4, i32 6, i32 2, i32 1, i32 6, i32 0, i32 7, i32 1, i32 6, i32 4>, i32 246)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm247() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm247(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 6>, <2 x i64> <i64 7, i64 7>, <2 x i64> <i64 0, i64 8>, i32 247)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -1>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 6>, <2 x i64> <i64 7, i64 7>, <2 x i64> <i64 0, i64 8>, i32 247)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm248() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm248(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 2, i32 4, i32 3, i32 2, i32 6, i32 6, i32 5>, <8 x i32> <i32 6, i32 5, i32 8, i32 4, i32 4, i32 5, i32 4, i32 4>, <8 x i32> <i32 6, i32 7, i32 8, i32 3, i32 4, i32 4, i32 7, i32 6>, i32 248)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 7, i32 7, i32 12, i32 3, i32 6, i32 6, i32 6, i32 5>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 2, i32 4, i32 3, i32 2, i32 6, i32 6, i32 5>, <8 x i32> <i32 6, i32 5, i32 8, i32 4, i32 4, i32 5, i32 4, i32 4>, <8 x i32> <i32 6, i32 7, i32 8, i32 3, i32 4, i32 4, i32 7, i32 6>, i32 248)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm249() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm249(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 5, i64 7, i64 2, i64 2, i64 4, i64 1, i64 3>, <8 x i64> <i64 4, i64 1, i64 8, i64 6, i64 0, i64 7, i64 2, i64 5>, <8 x i64> <i64 3, i64 5, i64 4, i64 6, i64 0, i64 1, i64 0, i64 7>, i32 249)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -1, i64 -9, i64 -1, i64 -1, i64 -3, i64 -3, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 5, i64 7, i64 2, i64 2, i64 4, i64 1, i64 3>, <8 x i64> <i64 4, i64 1, i64 8, i64 6, i64 0, i64 7, i64 2, i64 5>, <8 x i64> <i64 3, i64 5, i64 4, i64 6, i64 0, i64 1, i64 0, i64 7>, i32 249)
   ret <8 x i64> %r
 }
 
 define <4 x i32> @vpternlog_d_constv128_imm250() {
 ; CHECK-LABEL: @vpternlog_d_constv128_imm250(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 1, i32 3, i32 5>, <4 x i32> <i32 8, i32 4, i32 0, i32 9>, <4 x i32> <i32 3, i32 8, i32 3, i32 5>, i32 250)
-; CHECK-NEXT:    ret <4 x i32> [[R]]
+; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 9, i32 3, i32 5>
 ;
   %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 1, i32 3, i32 5>, <4 x i32> <i32 8, i32 4, i32 0, i32 9>, <4 x i32> <i32 3, i32 8, i32 3, i32 5>, i32 250)
   ret <4 x i32> %r
 }
 
 define <4 x i64> @vpternlog_q_constv256_imm251() {
 ; CHECK-LABEL: @vpternlog_q_constv256_imm251(
-; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 8, i64 4, i64 3>, <4 x i64> <i64 1, i64 5, i64 8, i64 1>, <4 x i64> <i64 1, i64 9, i64 9, i64 4>, i32 251)
-; CHECK-NEXT:    ret <4 x i64> [[R]]
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -5, i64 -1, i64 -1>
 ;
   %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 8, i64 4, i64 3>, <4 x i64> <i64 1, i64 5, i64 8, i64 1>, <4 x i64> <i64 1, i64 9, i64 9, i64 4>, i32 251)
   ret <4 x i64> %r
 }
 
 define <16 x i32> @vpternlog_d_constv512_imm252() {
 ; CHECK-LABEL: @vpternlog_d_constv512_imm252(
-; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 2, i32 9, i32 6, i32 2, i32 3, i32 0, i32 3, i32 3, i32 3, i32 3, i32 5, i32 0, i32 9, i32 6, i32 4, i32 7>, <16 x i32> <i32 9, i32 4, i32 6, i32 1, i32 9, i32 6, i32 6, i32 0, i32 5, i32 7, i32 6, i32 8, i32 9, i32 9, i32 5, i32 1>, <16 x i32> <i32 2, i32 8, i32 3, i32 8, i32 7, i32 7, i32 2, i32 3, i32 0, i32 6, i32 5, i32 8, i32 0, i32 2, i32 6, i32 1>, i32 252)
-; CHECK-NEXT:    ret <16 x i32> [[R]]
+; CHECK-NEXT:    ret <16 x i32> <i32 11, i32 13, i32 6, i32 3, i32 11, i32 6, i32 7, i32 3, i32 7, i32 7, i32 7, i32 8, i32 9, i32 15, i32 5, i32 7>
 ;
   %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 2, i32 9, i32 6, i32 2, i32 3, i32 0, i32 3, i32 3, i32 3, i32 3, i32 5, i32 0, i32 9, i32 6, i32 4, i32 7>, <16 x i32> <i32 9, i32 4, i32 6, i32 1, i32 9, i32 6, i32 6, i32 0, i32 5, i32 7, i32 6, i32 8, i32 9, i32 9, i32 5, i32 1>, <16 x i32> <i32 2, i32 8, i32 3, i32 8, i32 7, i32 7, i32 2, i32 3, i32 0, i32 6, i32 5, i32 8, i32 0, i32 2, i32 6, i32 1>, i32 252)
   ret <16 x i32> %r
 }
 
 define <2 x i64> @vpternlog_q_constv128_imm253() {
 ; CHECK-LABEL: @vpternlog_q_constv128_imm253(
-; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 5, i64 6>, <2 x i64> <i64 6, i64 1>, <2 x i64> <i64 5, i64 9>, i32 253)
-; CHECK-NEXT:    ret <2 x i64> [[R]]
+; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -9>
 ;
   %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 5, i64 6>, <2 x i64> <i64 6, i64 1>, <2 x i64> <i64 5, i64 9>, i32 253)
   ret <2 x i64> %r
 }
 
 define <8 x i32> @vpternlog_d_constv256_imm254() {
 ; CHECK-LABEL: @vpternlog_d_constv256_imm254(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 6, i32 1, i32 9, i32 4, i32 1, i32 9, i32 7>, <8 x i32> <i32 2, i32 9, i32 1, i32 5, i32 7, i32 1, i32 0, i32 9>, <8 x i32> <i32 1, i32 6, i32 2, i32 8, i32 8, i32 7, i32 0, i32 7>, i32 254)
-; CHECK-NEXT:    ret <8 x i32> [[R]]
+; CHECK-NEXT:    ret <8 x i32> <i32 7, i32 15, i32 3, i32 13, i32 15, i32 7, i32 9, i32 15>
 ;
   %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 6, i32 1, i32 9, i32 4, i32 1, i32 9, i32 7>, <8 x i32> <i32 2, i32 9, i32 1, i32 5, i32 7, i32 1, i32 0, i32 9>, <8 x i32> <i32 1, i32 6, i32 2, i32 8, i32 8, i32 7, i32 0, i32 7>, i32 254)
   ret <8 x i32> %r
 }
 
 define <8 x i64> @vpternlog_q_constv512_imm255() {
 ; CHECK-LABEL: @vpternlog_q_constv512_imm255(
-; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 3, i64 6, i64 0, i64 0, i64 6, i64 9, i64 3>, <8 x i64> <i64 4, i64 2, i64 1, i64 5, i64 3, i64 1, i64 5, i64 0>, <8 x i64> <i64 1, i64 5, i64 4, i64 4, i64 9, i64 7, i64 2, i64 5>, i32 255)
-; CHECK-NEXT:    ret <8 x i64> [[R]]
+; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
 ;
   %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 3, i64 6, i64 0, i64 0, i64 6, i64 9, i64 3>, <8 x i64> <i64 4, i64 2, i64 1, i64 5, i64 3, i64 1, i64 5, i64 0>, <8 x i64> <i64 1, i64 5, i64 4, i64 4, i64 9, i64 7, i64 2, i64 5>, i32 255)
   ret <8 x i64> %r
 }

llvm/unittests/Transforms/CMakeLists.txt

 add_subdirectory(Coroutines)
 add_subdirectory(IPO)
+add_subdirectory(InstCombine)
 add_subdirectory(Scalar)
 add_subdirectory(Utils)
 add_subdirectory(Vectorize)

llvm/unittests/Transforms/InstCombine/CMakeLists.txt

+add_subdirectory(X86)

llvm/unittests/Transforms/InstCombine/X86/CMakeLists.txt

+set(LLVM_LINK_COMPONENTS
+  Analysis
+  AsmParser
+  Core
+  Passes
+  Support
+  ScalarOpts
+  TransformUtils
+  InstCombine
+  Target
+  TargetParser
+  X86CodeGen
+  X86Desc
+  X86Info
+  MC
+  )
+
+add_llvm_unittest(InstCombineX86Tests
+  TernlogTest.cpp
+  )
+
+target_link_libraries(InstCombineX86Tests PRIVATE LLVMTestingSupport)
+set_property(TARGET InstCombineX86Tests PROPERTY FOLDER "Tests/UnitTests/TransformsTests")

llvm/unittests/Transforms/InstCombine/X86/TernlogTest.cpp

+//===- LICMTest.cpp - LICM unit tests -------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/AsmParser/Parser.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Passes/PassBuilder.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Transforms/InstCombine/InstCombine.h"
+
+#include "gtest/gtest.h"
+
+#include <random>
+
+namespace llvm {
+static std::unique_ptr<LLVMTargetMachine> initTM() {
+  LLVMInitializeX86TargetInfo();
+  LLVMInitializeX86Target();
+  LLVMInitializeX86TargetMC();
+
+  auto TT(Triple::normalize("x86_64--"));
+  std::string Error;
+  const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
+  return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
+      TheTarget->createTargetMachine(TT, "", "", TargetOptions(), std::nullopt,
+                                     std::nullopt, CodeGenOpt::Default)));
+}
+
+struct TernTester {
+  unsigned NElem;
+  unsigned ElemWidth;
+  std::mt19937_64 Rng;
+  unsigned ImmVal;
+  SmallVector<uint64_t, 16> VecElems[3];
+
+  void updateImm(uint8_t NewImmVal) { ImmVal = NewImmVal; }
+  void updateNElem(unsigned NewNElem) {
+    NElem = NewNElem;
+    for (unsigned I = 0; I < 3; ++I) {
+      VecElems[I].resize(NElem);
+    }
+  }
+  void updateElemWidth(unsigned NewElemWidth) {
+    ElemWidth = NewElemWidth;
+    assert(ElemWidth == 32 || ElemWidth == 64);
+  }
+
+  uint64_t getElemMask() const {
+    return (~uint64_t(0)) >> ((ElemWidth - 0) % 64);
+  }
+
+  void RandomizeVecArgs() {
+    uint64_t ElemMask = getElemMask();
+    for (unsigned I = 0; I < 3; ++I) {
+      for (unsigned J = 0; J < NElem; ++J) {
+        VecElems[I][J] = Rng() & ElemMask;
+      }
+    }
+  }
+
+  std::pair<std::string, std::string> getScalarInfo() const {
+    switch (ElemWidth) {
+    case 32:
+      return {"i32", "d"};
+    case 64:
+      return {"i64", "q"};
+    default:
+      llvm_unreachable("Invalid ElemWidth");
+    }
+  }
+  std::string getScalarType() const { return getScalarInfo().first; }
+  std::string getScalarExt() const { return getScalarInfo().second; }
+  std::string getVecType() const {
+    return "<" + Twine(NElem).str() + " x " + getScalarType() + ">";
+  };
+
+  std::string getVecWidth() const { return Twine(NElem * ElemWidth).str(); }
+  std::string getFunctionName() const {
+    return "@llvm.x86.avx512.pternlog." + getScalarExt() + "." + getVecWidth();
+  }
+  std::string getFunctionDecl() const {
+    return "declare " + getVecType() + getFunctionName() + "(" + getVecType() +
+           ", " + getVecType() + ", " + getVecType() + ", " + "i32 immarg)";
+  }
+
+  std::string getVecN(unsigned N) const {
+    assert(N < 3);
+    std::string VecStr = getVecType() + " <";
+    for (unsigned I = 0; I < VecElems[N].size(); ++I) {
+      if (I != 0)
+        VecStr += ", ";
+      VecStr += getScalarType() + " " + Twine(VecElems[N][I]).str();
+    }
+    return VecStr + ">";
+  }
+  std::string getFunctionCall() const {
+    return "tail call " + getVecType() + " " + getFunctionName() + "(" +
+           getVecN(0) + ", " + getVecN(1) + ", " + getVecN(2) + ", " + "i32 " +
+           Twine(ImmVal).str() + ")";
+  }
+
+  std::string getTestText() const {
+    return getFunctionDecl() + "\ndefine " + getVecType() +
+           "@foo() {\n%r = " + getFunctionCall() + "\nret " + getVecType() +
+           " %r\n}\n";
+  }
+
+  void checkResult(const Value *V) {
+    auto GetValElem = [&](unsigned Idx) -> uint64_t {
+      if (auto *CV = dyn_cast<ConstantDataVector>(V))
+        return CV->getElementAsInteger(Idx);
+
+      auto *C = dyn_cast<Constant>(V);
+      assert(C);
+      if (C->isNullValue())
+        return 0;
+      if (C->isAllOnesValue())
+        return ((~uint64_t(0)) >> (ElemWidth % 64));
+      if (C->isOneValue())
+        return 1;
+
+      assert(0 && "Unknown constant type");
+    };
+
+    auto ComputeBit = [&](uint64_t A, uint64_t B, uint64_t C) -> uint64_t {
+      unsigned BitIdx = ((A & 1) << 2) | ((B & 1) << 1) | (C & 1);
+      return (ImmVal >> BitIdx) & 1;
+    };
+
+    for (unsigned I = 0; I < NElem; ++I) {
+      uint64_t Expec = 0;
+      uint64_t AEle = VecElems[0][I];
+      uint64_t BEle = VecElems[1][I];
+      uint64_t CEle = VecElems[2][I];
+      for (unsigned J = 0; J < ElemWidth; ++J) {
+        Expec |= ComputeBit(AEle >> J, BEle >> J, CEle >> J) << J;
+      }
+
+      ASSERT_EQ(Expec, GetValElem(I));
+    }
+  }
+
+  void check(LLVMContext &Ctx, FunctionPassManager &FPM,
+             FunctionAnalysisManager &FAM) {
+    SMDiagnostic Error;
+    std::unique_ptr<Module> M = parseAssemblyString(getTestText(), Error, Ctx);
+    ASSERT_TRUE(M);
+    Function *F = M->getFunction("foo");
+    ASSERT_TRUE(F);
+    ASSERT_EQ(F->getInstructionCount(), 2u);
+    FPM.run(*F, FAM);
+    ASSERT_EQ(F->getInstructionCount(), 1u);
+    ASSERT_EQ(F->size(), 1u);
+    const Instruction *I = F->begin()->getTerminator();
+    ASSERT_TRUE(I);
+    ASSERT_EQ(I->getNumOperands(), 1u);
+    checkResult(I->getOperand(0));
+  }
+};
+
+TEST(TernlogTest, TestConstantFolding) {
+  LLVMContext Ctx;
+  FunctionAnalysisManager FAM;
+  FunctionPassManager FPM;
+  PassBuilder PB;
+  LoopAnalysisManager LAM;
+  CGSCCAnalysisManager CGAM;
+  ModuleAnalysisManager MAM;
+  TargetIRAnalysis TIRA = TargetIRAnalysis(
+      [&](const Function &F) { return initTM()->getTargetTransformInfo(F); });
+
+  FAM.registerPass([&] { return TIRA; });
+  PB.registerModuleAnalyses(MAM);
+  PB.registerCGSCCAnalyses(CGAM);
+  PB.registerFunctionAnalyses(FAM);
+  PB.registerLoopAnalyses(LAM);
+  PB.crossRegisterProxies(LAM, FAM, CGAM, MAM);
+
+  FPM.addPass(InstCombinePass());
+  TernTester TT;
+  for (unsigned NElem = 2; NElem < 16; NElem += NElem) {
+    TT.updateNElem(NElem);
+    for (unsigned ElemWidth = 32; ElemWidth <= 64; ElemWidth += ElemWidth) {
+      if (ElemWidth * NElem > 512 || ElemWidth * NElem < 128)
+        continue;
+      TT.updateElemWidth(ElemWidth);
+      TT.RandomizeVecArgs();
+      for (unsigned Imm = 0; Imm < 256; ++Imm) {
+        TT.updateImm(Imm);
+        TT.check(Ctx, FPM, FAM);
+      }
+    }
+  }
+}
+} // namespace llvm