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Differential D144458

[RISCV] Pre-commit test case for ordered reduction, NFC
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Authored by Mel-Chen on Feb 21 2023, 1:34 AM.

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reames
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rG9d0703a6461b: [RISCV] Pre-commit test case for ordered reduction, NFC

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Mel-Chen created this revision.Feb 21 2023, 1:34 AM
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Mel-Chen requested review of this revision.Feb 21 2023, 1:34 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 21 2023, 1:34 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Mel-Chen added a child revision: D144455: [RISCV] Enable ordered reduction..Feb 21 2023, 1:36 AM
Harbormaster completed remote builds in B214954: Diff 499075.Feb 21 2023, 3:41 AM
reames accepted this revision.Feb 22 2023, 3:09 PM
reames added a subscriber: reames.

LGTM w/comment addressed before landing.

llvm/test/Transforms/LoopVectorize/RISCV/ordered-reduction.ll
3

Please add a check line for the configuration: -force-ordered-reductions=true -hints-allow-reordering=false.

This allows you to test the codegen for ordered reductions in this change and next becomes only changing which check prefixes one line uses.

This revision is now accepted and ready to land.Feb 22 2023, 3:09 PM
reames added inline comments.Feb 22 2023, 3:12 PM
llvm/test/Transforms/LoopVectorize/RISCV/ordered-reduction.ll
3

Also, this has nothing to do with your change, but the fact that -hints-allow-reordering defaults to true is deeply and unpleasantly surprising. That is *not* the semantics I'd have expected from the loop directives.

Mel-Chen updated this revision to Diff 500152.Feb 24 2023, 5:13 AM

Rebase and add test for -force-ordered-reductions=true -hints-allow-reordering=false.

Mel-Chen marked an inline comment as done.Feb 24 2023, 5:19 AM
Mel-Chen added inline comments.
llvm/test/Transforms/LoopVectorize/RISCV/ordered-reduction.ll
3

Yes, this is news to me, and also surprise me.

Harbormaster completed remote builds in B215723: Diff 500152.Feb 24 2023, 11:57 AM
Mel-Chen updated this revision to Diff 501489.Mar 1 2023, 6:26 AM

Rebase and land.

This revision was landed with ongoing or failed builds.Mar 1 2023, 6:28 AM
Closed by commit rG9d0703a6461b: [RISCV] Pre-commit test case for ordered reduction, NFC (authored by Mel-Chen). · Explain Why
This revision was automatically updated to reflect the committed changes.
Mel-Chen added a commit: rG9d0703a6461b: [RISCV] Pre-commit test case for ordered reduction, NFC.
Harbormaster completed remote builds in B216708: Diff 501489.Mar 1 2023, 7:11 AM

Revision Contents

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llvm/
test/
Transforms/
LoopVectorize/
RISCV/
85 lines

Diff 499075

llvm/test/Transforms/LoopVectorize/RISCV/ordered-reduction.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=loop-vectorize -hints-allow-reordering=false -S < %s | FileCheck %s --check-prefix=CHECK-NOT-VECTORIZED
; RUN: opt -passes=loop-vectorize -S < %s | FileCheck %s --check-prefix=CHECK-UNORDERED
reamesUnsubmitted
Done
ReplyInline Actions

Please add a check line for the configuration: -force-ordered-reductions=true -hints-allow-reordering=false.

This allows you to test the codegen for ordered reductions in this change and next becomes only changing which check prefixes one line uses.

reames: Please add a check line for the configuration: -force-ordered-reductions=true -hints-allow…
reamesUnsubmitted
Not Done
ReplyInline Actions

Also, this has nothing to do with your change, but the fact that -hints-allow-reordering defaults to true is deeply and unpleasantly surprising. That is *not* the semantics I'd have expected from the loop directives.

reames: Also, this has nothing to do with your change, but the fact that -hints-allow-reordering…
Mel-ChenAuthorUnsubmitted
Done
ReplyInline Actions

Yes, this is news to me, and also surprise me.

Mel-Chen: Yes, this is news to me, and also surprise me.
; RUN: opt -passes=loop-vectorize -force-ordered-reductions=false -hints-allow-reordering=false -S < %s | FileCheck %s --check-prefix=CHECK-NOT-VECTORIZED
target triple = "riscv64"
define float @fadd(ptr noalias nocapture readonly %a, i64 %n) #0 {
; CHECK-UNORDERED-LABEL: @fadd(
; CHECK-UNORDERED-NEXT: entry:
; CHECK-UNORDERED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N:%.*]], 4
; CHECK-UNORDERED-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK-UNORDERED: vector.ph:
; CHECK-UNORDERED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
; CHECK-UNORDERED-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
; CHECK-UNORDERED-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK-UNORDERED: vector.body:
; CHECK-UNORDERED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-UNORDERED-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ]
; CHECK-UNORDERED-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
; CHECK-UNORDERED-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[TMP0]]
; CHECK-UNORDERED-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 0
; CHECK-UNORDERED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4
; CHECK-UNORDERED-NEXT: [[TMP3]] = fadd <4 x float> [[WIDE_LOAD]], [[VEC_PHI]]
; CHECK-UNORDERED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-UNORDERED-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-UNORDERED-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-UNORDERED: middle.block:
; CHECK-UNORDERED-NEXT: [[TMP5:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP3]])
; CHECK-UNORDERED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-UNORDERED-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]]
; CHECK-UNORDERED: scalar.ph:
; CHECK-UNORDERED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-UNORDERED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[TMP5]], [[MIDDLE_BLOCK]] ]
; CHECK-UNORDERED-NEXT: br label [[FOR_BODY:%.*]]
; CHECK-UNORDERED: for.body:
; CHECK-UNORDERED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-UNORDERED-NEXT: [[SUM_07:%.*]] = phi float [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
; CHECK-UNORDERED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]
; CHECK-UNORDERED-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX]], align 4
; CHECK-UNORDERED-NEXT: [[ADD]] = fadd float [[TMP6]], [[SUM_07]]
; CHECK-UNORDERED-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-UNORDERED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-UNORDERED-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK-UNORDERED: for.end:
; CHECK-UNORDERED-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], [[FOR_BODY]] ], [ [[TMP5]], [[MIDDLE_BLOCK]] ]
; CHECK-UNORDERED-NEXT: ret float [[ADD_LCSSA]]
;
; CHECK-NOT-VECTORIZED-LABEL: @fadd(
; CHECK-NOT-VECTORIZED-NEXT: entry:
; CHECK-NOT-VECTORIZED-NEXT: br label [[FOR_BODY:%.*]]
; CHECK-NOT-VECTORIZED: for.body:
; CHECK-NOT-VECTORIZED-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NOT-VECTORIZED-NEXT: [[SUM_07:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
; CHECK-NOT-VECTORIZED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[IV]]
; CHECK-NOT-VECTORIZED-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 4
; CHECK-NOT-VECTORIZED-NEXT: [[ADD]] = fadd float [[TMP0]], [[SUM_07]]
; CHECK-NOT-VECTORIZED-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NOT-VECTORIZED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N:%.*]]
; CHECK-NOT-VECTORIZED-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-NOT-VECTORIZED: for.end:
; CHECK-NOT-VECTORIZED-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], [[FOR_BODY]] ]
; CHECK-NOT-VECTORIZED-NEXT: ret float [[ADD_LCSSA]]
;
entry:
br label %for.body
for.body:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
%sum.07 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
%arrayidx = getelementptr inbounds float, ptr %a, i64 %iv
%0 = load float, ptr %arrayidx, align 4
%add = fadd float %0, %sum.07
%iv.next = add nuw nsw i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, %n
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
for.end:
ret float %add
}
attributes #0 = { "target-features"="+f,+v" }
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.width", i32 4}
!2 = !{!"llvm.loop.interleave.count", i32 1}