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Differential D144198

[AMDGPU] Check exact width in get*ClassForBitWidth
AbandonedPublic

Authored by foad on Feb 16 2023, 8:47 AM.

Details

Reviewers
arsenm
Group Reviewers
Restricted Project

Diff Detail

Unit TestsFailed

TimeTest
4,840 msx64 debian > LLVM.CodeGen/AMDGPU/GlobalISel::extractelement.ll
5,610 msx64 debian > LLVM.CodeGen/AMDGPU/GlobalISel::insertelement.ll

Event Timeline

foad created this revision.Feb 16 2023, 8:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 16 2023, 8:47 AM
Herald added subscribers: kosarev, StephenFan, kerbowa and 7 others. · View Herald Transcript
foad requested review of this revision.Feb 16 2023, 8:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 16 2023, 8:47 AM
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foad added reviewers: Restricted Project, arsenm.Feb 16 2023, 8:51 AM

This is an RFC to check my intuition that we really want exact matches here - there should not be any cases where we return a wider class than was asked for. In particular, we have SGPR classes corresponding to every VGPR class width.

Currently this causes a couple of test failures:

LLVM :: CodeGen/AMDGPU/GlobalISel/extractelement.ll
LLVM :: CodeGen/AMDGPU/GlobalISel/insertelement.ll

The failure mode is like:

LLVM ERROR: cannot select: %29:sreg_32(s32), %30:sreg_32(s32), %31:sreg_32(s32), %32:sreg_32(s32), %33:sreg_32(s32), %34:sreg_32(s32), %35:sreg_32(s32), %36:sreg_32(s32), %37:sreg_32(s32), %38:sreg_32(s32), %39:sreg_32(s32), %40:sreg_32(s32), %41:sreg_32(s32), %42:sreg_32(s32) = G_UNMERGE_VALUES %28:sgpr(<7 x s64>) (in function: dyn_insertelement_v7f64_s_s_s)

I guess this a globalisel legalization problem. We don't have any 448-bit register classes corresponding to the <7 x s64> on the RHS of this instruction, so maybe legalization should have widened it to <8 x s64>?

arsenm accepted this revision.Feb 16 2023, 9:08 AM

LGTM. I think only the <= case would make sense to handle 16/32

This revision is now accepted and ready to land.Feb 16 2023, 9:08 AM
Harbormaster completed remote builds in B214173: Diff 498044.Feb 16 2023, 10:39 AM
matejam added a parent revision: D148096: [AMDGPU][GlobalISel] Check exact width in get*ClassForBitWidth and widen if necessary.Apr 12 2023, 2:45 AM
matejam mentioned this in D148096: [AMDGPU][GlobalISel] Check exact width in get*ClassForBitWidth and widen if necessary.Apr 20 2023, 7:51 AM
matejam removed a parent revision: D148096: [AMDGPU][GlobalISel] Check exact width in get*ClassForBitWidth and widen if necessary.
foad planned changes to this revision.Apr 24 2023, 6:43 AM
In D144198#4132341, @foad wrote:

Currently this causes a couple of test failures:

LLVM :: CodeGen/AMDGPU/GlobalISel/extractelement.ll
LLVM :: CodeGen/AMDGPU/GlobalISel/insertelement.ll

This patch will probably be superseded by D148096 which aims to fix those failures.

foad abandoned this revision.Aug 7 2023, 6:07 AM

This patch will probably be superseded by D148096 which aims to fix those failures.

Yup, superseded.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
198 lines

Diff 498044

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Show First 20 Lines • Show All 2,511 Lines • ▼ Show 20 Lines
} }
StringRef SIRegisterInfo::getRegAsmName(MCRegister Reg) const { StringRef SIRegisterInfo::getRegAsmName(MCRegister Reg) const {
return AMDGPUInstPrinter::getRegisterName(Reg); return AMDGPUInstPrinter::getRegisterName(Reg);
} }
static const TargetRegisterClass * static const TargetRegisterClass *
getAnyVGPRClassForBitWidth(unsigned BitWidth) { getAnyVGPRClassForBitWidth(unsigned BitWidth) {
if (BitWidth <= 64) if (BitWidth == 64)
return &AMDGPU::VReg_64RegClass; return &AMDGPU::VReg_64RegClass;
if (BitWidth <= 96) if (BitWidth == 96)
return &AMDGPU::VReg_96RegClass; return &AMDGPU::VReg_96RegClass;
if (BitWidth <= 128) if (BitWidth == 128)
return &AMDGPU::VReg_128RegClass; return &AMDGPU::VReg_128RegClass;
if (BitWidth <= 160) if (BitWidth == 160)
return &AMDGPU::VReg_160RegClass; return &AMDGPU::VReg_160RegClass;
if (BitWidth <= 192) if (BitWidth == 192)
return &AMDGPU::VReg_192RegClass; return &AMDGPU::VReg_192RegClass;
if (BitWidth <= 224) if (BitWidth == 224)
return &AMDGPU::VReg_224RegClass; return &AMDGPU::VReg_224RegClass;
if (BitWidth <= 256) if (BitWidth == 256)
return &AMDGPU::VReg_256RegClass; return &AMDGPU::VReg_256RegClass;
if (BitWidth <= 288) if (BitWidth == 288)
return &AMDGPU::VReg_288RegClass; return &AMDGPU::VReg_288RegClass;
if (BitWidth <= 320) if (BitWidth == 320)
return &AMDGPU::VReg_320RegClass; return &AMDGPU::VReg_320RegClass;
if (BitWidth <= 352) if (BitWidth == 352)
return &AMDGPU::VReg_352RegClass; return &AMDGPU::VReg_352RegClass;
if (BitWidth <= 384) if (BitWidth == 384)
return &AMDGPU::VReg_384RegClass; return &AMDGPU::VReg_384RegClass;
if (BitWidth <= 512) if (BitWidth == 512)
return &AMDGPU::VReg_512RegClass; return &AMDGPU::VReg_512RegClass;
if (BitWidth <= 1024) if (BitWidth == 1024)
return &AMDGPU::VReg_1024RegClass; return &AMDGPU::VReg_1024RegClass;
return nullptr; return nullptr;
} }
static const TargetRegisterClass * static const TargetRegisterClass *
getAlignedVGPRClassForBitWidth(unsigned BitWidth) { getAlignedVGPRClassForBitWidth(unsigned BitWidth) {
if (BitWidth <= 64) if (BitWidth == 64)
return &AMDGPU::VReg_64_Align2RegClass; return &AMDGPU::VReg_64_Align2RegClass;
if (BitWidth <= 96) if (BitWidth == 96)
return &AMDGPU::VReg_96_Align2RegClass; return &AMDGPU::VReg_96_Align2RegClass;
if (BitWidth <= 128) if (BitWidth == 128)
return &AMDGPU::VReg_128_Align2RegClass; return &AMDGPU::VReg_128_Align2RegClass;
if (BitWidth <= 160) if (BitWidth == 160)
return &AMDGPU::VReg_160_Align2RegClass; return &AMDGPU::VReg_160_Align2RegClass;
if (BitWidth <= 192) if (BitWidth == 192)
return &AMDGPU::VReg_192_Align2RegClass; return &AMDGPU::VReg_192_Align2RegClass;
if (BitWidth <= 224) if (BitWidth == 224)
return &AMDGPU::VReg_224_Align2RegClass; return &AMDGPU::VReg_224_Align2RegClass;
if (BitWidth <= 256) if (BitWidth == 256)
return &AMDGPU::VReg_256_Align2RegClass; return &AMDGPU::VReg_256_Align2RegClass;
if (BitWidth <= 288) if (BitWidth == 288)
return &AMDGPU::VReg_288_Align2RegClass; return &AMDGPU::VReg_288_Align2RegClass;
if (BitWidth <= 320) if (BitWidth == 320)
return &AMDGPU::VReg_320_Align2RegClass; return &AMDGPU::VReg_320_Align2RegClass;
if (BitWidth <= 352) if (BitWidth == 352)
return &AMDGPU::VReg_352_Align2RegClass; return &AMDGPU::VReg_352_Align2RegClass;
if (BitWidth <= 384) if (BitWidth == 384)
return &AMDGPU::VReg_384_Align2RegClass; return &AMDGPU::VReg_384_Align2RegClass;
if (BitWidth <= 512) if (BitWidth == 512)
return &AMDGPU::VReg_512_Align2RegClass; return &AMDGPU::VReg_512_Align2RegClass;
if (BitWidth <= 1024) if (BitWidth == 1024)
return &AMDGPU::VReg_1024_Align2RegClass; return &AMDGPU::VReg_1024_Align2RegClass;
return nullptr; return nullptr;
} }
const TargetRegisterClass * const TargetRegisterClass *
SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) const { SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) const {
if (BitWidth == 1) if (BitWidth == 1)
return &AMDGPU::VReg_1RegClass; return &AMDGPU::VReg_1RegClass;
if (BitWidth <= 16) if (BitWidth == 16)
return &AMDGPU::VGPR_LO16RegClass; return &AMDGPU::VGPR_LO16RegClass;
if (BitWidth <= 32) if (BitWidth == 32)
return &AMDGPU::VGPR_32RegClass; return &AMDGPU::VGPR_32RegClass;
return ST.needsAlignedVGPRs() ? getAlignedVGPRClassForBitWidth(BitWidth) return ST.needsAlignedVGPRs() ? getAlignedVGPRClassForBitWidth(BitWidth)
: getAnyVGPRClassForBitWidth(BitWidth); : getAnyVGPRClassForBitWidth(BitWidth);
} }
static const TargetRegisterClass * static const TargetRegisterClass *
getAnyAGPRClassForBitWidth(unsigned BitWidth) { getAnyAGPRClassForBitWidth(unsigned BitWidth) {
if (BitWidth <= 64) if (BitWidth == 64)
return &AMDGPU::AReg_64RegClass; return &AMDGPU::AReg_64RegClass;
if (BitWidth <= 96) if (BitWidth == 96)
return &AMDGPU::AReg_96RegClass; return &AMDGPU::AReg_96RegClass;
if (BitWidth <= 128) if (BitWidth == 128)
return &AMDGPU::AReg_128RegClass; return &AMDGPU::AReg_128RegClass;
if (BitWidth <= 160) if (BitWidth == 160)
return &AMDGPU::AReg_160RegClass; return &AMDGPU::AReg_160RegClass;
if (BitWidth <= 192) if (BitWidth == 192)
return &AMDGPU::AReg_192RegClass; return &AMDGPU::AReg_192RegClass;
if (BitWidth <= 224) if (BitWidth == 224)
return &AMDGPU::AReg_224RegClass; return &AMDGPU::AReg_224RegClass;
if (BitWidth <= 256) if (BitWidth == 256)
return &AMDGPU::AReg_256RegClass; return &AMDGPU::AReg_256RegClass;
if (BitWidth <= 288) if (BitWidth == 288)
return &AMDGPU::AReg_288RegClass; return &AMDGPU::AReg_288RegClass;
if (BitWidth <= 320) if (BitWidth == 320)
return &AMDGPU::AReg_320RegClass; return &AMDGPU::AReg_320RegClass;
if (BitWidth <= 352) if (BitWidth == 352)
return &AMDGPU::AReg_352RegClass; return &AMDGPU::AReg_352RegClass;
if (BitWidth <= 384) if (BitWidth == 384)
return &AMDGPU::AReg_384RegClass; return &AMDGPU::AReg_384RegClass;
if (BitWidth <= 512) if (BitWidth == 512)
return &AMDGPU::AReg_512RegClass; return &AMDGPU::AReg_512RegClass;
if (BitWidth <= 1024) if (BitWidth == 1024)
return &AMDGPU::AReg_1024RegClass; return &AMDGPU::AReg_1024RegClass;
return nullptr; return nullptr;
} }
static const TargetRegisterClass * static const TargetRegisterClass *
getAlignedAGPRClassForBitWidth(unsigned BitWidth) { getAlignedAGPRClassForBitWidth(unsigned BitWidth) {
if (BitWidth <= 64) if (BitWidth == 64)
return &AMDGPU::AReg_64_Align2RegClass; return &AMDGPU::AReg_64_Align2RegClass;
if (BitWidth <= 96) if (BitWidth == 96)
return &AMDGPU::AReg_96_Align2RegClass; return &AMDGPU::AReg_96_Align2RegClass;
if (BitWidth <= 128) if (BitWidth == 128)
return &AMDGPU::AReg_128_Align2RegClass; return &AMDGPU::AReg_128_Align2RegClass;
if (BitWidth <= 160) if (BitWidth == 160)
return &AMDGPU::AReg_160_Align2RegClass; return &AMDGPU::AReg_160_Align2RegClass;
if (BitWidth <= 192) if (BitWidth == 192)
return &AMDGPU::AReg_192_Align2RegClass; return &AMDGPU::AReg_192_Align2RegClass;
if (BitWidth <= 224) if (BitWidth == 224)
return &AMDGPU::AReg_224_Align2RegClass; return &AMDGPU::AReg_224_Align2RegClass;
if (BitWidth <= 256) if (BitWidth == 256)
return &AMDGPU::AReg_256_Align2RegClass; return &AMDGPU::AReg_256_Align2RegClass;
if (BitWidth <= 288) if (BitWidth == 288)
return &AMDGPU::AReg_288_Align2RegClass; return &AMDGPU::AReg_288_Align2RegClass;
if (BitWidth <= 320) if (BitWidth == 320)
return &AMDGPU::AReg_320_Align2RegClass; return &AMDGPU::AReg_320_Align2RegClass;
if (BitWidth <= 352) if (BitWidth == 352)
return &AMDGPU::AReg_352_Align2RegClass; return &AMDGPU::AReg_352_Align2RegClass;
if (BitWidth <= 384) if (BitWidth == 384)
return &AMDGPU::AReg_384_Align2RegClass; return &AMDGPU::AReg_384_Align2RegClass;
if (BitWidth <= 512) if (BitWidth == 512)
return &AMDGPU::AReg_512_Align2RegClass; return &AMDGPU::AReg_512_Align2RegClass;
if (BitWidth <= 1024) if (BitWidth == 1024)
return &AMDGPU::AReg_1024_Align2RegClass; return &AMDGPU::AReg_1024_Align2RegClass;
return nullptr; return nullptr;
} }
const TargetRegisterClass * const TargetRegisterClass *
SIRegisterInfo::getAGPRClassForBitWidth(unsigned BitWidth) const { SIRegisterInfo::getAGPRClassForBitWidth(unsigned BitWidth) const {
if (BitWidth <= 16) if (BitWidth == 16)
return &AMDGPU::AGPR_LO16RegClass; return &AMDGPU::AGPR_LO16RegClass;
if (BitWidth <= 32) if (BitWidth == 32)
return &AMDGPU::AGPR_32RegClass; return &AMDGPU::AGPR_32RegClass;
return ST.needsAlignedVGPRs() ? getAlignedAGPRClassForBitWidth(BitWidth) return ST.needsAlignedVGPRs() ? getAlignedAGPRClassForBitWidth(BitWidth)
: getAnyAGPRClassForBitWidth(BitWidth); : getAnyAGPRClassForBitWidth(BitWidth);
} }
static const TargetRegisterClass * static const TargetRegisterClass *
getAnyVectorSuperClassForBitWidth(unsigned BitWidth) { getAnyVectorSuperClassForBitWidth(unsigned BitWidth) {
if (BitWidth <= 64) if (BitWidth == 64)
return &AMDGPU::AV_64RegClass; return &AMDGPU::AV_64RegClass;
if (BitWidth <= 96) if (BitWidth == 96)
return &AMDGPU::AV_96RegClass; return &AMDGPU::AV_96RegClass;
if (BitWidth <= 128) if (BitWidth == 128)
return &AMDGPU::AV_128RegClass; return &AMDGPU::AV_128RegClass;
if (BitWidth <= 160) if (BitWidth == 160)
return &AMDGPU::AV_160RegClass; return &AMDGPU::AV_160RegClass;
if (BitWidth <= 192) if (BitWidth == 192)
return &AMDGPU::AV_192RegClass; return &AMDGPU::AV_192RegClass;
if (BitWidth <= 224) if (BitWidth == 224)
return &AMDGPU::AV_224RegClass; return &AMDGPU::AV_224RegClass;
if (BitWidth <= 256) if (BitWidth == 256)
return &AMDGPU::AV_256RegClass; return &AMDGPU::AV_256RegClass;
if (BitWidth <= 288) if (BitWidth == 288)
return &AMDGPU::AV_288RegClass; return &AMDGPU::AV_288RegClass;
if (BitWidth <= 320) if (BitWidth == 320)
return &AMDGPU::AV_320RegClass; return &AMDGPU::AV_320RegClass;
if (BitWidth <= 352) if (BitWidth == 352)
return &AMDGPU::AV_352RegClass; return &AMDGPU::AV_352RegClass;
if (BitWidth <= 384) if (BitWidth == 384)
return &AMDGPU::AV_384RegClass; return &AMDGPU::AV_384RegClass;
if (BitWidth <= 512) if (BitWidth == 512)
return &AMDGPU::AV_512RegClass; return &AMDGPU::AV_512RegClass;
if (BitWidth <= 1024) if (BitWidth == 1024)
return &AMDGPU::AV_1024RegClass; return &AMDGPU::AV_1024RegClass;
return nullptr; return nullptr;
} }
static const TargetRegisterClass * static const TargetRegisterClass *
getAlignedVectorSuperClassForBitWidth(unsigned BitWidth) { getAlignedVectorSuperClassForBitWidth(unsigned BitWidth) {
if (BitWidth <= 64) if (BitWidth == 64)
return &AMDGPU::AV_64_Align2RegClass; return &AMDGPU::AV_64_Align2RegClass;
if (BitWidth <= 96) if (BitWidth == 96)
return &AMDGPU::AV_96_Align2RegClass; return &AMDGPU::AV_96_Align2RegClass;
if (BitWidth <= 128) if (BitWidth == 128)
return &AMDGPU::AV_128_Align2RegClass; return &AMDGPU::AV_128_Align2RegClass;
if (BitWidth <= 160) if (BitWidth == 160)
return &AMDGPU::AV_160_Align2RegClass; return &AMDGPU::AV_160_Align2RegClass;
if (BitWidth <= 192) if (BitWidth == 192)
return &AMDGPU::AV_192_Align2RegClass; return &AMDGPU::AV_192_Align2RegClass;
if (BitWidth <= 224) if (BitWidth == 224)
return &AMDGPU::AV_224_Align2RegClass; return &AMDGPU::AV_224_Align2RegClass;
if (BitWidth <= 256) if (BitWidth == 256)
return &AMDGPU::AV_256_Align2RegClass; return &AMDGPU::AV_256_Align2RegClass;
if (BitWidth <= 288) if (BitWidth == 288)
return &AMDGPU::AV_288_Align2RegClass; return &AMDGPU::AV_288_Align2RegClass;
if (BitWidth <= 320) if (BitWidth == 320)
return &AMDGPU::AV_320_Align2RegClass; return &AMDGPU::AV_320_Align2RegClass;
if (BitWidth <= 352) if (BitWidth == 352)
return &AMDGPU::AV_352_Align2RegClass; return &AMDGPU::AV_352_Align2RegClass;
if (BitWidth <= 384) if (BitWidth == 384)
return &AMDGPU::AV_384_Align2RegClass; return &AMDGPU::AV_384_Align2RegClass;
if (BitWidth <= 512) if (BitWidth == 512)
return &AMDGPU::AV_512_Align2RegClass; return &AMDGPU::AV_512_Align2RegClass;
if (BitWidth <= 1024) if (BitWidth == 1024)
return &AMDGPU::AV_1024_Align2RegClass; return &AMDGPU::AV_1024_Align2RegClass;
return nullptr; return nullptr;
} }
const TargetRegisterClass * const TargetRegisterClass *
SIRegisterInfo::getVectorSuperClassForBitWidth(unsigned BitWidth) const { SIRegisterInfo::getVectorSuperClassForBitWidth(unsigned BitWidth) const {
if (BitWidth <= 16) if (BitWidth == 16)
return &AMDGPU::VGPR_LO16RegClass; return &AMDGPU::VGPR_LO16RegClass;
if (BitWidth <= 32) if (BitWidth == 32)
return &AMDGPU::AV_32RegClass; return &AMDGPU::AV_32RegClass;
return ST.needsAlignedVGPRs() return ST.needsAlignedVGPRs()
? getAlignedVectorSuperClassForBitWidth(BitWidth) ? getAlignedVectorSuperClassForBitWidth(BitWidth)
: getAnyVectorSuperClassForBitWidth(BitWidth); : getAnyVectorSuperClassForBitWidth(BitWidth);
} }
const TargetRegisterClass * const TargetRegisterClass *
SIRegisterInfo::getSGPRClassForBitWidth(unsigned BitWidth) { SIRegisterInfo::getSGPRClassForBitWidth(unsigned BitWidth) {
if (BitWidth <= 16) if (BitWidth == 16)
return &AMDGPU::SGPR_LO16RegClass; return &AMDGPU::SGPR_LO16RegClass;
if (BitWidth <= 32) if (BitWidth == 32)
return &AMDGPU::SReg_32RegClass; return &AMDGPU::SReg_32RegClass;
if (BitWidth <= 64) if (BitWidth == 64)
return &AMDGPU::SReg_64RegClass; return &AMDGPU::SReg_64RegClass;
if (BitWidth <= 96) if (BitWidth == 96)
return &AMDGPU::SGPR_96RegClass; return &AMDGPU::SGPR_96RegClass;
if (BitWidth <= 128) if (BitWidth == 128)
return &AMDGPU::SGPR_128RegClass; return &AMDGPU::SGPR_128RegClass;
if (BitWidth <= 160) if (BitWidth == 160)
return &AMDGPU::SGPR_160RegClass; return &AMDGPU::SGPR_160RegClass;
if (BitWidth <= 192) if (BitWidth == 192)
return &AMDGPU::SGPR_192RegClass; return &AMDGPU::SGPR_192RegClass;
if (BitWidth <= 224) if (BitWidth == 224)
return &AMDGPU::SGPR_224RegClass; return &AMDGPU::SGPR_224RegClass;
if (BitWidth <= 256) if (BitWidth == 256)
return &AMDGPU::SGPR_256RegClass; return &AMDGPU::SGPR_256RegClass;
if (BitWidth <= 288) if (BitWidth == 288)
return &AMDGPU::SGPR_288RegClass; return &AMDGPU::SGPR_288RegClass;
if (BitWidth <= 320) if (BitWidth == 320)
return &AMDGPU::SGPR_320RegClass; return &AMDGPU::SGPR_320RegClass;
if (BitWidth <= 352) if (BitWidth == 352)
return &AMDGPU::SGPR_352RegClass; return &AMDGPU::SGPR_352RegClass;
if (BitWidth <= 384) if (BitWidth == 384)
return &AMDGPU::SGPR_384RegClass; return &AMDGPU::SGPR_384RegClass;
if (BitWidth <= 512) if (BitWidth == 512)
return &AMDGPU::SGPR_512RegClass; return &AMDGPU::SGPR_512RegClass;
if (BitWidth <= 1024) if (BitWidth == 1024)
return &AMDGPU::SGPR_1024RegClass; return &AMDGPU::SGPR_1024RegClass;
return nullptr; return nullptr;
} }
bool SIRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI, bool SIRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI,
Register Reg) const { Register Reg) const {
const TargetRegisterClass *RC; const TargetRegisterClass *RC;
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